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cameron.mcinally (Cameron McInally)
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User Since
Jan 6 2015, 6:21 AM (297 w, 3 d)

Recent Activity

Yesterday

cameron.mcinally committed rGa35c7f30769b: [SVE][WIP] Implement lowering for fixed length VSELECT to Scalable (authored by cameron.mcinally).
[SVE][WIP] Implement lowering for fixed length VSELECT to Scalable
Thu, Sep 17, 12:03 PM
cameron.mcinally closed D85364: [SVE][WIP] Implement lowering for fixed width select.
Thu, Sep 17, 12:03 PM · Restricted Project
cameron.mcinally planned changes to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.

This is certainly not the expected behaviour so I'll get it fixed.

Thu, Sep 17, 9:04 AM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Here's the most obvious choice -- glueing the new check to the AArch64ISD::EXT generation. That's good because the intention is obvious, and future code changes won't get in the way. But it could also be argued that the NEON-sized vector check should precede this entire if-else statement. I.e. the EXTRACT_SUBVECTORs have the same problem as AArch64ISD::EXT. None of this code is ready for SVE-sized fixed vectors.

Thu, Sep 17, 9:02 AM · Restricted Project

Wed, Sep 16

cameron.mcinally requested review of D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.
Wed, Sep 16, 2:15 PM · Restricted Project

Mon, Sep 14

cameron.mcinally added inline comments to D85364: [SVE][WIP] Implement lowering for fixed width select.
Mon, Sep 14, 2:13 PM · Restricted Project
cameron.mcinally added inline comments to D85364: [SVE][WIP] Implement lowering for fixed width select.
Mon, Sep 14, 7:45 AM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Remove the BUILD_VECTOR->EXTRACT_SUBVECTOR transform so that this is easier to review. Will post a separate Diff for that.

Mon, Sep 14, 7:42 AM · Restricted Project

Tue, Sep 8

cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Fix comment.

Tue, Sep 8, 8:49 AM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Turns out that ReconstructShuffle(...) needs a lot of work to be updated. The EXTRACT_SUBVECTOR index assumes we're extracting a 1/2 width vector. I missed that.

Tue, Sep 8, 8:44 AM · Restricted Project

Thu, Sep 3

cameron.mcinally added inline comments to D85364: [SVE][WIP] Implement lowering for fixed width select.
Thu, Sep 3, 8:40 AM · Restricted Project
cameron.mcinally added inline comments to D85364: [SVE][WIP] Implement lowering for fixed width select.
Thu, Sep 3, 6:35 AM · Restricted Project

Wed, Sep 2

cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Update tests -- don't use pointer args for NEON sized vectors.

Wed, Sep 2, 1:02 PM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Fix bad copy-and-paste in CHECK lines. No significant changes made.

Wed, Sep 2, 12:18 PM · Restricted Project
cameron.mcinally added a reviewer for D85364: [SVE][WIP] Implement lowering for fixed width select: t.p.northover.
Wed, Sep 2, 8:45 AM · Restricted Project
cameron.mcinally updated subscribers of D85364: [SVE][WIP] Implement lowering for fixed width select.
Wed, Sep 2, 8:45 AM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Updating Diff for recent upstream changes.

Wed, Sep 2, 8:38 AM · Restricted Project

Tue, Sep 1

cameron.mcinally committed rGcfe2b81710c4: [SVE] Update INSERT_SUBVECTOR DAGCombine to use getVectorElementCount(). (authored by cameron.mcinally).
[SVE] Update INSERT_SUBVECTOR DAGCombine to use getVectorElementCount().
Tue, Sep 1, 2:52 PM
cameron.mcinally closed D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.
Tue, Sep 1, 2:52 PM · Restricted Project
cameron.mcinally added a comment to D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.

Is there any way to write a test for the transform? Maybe not, given the limited places we use INSERT_SUBVECTOR.

Tue, Sep 1, 1:04 PM · Restricted Project
cameron.mcinally updated the diff for D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.

Updated with @david-arm's comments for Thursday's Sync-up call.

Tue, Sep 1, 9:01 AM · Restricted Project
cameron.mcinally added a comment to D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.

Thanks, David. Ok, I'll put a pin in this until Thursday's call. But yeah, isKnownMultipleOf(...) sounds fair. I'll prepare a patch to see if any surprises come up.

Tue, Sep 1, 7:19 AM · Restricted Project

Mon, Aug 31

cameron.mcinally added a comment to D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.

I don't really have an opinion on any of this. Just thinking aloud...

Mon, Aug 31, 4:23 PM · Restricted Project
cameron.mcinally updated the diff for D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.

Ok, I guess that makes sense. So if we're considering Min elements, should we just overload % then?

Mon, Aug 31, 2:47 PM · Restricted Project
cameron.mcinally requested review of D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors.
Mon, Aug 31, 1:29 PM · Restricted Project

Wed, Aug 26

cameron.mcinally added a comment to D85364: [SVE][WIP] Implement lowering for fixed width select.

˜Bah, egg on my face. You're right that D86394 fixes the immediate issue. Sorry for the noise.

Wed, Aug 26, 7:55 AM · Restricted Project

Mon, Aug 24

cameron.mcinally added a comment to D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations.

D86394 addresses a different issue, I think. Posted some new code in D85364 to expose the AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU issue.

Mon, Aug 24, 1:41 PM · Restricted Project
cameron.mcinally updated the diff for D85364: [SVE][WIP] Implement lowering for fixed width select.

Updating to exhibit the problem mentioned in D85546. One way to see the issue is:

Mon, Aug 24, 1:40 PM · Restricted Project
cameron.mcinally accepted D86415: [SVE] Lower scalable vector ISD::FNEG operations..

There is a subtle wrong answers bug with this transform, but it's something that's under development separately. That is, FMUL(X,-1.0) != FNEG(X) when FTZ is enabled. We have a flag for checking the denormal mode, namely DenormalMode. We can address it later though. @arsenm

Mon, Aug 24, 7:14 AM · Restricted Project

Fri, Aug 21

cameron.mcinally added a comment to D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations.

Eh, thinking some more, it's still a little weird:

Fri, Aug 21, 4:36 PM · Restricted Project
cameron.mcinally closed D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations.

Ah, you're right. I misread the register classes.

Fri, Aug 21, 4:20 PM · Restricted Project
cameron.mcinally reopened D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations.

These patterns might need attention. ISD::SIGN_EXTEND_INREG expects both the input and output registers to have the same type, extending the small values in place. I.e. the input is unpacked.

Fri, Aug 21, 2:47 PM · Restricted Project
cameron.mcinally committed rG36dbb8fc972f: [SVE] Lower fixed length UDIV to scalable (authored by cameron.mcinally).
[SVE] Lower fixed length UDIV to scalable
Fri, Aug 21, 7:02 AM
cameron.mcinally closed D86316: [SVE] Lower fixed length UDIV to scalable.
Fri, Aug 21, 7:01 AM · Restricted Project

Thu, Aug 20

cameron.mcinally abandoned D73978: [WIP][FPEnv] Don't transform FSUB(-0.0,X)->FNEG(X) when flushing denormals.

Abandoning this Diff since most of it was covered in D84056. Will prepare a new patch to remove the problematic FSUB DAGCombine soon.

Thu, Aug 20, 2:21 PM · Restricted Project
cameron.mcinally requested review of D86316: [SVE] Lower fixed length UDIV to scalable.
Thu, Aug 20, 1:14 PM · Restricted Project
cameron.mcinally committed rG8372e47bb968: [NFCI][SVE] Move fixed length i32/i64 SDIV tests (authored by cameron.mcinally).
[NFCI][SVE] Move fixed length i32/i64 SDIV tests
Thu, Aug 20, 12:46 PM
cameron.mcinally committed rGac6395946060: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable (authored by cameron.mcinally).
[SVE] Lower fixed length vXi8/vXi16 SDIV to scalable
Thu, Aug 20, 11:47 AM
cameron.mcinally closed D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.
Thu, Aug 20, 11:47 AM · Restricted Project
cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

Oh, but to be fair, I didn't use DAG.SplitVector(Op.getOperand(0), DL);. So that may avoid some of the ugly expanding.

Thu, Aug 20, 11:15 AM · Restricted Project
cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

That said the custom lowering for i8/i16 doesn't have to be SVE specific as there's the alternative approach of using normal ISD nodes to do the widening so that only the final SDIV lowering is SVE specific.

Thu, Aug 20, 11:13 AM · Restricted Project

Wed, Aug 19

cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

We also need a peep for the smaller vectors, where the extend can fit in one register.

Wed, Aug 19, 7:47 PM · Restricted Project

Aug 19 2020

cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

The end result is a big uglier than I would have hoped for, but I can't think of any particularly better way given the constraints.

Aug 19 2020, 1:36 PM · Restricted Project
cameron.mcinally accepted D86204: [SVE] Add ISEL patterns for predicated shifts by an immediate..

LGTM

Aug 19 2020, 1:10 PM · Restricted Project
cameron.mcinally updated the diff for D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

Updated DIV lowering to make use of correct fixed length predicates.

Aug 19 2020, 10:56 AM · Restricted Project

Aug 18 2020

cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

Ok, I see it now. We have to explicitly call LowerToPredicatedOp(...) with the fixed types still intact, so that getPredicateForVector(...) will generate the correct predicate. Will update...

Aug 18 2020, 9:25 AM · Restricted Project
cameron.mcinally added inline comments to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.
Aug 18 2020, 9:22 AM · Restricted Project
cameron.mcinally added inline comments to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.
Aug 18 2020, 9:19 AM · Restricted Project

Aug 17 2020

cameron.mcinally added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

I don't see any obvious difference in the RUN lines?

Aug 17 2020, 5:06 PM · Restricted Project
cameron.mcinally requested review of D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.
Aug 17 2020, 3:02 PM · Restricted Project

Aug 14 2020

cameron.mcinally committed rG92593f9e77c3: [SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors. (authored by cameron.mcinally).
[SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors.
Aug 14 2020, 4:48 PM
cameron.mcinally closed D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV.
Aug 14 2020, 4:47 PM · Restricted Project
cameron.mcinally updated the diff for D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV.

Remove unneeded braces.

Aug 14 2020, 2:27 PM · Restricted Project
cameron.mcinally added inline comments to D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV.
Aug 14 2020, 11:41 AM · Restricted Project
cameron.mcinally updated the diff for D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV.

Remove UDIV setOperationAction.

Aug 14 2020, 11:40 AM · Restricted Project
cameron.mcinally requested review of D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV.
Aug 14 2020, 11:17 AM · Restricted Project

Aug 13 2020

cameron.mcinally committed rG21810b0e1428: [SVE] Lower fixed length vector integer UMIN/UMAX (authored by cameron.mcinally).
[SVE] Lower fixed length vector integer UMIN/UMAX
Aug 13 2020, 12:49 PM
cameron.mcinally closed D85926: [SVE] Lower fixed length vector integer UMIN/UMAX.
Aug 13 2020, 12:48 PM · Restricted Project
cameron.mcinally requested review of D85926: [SVE] Lower fixed length vector integer UMIN/UMAX.
Aug 13 2020, 12:39 PM · Restricted Project
cameron.mcinally committed rGe1a87f0a9bc3: [SVE] Lower fixed length vector integer SMIN/SMAX (authored by cameron.mcinally).
[SVE] Lower fixed length vector integer SMIN/SMAX
Aug 13 2020, 9:41 AM
cameron.mcinally closed D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.
Aug 13 2020, 9:41 AM · Restricted Project
cameron.mcinally added inline comments to D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.
Aug 13 2020, 9:00 AM · Restricted Project
cameron.mcinally added inline comments to D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.
Aug 13 2020, 8:32 AM · Restricted Project
cameron.mcinally updated the diff for D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.

Updated patch based on Paul's comments.

Aug 13 2020, 8:30 AM · Restricted Project
cameron.mcinally added a comment to D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.

Actually, I made a mistake. New patch coming soon...

Aug 13 2020, 8:16 AM · Restricted Project
cameron.mcinally updated the diff for D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.

Updated based on Paul's review. Inline comments to come shortly...

Aug 13 2020, 8:10 AM · Restricted Project

Aug 12 2020

cameron.mcinally accepted D85831: [SVE] Lower fixed length vector integer ISD::SETCC operations..

LGTM

Aug 12 2020, 2:46 PM · Restricted Project
cameron.mcinally requested review of D85855: [SVE] Lower fixed length vector integer SMIN/SMAX.
Aug 12 2020, 2:34 PM · Restricted Project
cameron.mcinally committed rGce2c991061bf: [SVE] Lower fixed length FP minnum/maxnum (authored by cameron.mcinally).
[SVE] Lower fixed length FP minnum/maxnum
Aug 12 2020, 10:03 AM
cameron.mcinally closed D85744: [SVE] Lower fixed length FP minnum/maxnum.
Aug 12 2020, 10:03 AM · Restricted Project

Aug 11 2020

cameron.mcinally added a comment to D85709: [InstSimplify] Implement Instruction simplification for X/sqrt(X) to sqrt(X)..

After looking at the codegen, I'm not sure if we can do this transform in IR with the expected performance in codegen because the transform loses information:
https://godbolt.org/z/7b84rG

The codegen for the case of "sqrt(x)" has to account for a 0.0 input. Ie, we filter out a 0.0 (or potentially denorm) input to avoid the NAN answer that we would get from "0.0 / 0.0". But the codegen for the case of "x/sqrt(x)" does not have to do that - NAN is the correct answer for a 0.0 input, so the code has implicitly signaled to us that 0.0 is not a valid input when compiled with -ffast-math (we can ignore possible NANs).

It might help to see the motivating code that produces the x/sqrt(x) pattern to see if there's something else we should be doing there.

Aug 11 2020, 1:03 PM · Restricted Project
cameron.mcinally added inline comments to D85744: [SVE] Lower fixed length FP minnum/maxnum.
Aug 11 2020, 12:25 PM · Restricted Project
cameron.mcinally updated the diff for D85744: [SVE] Lower fixed length FP minnum/maxnum.

Update based on @paulwalker-arm's comments.

Aug 11 2020, 12:22 PM · Restricted Project
cameron.mcinally requested review of D85744: [SVE] Lower fixed length FP minnum/maxnum.
Aug 11 2020, 9:10 AM · Restricted Project
cameron.mcinally added a comment to D85709: [InstSimplify] Implement Instruction simplification for X/sqrt(X) to sqrt(X)..

Yeah, separate patch is okay. A SQRT+DIV is definitely bad.

Aug 11 2020, 7:49 AM · Restricted Project
cameron.mcinally added a comment to D85709: [InstSimplify] Implement Instruction simplification for X/sqrt(X) to sqrt(X)..

I'm fairly sure this transform is a performance loss. For a target like Skylake Server, a SQRT(x) can take up to 20 cycles. But a RSQRT(x) is about 6 cycles and a MUL(y) is 4 cycles. We'd be better off with a X*RSQRT(X).

That is up to backends to decide. InstSimplify/InstCombine (and a few others) are canonicalization, target-independent passes.
A single sqrt(x) is more canonical IR than x/sqrt(x), because it's less instructions and x has less uses.

Aug 11 2020, 7:31 AM · Restricted Project
cameron.mcinally added a comment to D85709: [InstSimplify] Implement Instruction simplification for X/sqrt(X) to sqrt(X)..

I'm fairly sure this transform is a performance loss. For a target like Skylake Server, a SQRT(x) can take up to 20 cycles. But a RSQRT(x) is about 6 cycles and a MUL(y) is 4 cycles. We'd be better off with a X*RSQRT(X).

Aug 11 2020, 7:19 AM · Restricted Project

Aug 10 2020

cameron.mcinally added a comment to D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2]..

MIN/MAX and DIVs are up my alley. I'll try those. Will check out VREDUCE if I get through the others.

Aug 10 2020, 12:14 PM · Restricted Project, Restricted Project
cameron.mcinally added a comment to D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2]..

@cameron.mcinally this is the patch I mentioned the other day, which contains the nodes where once I've written suitable tests I'll push separate patches for.

Aug 10 2020, 9:15 AM · Restricted Project, Restricted Project

Aug 7 2020

cameron.mcinally abandoned D85558: [SVE] Implement fixed-width ZEXT lowering.
Aug 7 2020, 4:34 PM · Restricted Project
cameron.mcinally updated the summary of D85558: [SVE] Implement fixed-width ZEXT lowering.
Aug 7 2020, 3:27 PM · Restricted Project
cameron.mcinally requested review of D85558: [SVE] Implement fixed-width ZEXT lowering.
Aug 7 2020, 2:24 PM · Restricted Project

Aug 6 2020

cameron.mcinally abandoned D85460: [SVE] No need to AND(X, 0x1) when truncating a scalable mask.

Ah, okay. So it's not safe to assume that the truncate to i1 is a mask. Makes sense.

Aug 6 2020, 11:52 AM · Restricted Project
cameron.mcinally requested review of D85460: [SVE] No need to AND(X, 0x1) when truncating a scalable mask.
Aug 6 2020, 11:40 AM · Restricted Project
cameron.mcinally added a comment to D85364: [SVE][WIP] Implement lowering for fixed width select.

At VL=512, the v8i1 mask will be promoted to v8i64. In order to lower this to a scalable mask, we'd need to insert the v8i64 subvector into a nxv2i64. And then truncate that ZPR by performing a CMPNE against 0, to get the final nxv2i1 mask. Between the zero extend to promote the vXi1 mask, and the truncate to get back to a nxvXi1, there's a lot of extra instructions.

I had this concern when I was reviewing the code in question. @paulwalker-arm said he found the conversions were usually folded away in his prototype. Most i1 vectors will be produced by a compare that returns an nxv2i1 or something like that.

I guess if it is amortized away, it's not a big deal. But a CMPNE is 4 cycles and a SX is 4 cycles. So we have an 8 cycle no-op. That's not great.

Folded away, as in, DAGCombine gets rid of the extra instructions. If that doesn't work right now, we should be able to make it work with a little more code.

Aug 6 2020, 8:48 AM · Restricted Project

Aug 5 2020

cameron.mcinally added a comment to D85364: [SVE][WIP] Implement lowering for fixed width select.

For load <8 x i1> specifically, the code is terrible because we're using the generic target-independent expansion, which goes element by element. If we cared, we could custom-lower it to something more reasonable. Nobody has looked into it because there isn't any way to generate that operation from C code.

Aug 5 2020, 4:29 PM · Restricted Project
cameron.mcinally added a comment to D85364: [SVE][WIP] Implement lowering for fixed width select.

For this IR test and -aarch64-sve-vector-bits-min=512:

Aug 5 2020, 3:08 PM · Restricted Project
cameron.mcinally requested review of D85364: [SVE][WIP] Implement lowering for fixed width select.
Aug 5 2020, 2:57 PM · Restricted Project

Aug 4 2020

cameron.mcinally committed rG0f2b47b6da0b: [FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel (authored by cameron.mcinally).
[FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel
Aug 4 2020, 12:43 PM
cameron.mcinally closed D85149: [FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel.
Aug 4 2020, 12:43 PM · Restricted Project
cameron.mcinally added inline comments to D85149: [FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel.
Aug 4 2020, 12:17 PM · Restricted Project
cameron.mcinally added a comment to D85139: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel..

Ah, ok. Tests removed with:

Aug 4 2020, 9:34 AM · Restricted Project
cameron.mcinally committed rG724b035fe4df: [GlobalISel] Remove redundant FNEG tests. (authored by cameron.mcinally).
[GlobalISel] Remove redundant FNEG tests.
Aug 4 2020, 9:34 AM
cameron.mcinally committed rG23adbac9ee23: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel. (authored by cameron.mcinally).
[GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel.
Aug 4 2020, 9:28 AM
cameron.mcinally closed D85139: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel..
Aug 4 2020, 9:27 AM · Restricted Project
cameron.mcinally added a comment to D85139: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel..

I think this leaves behind a redundant test_fneg/test_fneg_fmf case elsewhere

Aug 4 2020, 9:25 AM · Restricted Project
cameron.mcinally accepted D85117: [SVE] Add lowering for fixed length vector and, or & xor operations..

LGTM

Aug 4 2020, 7:24 AM · Restricted Project

Aug 3 2020

cameron.mcinally requested review of D85149: [FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel.
Aug 3 2020, 12:37 PM · Restricted Project
cameron.mcinally added a comment to D85117: [SVE] Add lowering for fixed length vector and, or & xor operations..

I have mixed feelings out this patch. Ideally I would like everything lowered to _PRED nodes and then let ISel decide which instruction best does the job. Unfortunately I could not see a clear way to write a pattern where one of the inputs is ignored. Am I missing something obvious here? if not then I guess this patch will have to do.

Aug 3 2020, 9:32 AM · Restricted Project
cameron.mcinally updated the summary of D85139: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel..
Aug 3 2020, 8:54 AM · Restricted Project