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cameron.mcinally (Cameron McInally)
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User Since
Jan 6 2015, 6:21 AM (315 w, 3 d)

Recent Activity

Tue, Jan 19

cameron.mcinally updated subscribers of D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

Having said that, I wonder if we should revisit the idea of allowing shuffle vectors to accept step vector masks?

Tue, Jan 19, 1:21 PM · Restricted Project

Fri, Jan 15

cameron.mcinally added a comment to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.

In D94444, @paulwalker-arm proposed a more generic extract vector intrinsic that accepts an index and stride. Now I'm wondering if we should just have a generic scalable shuffle vector intrinsic to handle all these operations under one intrinsic.

Fri, Jan 15, 8:27 AM · Restricted Project

Thu, Jan 14

cameron.mcinally added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Thu, Jan 14, 12:37 PM · Restricted Project
cameron.mcinally added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

A bit of a flyby review as I'm still on holidays but to my mind many of the restrictions being proposed for the new intrinsic seem purely down to the design decision of splitting the input vector across two operands. I understand this is how the underlying instructions work for SVE but that does not seem like a good enough reason to compromise the IR.

So my first questions are whether the IR and ISD interfaces need to match and from an IR point of view what is the expected usage?

Thu, Jan 14, 8:10 AM · Restricted Project

Wed, Jan 13

cameron.mcinally added inline comments to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.
Wed, Jan 13, 10:25 AM · Restricted Project
cameron.mcinally updated the diff for D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

Add known minimum number of elements restrictions...

Wed, Jan 13, 10:24 AM · Restricted Project

Tue, Jan 12

cameron.mcinally updated the diff for D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

Updated to @david-arm's suggested naming scheme...

Tue, Jan 12, 1:49 PM · Restricted Project
cameron.mcinally accepted D94504: [SVE] Add ISel pattern for addvl.

I'm assuming scheduling the new addvls closer to their uses is a register pressure win?

Tue, Jan 12, 1:14 PM · Restricted Project
cameron.mcinally updated the diff for D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

Address some of @sdesmalen's comments, but deferring name changes...

Tue, Jan 12, 9:02 AM · Restricted Project
cameron.mcinally added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

Thanks for creating this patch!

I chose to extract the even elements from a pair of vectors (full vector result), rather than a single vector (1/2 width vector result). This is in line with existing fixed shuffle vectors. And can be extended to accept an undef argument if needed. The motivation behind this decision was that we'd want the result vector to be a full vector for performance reasons. It would also map well to SVE's LD2 and UZP1.

Are you also planning to add intrinsics for interleaving?

Tue, Jan 12, 7:30 AM · Restricted Project

Mon, Jan 11

cameron.mcinally requested review of D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.
Mon, Jan 11, 12:51 PM · Restricted Project

Thu, Jan 7

cameron.mcinally added a comment to D94193: [SVE] Unpacked scalable floating point ZIP/UZP/TRN.

Please can you add entries for nxv2f16 as well? That way all the legal fp types are covered.

Thu, Jan 7, 7:58 AM · Restricted Project
cameron.mcinally committed rGf4013359b3da: [SVE] Add unpacked scalable floating point ZIP/UZP/TRN patterns (authored by cameron.mcinally).
[SVE] Add unpacked scalable floating point ZIP/UZP/TRN patterns
Thu, Jan 7, 7:57 AM
cameron.mcinally closed D94193: [SVE] Unpacked scalable floating point ZIP/UZP/TRN.
Thu, Jan 7, 7:57 AM · Restricted Project

Wed, Jan 6

cameron.mcinally requested review of D94193: [SVE] Unpacked scalable floating point ZIP/UZP/TRN.
Wed, Jan 6, 1:30 PM · Restricted Project

Mon, Jan 4

cameron.mcinally committed rG92be640bd7d4: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are… (authored by cameron.mcinally).
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are…
Mon, Jan 4, 12:44 PM
cameron.mcinally closed D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.
Mon, Jan 4, 12:44 PM · Restricted Project
cameron.mcinally accepted D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..

LGTM

Mon, Jan 4, 7:57 AM · Restricted Project
cameron.mcinally added a comment to D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.

Ping.

Mon, Jan 4, 7:49 AM · Restricted Project

Sat, Dec 26

cameron.mcinally added inline comments to D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Sat, Dec 26, 9:46 AM · Restricted Project

Dec 17 2020

cameron.mcinally updated the diff for D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.

Add FIXME comment.

Dec 17 2020, 8:51 AM · Restricted Project

Dec 15 2020

cameron.mcinally added inline comments to D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.
Dec 15 2020, 7:41 AM · Restricted Project

Dec 14 2020

cameron.mcinally retitled D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed from [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are preserved to [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.
Dec 14 2020, 2:02 PM · Restricted Project
cameron.mcinally requested review of D93243: [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed.
Dec 14 2020, 2:01 PM · Restricted Project

Dec 11 2020

cameron.mcinally accepted D93050: [SVE][CodeGen] Lower scalable floating-point vector reductions.

LGTM

Dec 11 2020, 7:17 AM · Restricted Project

Dec 10 2020

cameron.mcinally added a comment to D93050: [SVE][CodeGen] Lower scalable floating-point vector reductions.

LGTM with one nit below...

Dec 10 2020, 1:29 PM · Restricted Project

Dec 4 2020

cameron.mcinally accepted D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.

I think @ctetreau's "first class citizen" argument on the RFC has merit though. But this patch is a good first step if we're not ready to extend ShuffleVector yet. I personally would like to see ShuffleVector extended eventually, since it would be easier to optimize.

Dec 4 2020, 9:54 AM · Restricted Project

Dec 1 2020

cameron.mcinally added a comment to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.

Do we need to protect against mismatched element types? Or does legalization handle those exts/truncs?

Dec 1 2020, 8:24 AM · Restricted Project

Nov 12 2020

cameron.mcinally added inline comments to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.
Nov 12 2020, 10:17 AM · Restricted Project

Nov 10 2020

cameron.mcinally added inline comments to D91077: [LoopVectorizer][SVE] Vectorize a simple loop with with a scalable VF..
Nov 10 2020, 7:35 AM · Restricted Project

Nov 4 2020

cameron.mcinally committed rGc126eb7529be: [SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL (authored by cameron.mcinally).
[SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL
Nov 4 2020, 12:21 PM
cameron.mcinally closed D90644: [Legalizer][ARM][AArch64] Add legalizations for VECREDUCE_SEQ_FMUL.
Nov 4 2020, 12:20 PM · Restricted Project

Nov 3 2020

cameron.mcinally added a comment to D90644: [Legalizer][ARM][AArch64] Add legalizations for VECREDUCE_SEQ_FMUL.
  • In llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll and llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll, use 1.0 instead of 0.0 as the start value. That was probably a copy&paste mistake from fadds.

That caught my eye too, but the 0.0 seemed okay since we can't peep this without NSZ (-0*0) and NNAN (0*NaN). Changing it to 1.0 isn't a big deal though...

Nov 3 2020, 2:11 PM · Restricted Project
cameron.mcinally added a comment to D90644: [Legalizer][ARM][AArch64] Add legalizations for VECREDUCE_SEQ_FMUL.
  • In llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll and llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll, use 1.0 instead of 0.0 as the start value. That was probably a copy&paste mistake from fadds.
Nov 3 2020, 1:45 PM · Restricted Project
cameron.mcinally updated the diff for D90644: [Legalizer][ARM][AArch64] Add legalizations for VECREDUCE_SEQ_FMUL.

Reformat to appease pre-merge checks...

Nov 3 2020, 7:40 AM · Restricted Project

Nov 2 2020

cameron.mcinally requested review of D90644: [Legalizer][ARM][AArch64] Add legalizations for VECREDUCE_SEQ_FMUL.
Nov 2 2020, 1:45 PM · Restricted Project

Oct 30 2020

cameron.mcinally committed rGdda1e74b58bd: [Legalize] Add legalizations for VECREDUCE_SEQ_FADD (authored by cameron.mcinally).
[Legalize] Add legalizations for VECREDUCE_SEQ_FADD
Oct 30 2020, 2:03 PM
cameron.mcinally closed D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .
Oct 30 2020, 2:03 PM · Restricted Project
cameron.mcinally added inline comments to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .
Oct 30 2020, 2:02 PM · Restricted Project
cameron.mcinally added inline comments to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .
Oct 30 2020, 12:48 PM · Restricted Project
cameron.mcinally updated the diff for D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Update patch based on @nikic's comments...

Oct 30 2020, 12:48 PM · Restricted Project

Oct 28 2020

cameron.mcinally updated the diff for D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Updated patch with, I think, all the needed legalizations.

Oct 28 2020, 11:59 AM · Restricted Project

Oct 27 2020

cameron.mcinally added a comment to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Comment from ARM/ARMISelLowering.cpp:

Oct 27 2020, 2:41 PM · Restricted Project
cameron.mcinally added a comment to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Ah, I see it in ARM/. That will work...

Oct 27 2020, 11:57 AM · Restricted Project
cameron.mcinally updated the diff for D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Update 'neutral' element to -0.0.

Oct 27 2020, 11:45 AM · Restricted Project
cameron.mcinally added a comment to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

Ok, I can build that out. Are we okay with the suboptimal legalization though? I'll wait for that decision before putting more time into this.

Or does anyone see a clever fix for the illegal type legalization? It looks like we lost information during widening, so I'm not sure we can get it back in a non-hacky way.

Not sure I follow. If the neutral element is fixed, then the extra fadds should also get folded away. Or is there some additional sub-optimality here?

Oct 27 2020, 11:31 AM · Restricted Project
cameron.mcinally added a comment to D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .

A good example of this can be seen in @test_v3f32 from vecreduce-fadd-legalization-strict.ll. Here we end up with 4 FADDs, instead of the 3 FADDs required. The newly added FADD is the result of widening the illegal v3f32 vector type to v4f32, where the newly added element in the reduction is the "neutral" value, 0.0.

Looking at https://github.com/llvm/llvm-project/blob/5a3ef55a524bf9e072d98286e5febdb218b1fc72/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L7477-L7480, shouldn't this just be a matter of using -0.0 as the neutral element instead? If 0.0 is not actually neutral here, then this is not just suboptimal, it's incorrect. (We should fix this for the non-sequential case as well.)

Oct 27 2020, 10:45 AM · Restricted Project
cameron.mcinally added a reviewer for D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD : spatel.
Oct 27 2020, 10:39 AM · Restricted Project
cameron.mcinally requested review of D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD .
Oct 27 2020, 9:39 AM · Restricted Project

Oct 23 2020

cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

[1] I just wanted to highlight my previous VBITS_EQ_256-COUNT-33: fadd comment as this gives us a bit more test coverage and is something that will obviously fail (in a good way) when the splitting work is available.

Oct 23 2020, 2:25 PM · Restricted Project
cameron.mcinally committed rGa1cc274cb35f: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_SEQ_FADD operation
Oct 23 2020, 2:24 PM
cameron.mcinally closed D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.
Oct 23 2020, 2:24 PM · Restricted Project
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@paulwalker-arm, back to the splitting discussion...

Oct 23 2020, 11:01 AM · Restricted Project
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

The eventual goal here is to expand reductions during legalization only. The IR expansion exists because the DAG legalization support has been patchy historically, with VECREDUCE_SEQ_* being the last remaining hole.

Oct 23 2020, 10:53 AM · Restricted Project
cameron.mcinally updated the diff for D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Updating patch, but not ready for a serious review yet as I haven't started the splitting work. I'm still not convinced we can handle splitting appropriately with the current setup, but will comment on that seperately.

Oct 23 2020, 9:18 AM · Restricted Project
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

The new tests would be broken without the legalisation changes, so I'm assuming that those are enough coverage. Maybe I'm missing something though...

Are you sure? I took your patch for a test drive and removed all but the TLI.getOperationAction related change from Legalize*.{cpp, h} and the tests passed.

Oct 23 2020, 8:03 AM · Restricted Project

Oct 22 2020

cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Sorry @cameron.mcinally I've not had much time for code reviews this week although will take proper look tomorrow. I have a question though. You've added extra legalisation support but I don't see any explicit tests (or at least ones with matching check lines) for it. Is this something you need for this patch? (I'm guessing sve-fixed-length-fp-reduce.ll's stock NEON run line triggers the cases?) If so then there really should be a neon specific test file that verifies the widening and scalarisation changes as the NEON run line for the "fixed-length" tests is more about ensuring no SVE instructions slip through.

Oct 22 2020, 10:11 AM · Restricted Project
cameron.mcinally updated the diff for D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Try again with 80 column fix...

Oct 22 2020, 7:51 AM · Restricted Project
cameron.mcinally updated the diff for D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Fix 80 column issue. No other changes intended...

Oct 22 2020, 7:42 AM · Restricted Project

Oct 19 2020

cameron.mcinally committed rG629d1d117ae0: [SVE] Update vector reduction intrinsics in new tests. (authored by cameron.mcinally).
[SVE] Update vector reduction intrinsics in new tests.
Oct 19 2020, 11:28 AM
cameron.mcinally added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Can you update the tests to use the new non-experimental intrinsic name?

Oct 19 2020, 10:22 AM · Restricted Project
cameron.mcinally added inline comments to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.
Oct 19 2020, 9:13 AM · Restricted Project
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Some other notes:

It looks like NEON FADDA support is missing upstream too.

Oct 19 2020, 9:10 AM · Restricted Project
cameron.mcinally updated the diff for D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

This is ready for review now...

Oct 19 2020, 9:08 AM · Restricted Project

Oct 14 2020

cameron.mcinally added a comment to D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.

Not lowering to SVE for v2f## MVTs makes sense for now but as before when we have proper support for v#i1 our hands will be tied.

Oct 14 2020, 7:44 AM · Restricted Project
cameron.mcinally committed rG421f1b7294ef: [SVE] Lower fixed length VECREDUCE_FADD operation (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_FADD operation
Oct 14 2020, 7:41 AM
cameron.mcinally closed D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.
Oct 14 2020, 7:41 AM · Restricted Project

Oct 12 2020

cameron.mcinally updated the summary of D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.
Oct 12 2020, 1:02 PM · Restricted Project
cameron.mcinally requested review of D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.
Oct 12 2020, 1:01 PM · Restricted Project
cameron.mcinally committed rGabe14485fed7: [SVE] Fix VBITS_GE_256 typo in fixed-width tests. (authored by cameron.mcinally).
[SVE] Fix VBITS_GE_256 typo in fixed-width tests.
Oct 12 2020, 12:33 PM
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Oh, and I can do VECREDUCE_FADD first. Just hit VECREDUCE_SEQ_FADD before I realized I need to add 'fast' to the intrinsic calls.

Oct 12 2020, 8:40 AM · Restricted Project
cameron.mcinally added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

You're right on all the comments. I stopped midway when I hit the legalisation issue, so that's why this patch is rough. That would need to be built out first before this work could continue. And I think NEON support should be built out before that. It sounds like I'm not stepping on toes, so I'll go in that order. Thanks.

Oct 12 2020, 8:29 AM · Restricted Project
cameron.mcinally committed rG974ddb54c9ad: [SVE] Lower fixed length VECREDUCE_XOR operation (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_XOR operation
Oct 12 2020, 8:12 AM
cameron.mcinally closed D88974: [SVE] Lower fixed length VECREDUCE_XOR operation.
Oct 12 2020, 8:12 AM · Restricted Project

Oct 9 2020

cameron.mcinally requested review of D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.
Oct 9 2020, 2:00 PM · Restricted Project

Oct 7 2020

cameron.mcinally added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Legalisation tests added for sve-fixed-length-fp-reduce.ll in:

Oct 7 2020, 1:23 PM · Restricted Project
cameron.mcinally committed rG365ef499d600: [SVE] Add legalisation tests to sve-fixed-length-fp-reduce.ll (authored by cameron.mcinally).
[SVE] Add legalisation tests to sve-fixed-length-fp-reduce.ll
Oct 7 2020, 1:22 PM
cameron.mcinally updated the diff for D88974: [SVE] Lower fixed length VECREDUCE_XOR operation.

Correct OR->EOR variable name.

Oct 7 2020, 9:09 AM · Restricted Project
cameron.mcinally requested review of D88974: [SVE] Lower fixed length VECREDUCE_XOR operation.
Oct 7 2020, 9:05 AM · Restricted Project
cameron.mcinally committed rG333b2ab60b61: [SVE] Lower fixed length VECREDUCE_OR operation (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_OR operation
Oct 7 2020, 7:56 AM
cameron.mcinally closed D88847: [SVE] Lower fixed length VECREDUCE_OR operation.
Oct 7 2020, 7:56 AM · Restricted Project

Oct 5 2020

cameron.mcinally added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Legalisation tests added for sve-fixed-length-int-reduce.ll in:

Oct 5 2020, 2:06 PM · Restricted Project
cameron.mcinally committed rG6bec45e25585: [SVE] Add legalisation tests to sve-fixed-length-int-reduce.ll (authored by cameron.mcinally).
[SVE] Add legalisation tests to sve-fixed-length-int-reduce.ll
Oct 5 2020, 2:06 PM
cameron.mcinally requested review of D88847: [SVE] Lower fixed length VECREDUCE_OR operation.
Oct 5 2020, 12:50 PM · Restricted Project
cameron.mcinally accepted D88671: [SVE] Lower fixed length vector floating point rounding operations..

LGTM

Oct 5 2020, 12:46 PM · Restricted Project
cameron.mcinally added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Committed. It looks like the legalisations seem reasonable. Something like:

Oct 5 2020, 9:38 AM · Restricted Project
cameron.mcinally committed rG9642ded8ba64: [SVE] Lower fixed length VECREDUCE_AND operation (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_AND operation
Oct 5 2020, 9:34 AM
cameron.mcinally closed D88707: [SVE] Lower fixed length VECREDUCE_AND operation.
Oct 5 2020, 9:34 AM · Restricted Project

Oct 2 2020

cameron.mcinally added inline comments to D88683: [SVE] Lower fixed length vector fneg and fsqrt operations..
Oct 2 2020, 6:25 AM · Restricted Project
cameron.mcinally added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

we start adding proper v#i1 support

Oct 2 2020, 6:18 AM · Restricted Project

Oct 1 2020

cameron.mcinally requested review of D88707: [SVE] Lower fixed length VECREDUCE_AND operation.
Oct 1 2020, 3:33 PM · Restricted Project
cameron.mcinally accepted D88683: [SVE] Lower fixed length vector fneg and fsqrt operations..

LGTM

Oct 1 2020, 3:09 PM · Restricted Project

Sep 29 2020

cameron.mcinally committed rG80381c4dc925: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable (authored by cameron.mcinally).
[SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable
Sep 29 2020, 2:31 PM
cameron.mcinally closed D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Sep 29 2020, 2:31 PM · Restricted Project
cameron.mcinally added a comment to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

Ok, I think that's all of them. Looks like it started with D87796 and was buried in other changes. To confirm:

Sep 29 2020, 9:24 AM · Restricted Project
cameron.mcinally added a comment to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

Sorry again, Paul. Still looking at how far this propagated. Looks like it was introduced with the VECREDUC_ADD patch. Need some more time...

Sep 29 2020, 9:14 AM · Restricted Project
cameron.mcinally updated the diff for D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

Update more typos...

Sep 29 2020, 9:10 AM · Restricted Project
cameron.mcinally added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Sep 29 2020, 8:33 AM · Restricted Project
cameron.mcinally committed rG01c95f79424d: [SVE] Fix typo in CHECK lines for sve-fixed-length-int-reduce.ll (authored by cameron.mcinally).
[SVE] Fix typo in CHECK lines for sve-fixed-length-int-reduce.ll
Sep 29 2020, 8:25 AM
cameron.mcinally added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Sep 29 2020, 8:14 AM · Restricted Project