Add an MCTargetMachine and have it construct MC classes.

[dsanders]

Summary

All targets require a registered MCTargetMachine, even if it's just
MCTargetMachine itself.

This patch uses the Triple as the representation for the target but follow
up patches will start to break this up on a per-target basis.

A corresponding patch to clang will be committed along with this. The patch
is similar to the patches in the tools in ./tools/....

MCRelocationInfo, and MCSymbolizer has been left out of this patch since
they require special care to avoid a circular dependency between MC and
MCDisassembler.

[dsanders]

lib/Target/X86/Disassembler/X86Disassembler.cpp

996

I just noticed this redundant std::move(). I'll remove it since it's a leftover from when createX86Disassembler() created it's own redundant copy of MCInstrInfo.

[dsanders]

ping

[dsanders]

ping

[dsanders]

Refreshed patch.
During this rebase I hit a use-after-free bug in the change to
createMCDisassembler(). The change was to use the callers MCInstrInfo instead
of creating another one (only X86 and Hexagon did this) but it seems the
callers MCInstrInfo isn't preserved as long as it used to be. I've reverted
that change for now and I'll revisit it later.

[dsanders]

Virtualize each of the MCTargetMachine::create*() functions. The following
patches were going to do it anyway and doing it in this patch means that as
long as this patch makes it into LLVM 3.8, the later work can potentially
be merged without breaking the library ABI.

[• tstellarAMD]

Hi,

Can you explain why you are making this change?

[dsanders]

This patch series is the beginning of another attempt to resolve the GNU Triple
problems discussed ~4 months ago in "The Trouble with Triples"
(http://lists.llvm.org/pipermail/llvm-dev/2015-July/087700.html). The linked
thread goes into several problems which these patches set up a solution for.
It's a long read so I've tried to include all the important bits below.

At the moment, the Triple is used to configure the MC-layer classes. D13863
highlights a few examples for the MCAsmInfo subclasses:

• Several targets infer the endianness from the Triple.
• A few targets select between MCAsmInfo subclasses depending on the triple.
  • Each possible implementation needs to know different things.
• ARM infers the exception handling mechanism from the triple.
• Mips infers ABI information such as the pointer size and stack slot size from the triple.
• A few targets infer 32/64-bit from the triple.
• A couple targets infer behaviour from the OS X version in the triple.
• Several targets don't need to know anything in particular.
• etc.

Despite having different information requirements, each subclass is required to
have a factory function with the same function type (MCAsmInfoCTorFnTy) even
though this is not publicly visible (there's no public accessor for
MCAsmInfoCtorFn). One of these arguments is the Triple which is both
ambiguous and incomplete. Here are a couple examples for MIPS:

• Mips triples do not contain information about the ABI.
• Mips triples seem to contain information about the endian, 32/64-bit, etc. but it's generally subject to being overridden by distribution defaults and by command line options.

I've only given examples for Mips but ARM has a similar degree of ambiguity and
even X86 has some.

My first attempt at solving this was simply to replace Triple objects with a
TargetTuple that provided the same interface but wasn't ambiguous. The
Triple ambiguity was handled in a single controlled point in the code.
This plan was also going to solve some other problems (mostly related to
generating 32-bit code on a 64-bit Mips CPU). Unfortunately for me, this met
opposition but the result of those discussions is the MCTargetMachine.

My intent with this patch series is to make MCTargetMachine (and its
target-specific subclasses) both factories for MC-layer classes and a
representation of the target those MC-layer classes should be configured for.
It will be initialized by the Triple and then mutated into the desired target
by distribution defaults, command line options, etc.. For example, clang would do this:

// Create a MCTargetMachine for Mips using the default ABI for the triple (o32).
MCTargetMachine *MTM = Target->createMCTargetMachine(Triple("mips-linux-gnu"));
...
// Process -EL option
MipsMCTargetMachine *MipsMTM = static_cast<MipsMCTargetMachine *>(MTM);
MipsMTM->setEndian(LittleEndian);
...
// Process -mabi=64 option
MipsMCTargetMachine *MipsMTM = static_cast<MipsMCTargetMachine *>(MTM);
MipsMTM->setABI("n64");
...
// Create MC layer objects as usual.
MTM->createMCAsmInfo(MRI)

This solves the ambiguity problem by merging Triples, distribution defaults,
and command line options into a single target description. It also solves the
problem of each target needing different information since the MCTargetMachine
subclasses can contain information not present in the Triple and the overridden
createMCAsmInfo() only has to comply with the public interface.

The three patches posted so far are mainly concerned with the factory side of things. If they're accepted then I'll start working on the mutation side.

include/llvm/MC/MCTargetMachine.h

+//===-- llvm/MC/MCTargetMachine.h - Target Information ----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCTARGETMACHINE_H
+#define LLVM_MC_MCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/Support/CodeGen.h"
+
+namespace llvm {
+class MCAsmBackend;
+class MCAsmInfo;
+class MCAsmParser;
+class MCCodeEmitter;
+class MCCodeGenInfo;
+class MCContext;
+class MCDisassembler;
+class MCInstPrinter;
+class MCInstrAnalysis;
+class MCInstrInfo;
+class MCRegisterInfo;
+class MCStreamer;
+class MCSubtargetInfo;
+class MCTargetAsmParser;
+class MCTargetOptions;
+class MCTargetStreamer;
+class Target;
+class Triple;
+class formatted_raw_ostream;
+class raw_pwrite_stream;
+
+//===----------------------------------------------------------------------===//
+///
+/// Primary interface to the complete machine description for the target
+/// machine.  All target-specific information should be accessible through this
+/// interface.
+///
+class MCTargetMachine {
+  MCTargetMachine(const MCTargetMachine &) = delete;
+  void operator=(const MCTargetMachine &) = delete;
+
+protected:
+  /// The Target that this machine was created for.
+  const Target &TheTarget;
+
+  /// The Triple used to configure this machine.
+  /// TODO: Gradually break this up into the actual machine description.
+  const Triple TheTriple;
+
+public:
+  MCTargetMachine(const Target &T, const Triple &TT);
+  virtual ~MCTargetMachine() {}
+
+  const Target &getTarget() const { return TheTarget; }
+
+  /// Create a MCAsmInfo implementation.
+  virtual MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const;
+
+  /// Create a MCCodeGenInfo implementation.
+  virtual MCCodeGenInfo *createMCCodeGenInfo(Reloc::Model RM,
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) const;
+
+  /// Create a MCInstrInfo implementation.
+  virtual MCInstrInfo *createMCInstrInfo() const;
+
+  /// Create a MCInstrAnalysis implementation.
+  virtual MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const;
+
+  /// Create a MCRegisterInfo implementation.
+  virtual MCRegisterInfo *createMCRegisterInfo() const;
+
+  virtual MCSubtargetInfo *createMCSubtargetInfo(StringRef CPU,
+                                                 StringRef Features) const;
+
+  /// Create a target specific assembly parser.
+  virtual MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
+                                           StringRef CPU) const;
+
+  /// Create a target specific assembly parser.
+  ///
+  /// \param Parser The target independent parser implementation to use for
+  /// parsing and lexing.
+  virtual MCTargetAsmParser *
+  createMCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
+                    const MCInstrInfo &MII,
+                    const MCTargetOptions &Options) const;
+
+  virtual MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
+                                               MCContext &Ctx) const;
+
+  virtual MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
+                                             const MCAsmInfo &MAI,
+                                             const MCInstrInfo &MII,
+                                             const MCRegisterInfo &MRI) const;
+
+  /// Create a target specific code emitter.
+  virtual MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
+                                             const MCRegisterInfo &MRI,
+                                             MCContext &Ctx) const;
+
+  /// Create a target specific MCStreamer.
+  ///
+  /// \param Ctx The target context.
+  /// \param TAB The target assembler backend object. Takes ownership.
+  /// \param OS The stream object.
+  /// \param Emitter The target independent assembler object.Takes ownership.
+  /// \param RelaxAll Relax all fixups?
+  virtual MCStreamer *createMCObjectStreamer(MCContext &Ctx, MCAsmBackend &TAB,
+                                             raw_pwrite_stream &OS,
+                                             MCCodeEmitter *Emitter,
+                                             const MCSubtargetInfo &STI,
+                                             bool RelaxAll,
+                                             bool DWARFMustBeAtTheEnd) const;
+
+  virtual MCStreamer *
+  createAsmStreamer(MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
+                    bool IsVerboseAsm, bool UseDwarfDirectory,
+                    MCInstPrinter *InstPrint, MCCodeEmitter *CE,
+                    MCAsmBackend *TAB, bool ShowInst) const;
+
+  virtual MCStreamer *createNullStreamer(MCContext &Ctx) const;
+  virtual MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const;
+};
+
+} // End llvm namespace
+
+#endif

include/llvm/Support/TargetRegistry.h

 class MCInstPrinter;
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCStreamer;
 class MCSubtargetInfo;
 class MCSymbolizer;
 class MCRelocationInfo;
 class MCTargetAsmParser;
+class MCTargetMachine;
 class MCTargetOptions;
 class MCTargetStreamer;
 class TargetMachine;
 class TargetOptions;
 class raw_ostream;
 class raw_pwrite_stream;
 class formatted_raw_ostream;
 

 /// registered without the use of static constructors.
 ///
 /// Targets should implement a single global instance of this class (which
 /// will be zero initialized), and pass that instance to the TargetRegistry as
 /// part of their initialization.
 class Target {
 public:
   friend struct TargetRegistry;
+  friend class MCTargetMachine;
 
   typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
   typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
                                           const Triple &TT);
   typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
                                                   CodeGenOpt::Level OL);
   typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
   typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
   typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
   typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
                                                       StringRef CPU,
                                                       StringRef Features);
   typedef TargetMachine *(*TargetMachineCtorTy)(
       const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
       const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
       CodeGenOpt::Level OL);
+  typedef MCTargetMachine *(*MCTargetMachineCtorTy)(const Target &T,
+                                                    const Triple &TT);
   // If it weren't for layering issues (this header is in llvm/Support, but
   // depends on MC?) this should take the Streamer by value rather than rvalue
   // reference.
   typedef AsmPrinter *(*AsmPrinterCtorTy)(
       TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
-  typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
+  typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const MCTargetMachine &MTM,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TT, StringRef CPU);
   typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
       const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
       const MCTargetOptions &Options);
-  typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
+  typedef MCDisassembler *(*MCDisassemblerCtorTy)(const MCTargetMachine &MCTM,
                                                   const MCSubtargetInfo &STI,
                                                   MCContext &Ctx);
   typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Triple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI);
   typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
private:
   /// MCSubtargetInfoCtorFn - Constructor function for this target's
   /// MCSubtargetInfo, if registered.
   MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
 
   /// TargetMachineCtorFn - Construction function for this target's
   /// TargetMachine, if registered.
   TargetMachineCtorTy TargetMachineCtorFn;
 
+  /// MCTargetMachineCtorFn - Construction function for this target's
+  /// MCTargetMachine, if registered.
+  MCTargetMachineCtorTy MCTargetMachineCtorFn;
+
   /// MCAsmBackendCtorFn - Construction function for this target's
   /// MCAsmBackend, if registered.
   MCAsmBackendCtorTy MCAsmBackendCtorFn;
 
   /// MCAsmParserCtorFn - Construction function for this target's
   /// MCTargetAsmParser, if registered.
   MCAsmParserCtorTy MCAsmParserCtorFn;
 
public:
   /// @{
 
   /// hasJIT - Check if this targets supports the just-in-time compilation.
   bool hasJIT() const { return HasJIT; }
 
   /// hasTargetMachine - Check if this target supports code generation.
   bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; }
 
+  /// hasMCTargetMachine - Check if this target supports machine code.
+  bool hasMCTargetMachine() const { return MCTargetMachineCtorFn != nullptr; }
+
   /// hasMCAsmBackend - Check if this target supports .o generation.
   bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
 
   /// @}
   /// @name Feature Constructors
   /// @{
 
+protected:
   /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
   /// target triple.
   ///
   /// \param TheTriple This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
protected:
   /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation.
   ///
   MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
     if (!MCInstrAnalysisCtorFn)
       return nullptr;
     return MCInstrAnalysisCtorFn(Info);
   }
 
-  /// createMCRegInfo - Create a MCRegisterInfo implementation.
+  /// createMCRegisterInfo - Create a MCRegisterInfo implementation.
   ///
-  MCRegisterInfo *createMCRegInfo(StringRef TT) const {
+  MCRegisterInfo *createMCRegisterInfo(StringRef TT) const {
     if (!MCRegInfoCtorFn)
       return nullptr;
     return MCRegInfoCtorFn(Triple(TT));
   }
 
   /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
   ///
   /// \param TheTriple This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   /// \param CPU This specifies the name of the target CPU.
   /// \param Features This specifies the string representation of the
   /// additional target features.
   MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
                                          StringRef Features) const {
     if (!MCSubtargetInfoCtorFn)
       return nullptr;
     return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
   }
 
+public:
   /// createTargetMachine - Create a target specific machine implementation
   /// for the specified \p Triple.
   ///
   /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   TargetMachine *
   createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
                       const TargetOptions &Options,
                       Reloc::Model RM = Reloc::Default,
                       CodeModel::Model CM = CodeModel::Default,
                       CodeGenOpt::Level OL = CodeGenOpt::Default) const {
     if (!TargetMachineCtorFn)
       return nullptr;
     return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
                                CM, OL);
   }
 
+  /// createMCTargetMachine - Create a target specific machine implementation
+  /// for the specified \p Triple.
+  ///
+  /// \param TT This argument is used to determine the target machine
+  /// feature set; it should always be provided. Generally this should be
+  /// either the target triple from the module, or the target triple of the
+  /// host if that does not exist.
+  MCTargetMachine *createMCTargetMachine(const Triple &TT) const {
+    if (!MCTargetMachineCtorFn)
+      return nullptr;
+    return MCTargetMachineCtorFn(*this, TT);
+  }
+
+protected:
   /// createMCAsmBackend - Create a target specific assembly parser.
   ///
   /// \param TheTriple The target triple string.
-  MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
+  MCAsmBackend *createMCAsmBackend(const MCTargetMachine &MTM,
+                                   const MCRegisterInfo &MRI,
                                    StringRef TheTriple, StringRef CPU) const {
     if (!MCAsmBackendCtorFn)
       return nullptr;
-    return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
+    return MCAsmBackendCtorFn(MTM, MRI, Triple(TheTriple), CPU);
   }
 
   /// createMCAsmParser - Create a target specific assembly parser.
   ///
   /// \param Parser The target independent parser implementation to use for
   /// parsing and lexing.
   MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
                                        MCAsmParser &Parser,
                                        const MCInstrInfo &MII,
                                        const MCTargetOptions &Options) const {
     if (!MCAsmParserCtorFn)
       return nullptr;
     return MCAsmParserCtorFn(STI, Parser, MII, Options);
   }
 
+public:
   /// createAsmPrinter - Create a target specific assembly printer pass.  This
   /// takes ownership of the MCStreamer object.
   AsmPrinter *createAsmPrinter(TargetMachine &TM,
                                std::unique_ptr<MCStreamer> &&Streamer) const {
     if (!AsmPrinterCtorFn)
       return nullptr;
     return AsmPrinterCtorFn(TM, std::move(Streamer));
   }
 
-  MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
+protected:
+  MCDisassembler *createMCDisassembler(const MCTargetMachine &MCTM,
+                                       const MCSubtargetInfo &STI,
                                        MCContext &Ctx) const {
     if (!MCDisassemblerCtorFn)
       return nullptr;
-    return MCDisassemblerCtorFn(*this, STI, Ctx);
+    return MCDisassemblerCtorFn(MCTM, STI, Ctx);
   }
 
   MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
                                      const MCAsmInfo &MAI,
                                      const MCInstrInfo &MII,
                                      const MCRegisterInfo &MRI) const {
     if (!MCInstPrinterCtorFn)
       return nullptr;
protected:
   }
 
   MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const {
     if (NullTargetStreamerCtorFn)
       return NullTargetStreamerCtorFn(S);
     return nullptr;
   }
 
+public:
   /// createMCRelocationInfo - Create a target specific MCRelocationInfo.
   ///
   /// \param TT The target triple.
   /// \param Ctx The target context.
   MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
     MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
                                     ? MCRelocationInfoCtorFn
                                     : llvm::createMCRelocationInfo;
struct TargetRegistry {
   /// this is done by initializing all targets at program startup.
   ///
   /// @param T - The target being registered.
   /// @param Fn - A function to construct a TargetMachine for the target.
   static void RegisterTargetMachine(Target &T, Target::TargetMachineCtorTy Fn) {
     T.TargetMachineCtorFn = Fn;
   }
 
+  /// RegisterMCTargetMachine - Register a MCTargetMachine implementation for
+  /// the given target.
+  ///
+  /// Clients are responsible for ensuring that registration doesn't occur
+  /// while another thread is attempting to access the registry. Typically
+  /// this is done by initializing all targets at program startup.
+  ///
+  /// @param T - The target being registered.
+  /// @param Fn - A function to construct a MCTargetMachine for the target.
+  static void RegisterMCTargetMachine(Target &T,
+                                      Target::MCTargetMachineCtorTy Fn) {
+    T.MCTargetMachineCtorFn = Fn;
+  }
+
   /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
   /// given target.
   ///
   /// Clients are responsible for ensuring that registration doesn't occur
   /// while another thread is attempting to access the registry. Typically
   /// this is done by initializing all targets at program startup.
   ///
   /// @param T - The target being registered.
private:
   static TargetMachine *Allocator(const Target &T, const Triple &TT,
                                   StringRef CPU, StringRef FS,
                                   const TargetOptions &Options, Reloc::Model RM,
                                   CodeModel::Model CM, CodeGenOpt::Level OL) {
     return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
   }
 };
 
+/// RegisterMCTargetMachine - Helper template for registering a target machine
+/// implementation, for use in the target machine initialization
+/// function. Usage:
+///
+/// extern "C" void LLVMInitializeFooTarget() {
+///   extern Target TheFooTarget;
+///   RegisterMCTargetMachine<FooMCTargetMachine> X(TheFooTarget);
+/// }
+template <class MCTargetMachineImpl> struct RegisterMCTargetMachine {
+  RegisterMCTargetMachine(Target &T) {
+    TargetRegistry::RegisterMCTargetMachine(T, &Allocator);
+  }
+
+private:
+  static MCTargetMachine *Allocator(const Target &T, const Triple &TT) {
+    return new MCTargetMachineImpl(T, TT);
+  }
+};
+
 /// RegisterMCAsmBackend - Helper template for registering a target specific
 /// assembler backend. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmBackend() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
 /// }
 template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
   RegisterMCAsmBackend(Target &T) {
     TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
   }
 
 private:
-  static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
+  static MCAsmBackend *Allocator(const MCTargetMachine &MTM,
+                                 const MCRegisterInfo &MRI,
                                  const Triple &TheTriple, StringRef CPU) {
-    return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
+    return new MCAsmBackendImpl(MTM, MRI, TheTriple, CPU);
   }
 };
 
 /// RegisterMCAsmParser - Helper template for registering a target specific
 /// assembly parser, for use in the target machine initialization
 /// function. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmParser() {

include/llvm/Target/TargetMachine.h

 class MachineFunctionInitializer;
 class MCAsmInfo;
 class MCCodeGenInfo;
 class MCContext;
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCSymbol;
+class MCTargetMachine;
 class Target;
 class DataLayout;
 class TargetLibraryInfo;
 class TargetFrameLowering;
 class TargetIRAnalysis;
 class TargetIntrinsicInfo;
 class TargetLowering;
 class TargetPassConfig;
protected: // Can only create subclasses.
   const DataLayout DL;
 
   /// Triple string, CPU name, and target feature strings the TargetMachine
   /// instance is created with.
   Triple TargetTriple;
   std::string TargetCPU;
   std::string TargetFS;
 
+  // The MC-level target machine
+  const MCTargetMachine *MTM;
+
   /// Low level target information such as relocation model. Non-const to
   /// allow resetting optimization level per-function.
   MCCodeGenInfo *CodeGenInfo;
 
   /// Contains target specific asm information.
   const MCAsmInfo *AsmInfo;
 
   const MCRegisterInfo *MRI;
public:
   /// \brief Reset the target options based on the function's attributes.
   // FIXME: Remove TargetOptions that affect per-function code generation
   // from TargetMachine.
   void resetTargetOptions(const Function &F) const;
 
   /// Return target specific asm information.
   const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
 
+  const MCTargetMachine *getMCTargetMachine() const { return MTM; }
   const MCRegisterInfo *getMCRegisterInfo() const { return MRI; }
   const MCInstrInfo *getMCInstrInfo() const { return MII; }
   const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; }
 
   /// If intrinsic information is available, return it.  If not, return null.
   virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
     return nullptr;
   }

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

 #include "llvm/IR/Operator.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/Timer.h"
 #include "llvm/Target/TargetFrameLowering.h"
 #include "llvm/Target/TargetInstrInfo.h"
bool AsmPrinter::doInitialization(Module &M) {
   for (auto &I : *MI)
     if (GCMetadataPrinter *MP = GetOrCreateGCPrinter(*I))
       MP->beginAssembly(M, *MI, *this);
 
   // Emit module-level inline asm if it exists.
   if (!M.getModuleInlineAsm().empty()) {
     // We're at the module level. Construct MCSubtarget from the default CPU
     // and target triple.
-    std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
-        TM.getTargetTriple().str(), TM.getTargetCPU(),
-        TM.getTargetFeatureString()));
+    std::unique_ptr<MCSubtargetInfo> STI(
+        TM.getMCTargetMachine()->createMCSubtargetInfo(
+            TM.getTargetCPU(), TM.getTargetFeatureString()));
     OutStreamer->AddComment("Start of file scope inline assembly");
     OutStreamer->AddBlankLine();
     EmitInlineAsm(M.getModuleInlineAsm()+"\n",
                   OutContext.getSubtargetCopy(*STI), TM.Options.MCOptions);
     OutStreamer->AddComment("End of file scope inline assembly");
     OutStreamer->AddBlankLine();
   }
 

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCTargetAsmParser.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
 
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(SrcMgr, OutContext, *OutStreamer, *MAI));
 
   // We create a new MCInstrInfo here since we might be at the module level
   // and not have a MachineFunction to initialize the TargetInstrInfo from and
   // we only need MCInstrInfo for asm parsing. We create one unconditionally
   // because it's not subtarget dependent.
-  std::unique_ptr<MCInstrInfo> MII(TM.getTarget().createMCInstrInfo());
-  std::unique_ptr<MCTargetAsmParser> TAP(TM.getTarget().createMCAsmParser(
-      STI, *Parser, *MII, MCOptions));
+  std::unique_ptr<MCInstrInfo> MII(
+      TM.getMCTargetMachine()->createMCInstrInfo());
+  std::unique_ptr<MCTargetAsmParser> TAP(
+      TM.getMCTargetMachine()->createMCAsmParser(STI, *Parser, *MII,
+                                                 MCOptions));
   if (!TAP)
     report_fatal_error("Inline asm not supported by this streamer because"
                        " we don't have an asm parser for this target\n");
   Parser->setAssemblerDialect(Dialect);
   Parser->setTargetParser(*TAP.get());
   if (MF) {
     const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     TAP->SetFrameRegister(TRI->getFrameRegister(*MF));

lib/CodeGen/LLVMTargetMachine.cpp

 #include "llvm/IR/IRPrintingPasses.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/Scalar.h"
 using namespace llvm;
 
 // Enable or disable FastISel. Both options are needed, because
 // FastISel is enabled by default with -fast, and we wish to be
 // able to enable or disable fast-isel independently from -O0.
 static cl::opt<cl::boolOrDefault>
 EnableFastISelOption("fast-isel", cl::Hidden,
   cl::desc("Enable the \"fast\" instruction selector"));
 
 void LLVMTargetMachine::initAsmInfo() {
-  MRI = TheTarget.createMCRegInfo(getTargetTriple().str());
-  MII = TheTarget.createMCInstrInfo();
+  MRI = MTM->createMCRegisterInfo();
+  MII = MTM->createMCInstrInfo();
   // FIXME: Having an MCSubtargetInfo on the target machine is a hack due
   // to some backends having subtarget feature dependent module level
   // code generation. This is similar to the hack in the AsmPrinter for
   // module level assembly etc.
-  STI = TheTarget.createMCSubtargetInfo(getTargetTriple().str(), getTargetCPU(),
-                                        getTargetFeatureString());
+  STI = MTM->createMCSubtargetInfo(getTargetCPU(), getTargetFeatureString());
 
-  MCAsmInfo *TmpAsmInfo =
-      TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str());
+  MCAsmInfo *TmpAsmInfo = MTM->createMCAsmInfo(*MRI);
   // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
   // and if the old one gets included then MCAsmInfo will be NULL and
   // we'll crash later.
   // Provide the user with a useful error message about what's wrong.
   assert(TmpAsmInfo && "MCAsmInfo not initialized. "
          "Make sure you include the correct TargetSelect.h"
          "and that InitializeAllTargetMCs() is being invoked!");
 
   if (Options.DisableIntegratedAS)
     TmpAsmInfo->setUseIntegratedAssembler(false);
 
   if (Options.CompressDebugSections)
     TmpAsmInfo->setCompressDebugSections(true);
 
   AsmInfo = TmpAsmInfo;
 }
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
                                      StringRef DataLayoutString,
                                      const Triple &TT, StringRef CPU,
                                      StringRef FS, TargetOptions Options,
                                      Reloc::Model RM, CodeModel::Model CM,
                                      CodeGenOpt::Level OL)
     : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
-  CodeGenInfo = T.createMCCodeGenInfo(TT.str(), RM, CM, OL);
+  MTM = TheTarget.createMCTargetMachine(getTargetTriple());
+  CodeGenInfo = MTM->createMCCodeGenInfo(RM, CM, OL);
 }
 
 TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(BasicTTIImpl(this, F));
   });
 }
 
bool LLVMTargetMachine::addPassesToEmitFile(
   const MCAsmInfo &MAI = *getMCAsmInfo();
   const MCRegisterInfo &MRI = *getMCRegisterInfo();
   const MCInstrInfo &MII = *getMCInstrInfo();
 
   std::unique_ptr<MCStreamer> AsmStreamer;
 
   switch (FileType) {
   case CGFT_AssemblyFile: {
-    MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
-        getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
+    MCInstPrinter *InstPrinter =
+        MTM->createMCInstPrinter(MAI.getAssemblerDialect(), MAI, MII, MRI);
 
     // Create a code emitter if asked to show the encoding.
     MCCodeEmitter *MCE = nullptr;
     if (Options.MCOptions.ShowMCEncoding)
-      MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
+      MCE = MTM->createMCCodeEmitter(MII, MRI, *Context);
 
-    MCAsmBackend *MAB =
-        getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
+    MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU);
     auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
-    MCStreamer *S = getTarget().createAsmStreamer(
+    MCStreamer *S = MTM->createAsmStreamer(
         *Context, std::move(FOut), Options.MCOptions.AsmVerbose,
         Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB,
         Options.MCOptions.ShowMCInst);
     AsmStreamer.reset(S);
     break;
   }
   case CGFT_ObjectFile: {
     // Create the code emitter for the target if it exists.  If not, .o file
     // emission fails.
-    MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
-    MCAsmBackend *MAB =
-        getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
+    MCCodeEmitter *MCE = MTM->createMCCodeEmitter(MII, MRI, *Context);
+    MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU);
     if (!MCE || !MAB)
       return true;
 
     // Don't waste memory on names of temp labels.
     Context->setUseNamesOnTempLabels(false);
 
-    Triple T(getTargetTriple().str());
-    AsmStreamer.reset(getTarget().createMCObjectStreamer(
-        T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
+    AsmStreamer.reset(MTM->createMCObjectStreamer(
+        *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
         /*DWARFMustBeAtTheEnd*/ true));
     break;
   }
   case CGFT_Null:
     // The Null output is intended for use for performance analysis and testing,
     // not real users.
-    AsmStreamer.reset(getTarget().createNullStreamer(*Context));
+    AsmStreamer.reset(MTM->createNullStreamer(*Context));
     break;
   }
 
   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
   FunctionPass *Printer =
       getTarget().createAsmPrinter(*this, std::move(AsmStreamer));
   if (!Printer)
     return true;
if (!Ctx)
     return true;
 
   if (Options.MCOptions.MCSaveTempLabels)
     Ctx->setAllowTemporaryLabels(false);
 
   // Create the code emitter for the target if it exists.  If not, .o file
   // emission fails.
   const MCRegisterInfo &MRI = *getMCRegisterInfo();
-  MCCodeEmitter *MCE =
-      getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
-  MCAsmBackend *MAB =
-      getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
+  MCCodeEmitter *MCE = MTM->createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
+  MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU);
   if (!MCE || !MAB)
     return true;
 
-  const Triple &T = getTargetTriple();
   const MCSubtargetInfo &STI = *getMCSubtargetInfo();
-  std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
-      T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
+  std::unique_ptr<MCStreamer> AsmStreamer(MTM->createMCObjectStreamer(
+      *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
       /*DWARFMustBeAtTheEnd*/ true));
 
   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
   FunctionPass *Printer =
       getTarget().createAsmPrinter(*this, std::move(AsmStreamer));
   if (!Printer)
     return true;
 
   PM.add(Printer);
 
   return false; // success!
 }

lib/MC/CMakeLists.txt

add_llvm_library(LLVMMC
   MCSectionELF.cpp
   MCSectionMachO.cpp
   MCStreamer.cpp
   MCSubtargetInfo.cpp
   MCSymbol.cpp
   MCSymbolELF.cpp
   MCSymbolizer.cpp
   MCTargetOptions.cpp
+  MCTargetMachine.cpp
   MCValue.cpp
   MCWin64EH.cpp
   MCWinEH.cpp
   MachObjectWriter.cpp
   StringTableBuilder.cpp
   SubtargetFeature.cpp
   WinCOFFObjectWriter.cpp
   WinCOFFStreamer.cpp
   YAML.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${LLVM_MAIN_INCLUDE_DIR}/llvm/MC
   )
 
 add_subdirectory(MCParser)
 add_subdirectory(MCDisassembler)

lib/MC/MCDisassembler/Disassembler.h

 namespace llvm {
 class MCContext;
 class MCAsmInfo;
 class MCDisassembler;
 class MCInstPrinter; 
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class Target;
 
 //
 // This is the disassembler context returned by LLVMCreateDisasm().
 //
 class LLVMDisasmContext {
 private:
   //
private:
   //
   // The objects created and saved by LLVMCreateDisasm() then used by
   // LLVMDisasmInstruction().
   //
   // The LLVM target corresponding to the disassembler.
   // FIXME: using std::unique_ptr<const llvm::Target> causes a malloc error
   //        when this LLVMDisasmContext is deleted.
   const Target *TheTarget;
+  // The target machine for the target architecture.
+  std::unique_ptr<const llvm::MCTargetMachine> MTM;
   // The assembly information for the target architecture.
   std::unique_ptr<const llvm::MCAsmInfo> MAI;
   // The register information for the target architecture.
   std::unique_ptr<const llvm::MCRegisterInfo> MRI;
   // The subtarget information for the target architecture.
   std::unique_ptr<const llvm::MCSubtargetInfo> MSI;
   // The instruction information for the target architecture.
   std::unique_ptr<const llvm::MCInstrInfo> MII;

 public:
   // Comment stream and backing vector.
   SmallString<128> CommentsToEmit;
   raw_svector_ostream CommentStream;
 
   LLVMDisasmContext(std::string tripleName, void *disInfo, int tagType,
                     LLVMOpInfoCallback getOpInfo,
                     LLVMSymbolLookupCallback symbolLookUp,
-                    const Target *theTarget, const MCAsmInfo *mAI,
-                    const MCRegisterInfo *mRI,
-                    const MCSubtargetInfo *mSI,
-                    const MCInstrInfo *mII,
+                    const Target *theTarget, const MCTargetMachine *mTM,
+                    const MCAsmInfo *mAI, const MCRegisterInfo *mRI,
+                    const MCSubtargetInfo *mSI, const MCInstrInfo *mII,
                     llvm::MCContext *ctx, const MCDisassembler *disAsm,
-                    MCInstPrinter *iP) : TripleName(tripleName),
-                    DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo),
-                    SymbolLookUp(symbolLookUp), TheTarget(theTarget),
-                    Options(0),
-                    CommentStream(CommentsToEmit) {
+                    MCInstPrinter *iP)
+      : TripleName(tripleName), DisInfo(disInfo), TagType(tagType),
+        GetOpInfo(getOpInfo), SymbolLookUp(symbolLookUp), TheTarget(theTarget),
+        Options(0), CommentStream(CommentsToEmit) {
+    MTM.reset(mTM);
     MAI.reset(mAI);
     MRI.reset(mRI);
     MSI.reset(mSI);
     MII.reset(mII);
     Ctx.reset(ctx);
     DisAsm.reset(disAsm);
     IP.reset(iP);
   }
   const std::string &getTripleName() const { return TripleName; }
   void *getDisInfo() const { return DisInfo; }
   int getTagType() const { return TagType; }
   LLVMOpInfoCallback getGetOpInfo() const { return GetOpInfo; }
   LLVMSymbolLookupCallback getSymbolLookupCallback() const {
     return SymbolLookUp;
   }
   const Target *getTarget() const { return TheTarget; }
+  const MCTargetMachine *getMCTargetMachine() { return MTM.get(); }
   const MCDisassembler *getDisAsm() const { return DisAsm.get(); }
   const MCAsmInfo *getAsmInfo() const { return MAI.get(); }
   const MCInstrInfo *getInstrInfo() const { return MII.get(); }
   const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
   const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); }
   MCInstPrinter *getIP() { return IP.get(); }
   void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); }
   uint64_t getOptions() const { return Options; }
   void addOptions(uint64_t Options) { this->Options |= Options; }
   StringRef getCPU() const { return CPU; }
   void setCPU(const char *CPU) { this->CPU = CPU; }
 };
 
 } // namespace llvm
 
 #endif

lib/MC/MCDisassembler/Disassembler.cpp

 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCRelocationInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbolizer.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 // LLVMCreateDisasm() creates a disassembler for the TripleName.  Symbolic
 // disassembly is supported by passing a block of information in the DisInfo
 // parameter and specifying the TagType and callback functions as described in
 // the header llvm-c/Disassembler.h .  The pointer to the block and the 
 // functions can all be passed as NULL.  If successful, this returns a
 // disassembler context.  If not, it returns NULL.
 //
 LLVMDisasmContextRef
-LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
+LLVMCreateDisasmCPUFeatures(const char *TTStr, const char *CPU,
                             const char *Features, void *DisInfo, int TagType,
                             LLVMOpInfoCallback GetOpInfo,
                             LLVMSymbolLookupCallback SymbolLookUp) {
   // Get the target.
   std::string Error;
-  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
+  const Target *TheTarget = TargetRegistry::lookupTarget(TTStr, Error);
   if (!TheTarget)
     return nullptr;
 
-  const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT);
+  Triple TT(TTStr);
+  const MCTargetMachine *MTM = TheTarget->createMCTargetMachine(TT);
+  if (!MTM)
+    return nullptr;
+
+  const MCRegisterInfo *MRI = MTM->createMCRegisterInfo();
   if (!MRI)
     return nullptr;
 
   // Get the assembler info needed to setup the MCContext.
-  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT);
+  const MCAsmInfo *MAI = MTM->createMCAsmInfo(*MRI);
   if (!MAI)
     return nullptr;
 
-  const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
+  const MCInstrInfo *MII = MTM->createMCInstrInfo();
   if (!MII)
     return nullptr;
 
-  const MCSubtargetInfo *STI =
-      TheTarget->createMCSubtargetInfo(TT, CPU, Features);
+  const MCSubtargetInfo *STI = MTM->createMCSubtargetInfo(CPU, Features);
   if (!STI)
     return nullptr;
 
   // Set up the MCContext for creating symbols and MCExpr's.
   MCContext *Ctx = new MCContext(MAI, MRI, nullptr);
   if (!Ctx)
     return nullptr;
 
   // Set up disassembler.
-  MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
+  MCDisassembler *DisAsm = MTM->createMCDisassembler(*STI, *Ctx);
   if (!DisAsm)
     return nullptr;
 
   std::unique_ptr<MCRelocationInfo> RelInfo(
-      TheTarget->createMCRelocationInfo(TT, *Ctx));
+      TheTarget->createMCRelocationInfo(TTStr, *Ctx));
   if (!RelInfo)
     return nullptr;
 
   std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
-      TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
+      TTStr, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
   DisAsm->setSymbolizer(std::move(Symbolizer));
 
   // Set up the instruction printer.
   int AsmPrinterVariant = MAI->getAssemblerDialect();
-  MCInstPrinter *IP = TheTarget->createMCInstPrinter(
-      Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
+  MCInstPrinter *IP =
+      MTM->createMCInstPrinter(AsmPrinterVariant, *MAI, *MII, *MRI);
   if (!IP)
     return nullptr;
 
   LLVMDisasmContext *DC =
-      new LLVMDisasmContext(TT, DisInfo, TagType, GetOpInfo, SymbolLookUp,
-                            TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
+      new LLVMDisasmContext(TTStr, DisInfo, TagType, GetOpInfo, SymbolLookUp,
+                            TheTarget, MTM, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
   if (!DC)
     return nullptr;
 
   DC->setCPU(CPU);
   return DC;
 }
 
 LLVMDisasmContextRef
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
   if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
       LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
       // Try to set up the new instruction printer.
       const MCAsmInfo *MAI = DC->getAsmInfo();
       const MCInstrInfo *MII = DC->getInstrInfo();
       const MCRegisterInfo *MRI = DC->getRegisterInfo();
       int AsmPrinterVariant = MAI->getAssemblerDialect();
       AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
-      MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
-          Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
+      MCInstPrinter *IP = DC->getMCTargetMachine()->createMCInstPrinter(
+          AsmPrinterVariant, *MAI, *MII, *MRI);
       if (IP) {
         DC->setIP(IP);
         DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
         Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
       }
   }
   if (Options & LLVMDisassembler_Option_SetInstrComments) {
     LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;

lib/MC/MCTargetMachine.cpp

+//===-- MCTargetMachine.cpp - General Target Information -------------------==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the general parts of a MC Target machine.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCTargetMachine.h"
+#include "llvm/Support/TargetRegistry.h"
+using namespace llvm;
+
+MCTargetMachine::MCTargetMachine(const Target &T, const Triple &TT)
+    : TheTarget(T), TheTriple(TT) {}
+
+MCAsmInfo *MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return TheTarget.createMCAsmInfo(MRI, TheTriple.str());
+}
+
+MCCodeGenInfo *
+MCTargetMachine::createMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
+                                     CodeGenOpt::Level OL) const {
+  return TheTarget.createMCCodeGenInfo(TheTriple.str(), RM, CM, OL);
+}
+
+MCInstrInfo *MCTargetMachine::createMCInstrInfo() const {
+  return TheTarget.createMCInstrInfo();
+}
+
+MCInstrAnalysis *
+MCTargetMachine::createMCInstrAnalysis(const MCInstrInfo *Info) const {
+  return TheTarget.createMCInstrAnalysis(Info);
+}
+
+MCRegisterInfo *MCTargetMachine::createMCRegisterInfo() const {
+  return TheTarget.createMCRegisterInfo(TheTriple.str());
+}
+
+MCSubtargetInfo *
+MCTargetMachine::createMCSubtargetInfo(StringRef CPU,
+                                       StringRef Features) const {
+  return TheTarget.createMCSubtargetInfo(TheTriple.str(), CPU, Features);
+}
+
+MCAsmBackend *MCTargetMachine::createMCAsmBackend(const MCRegisterInfo &MRI,
+                                                  StringRef CPU) const {
+  return TheTarget.createMCAsmBackend(*this, MRI, TheTriple.str(), CPU);
+};
+
+MCTargetAsmParser *
+MCTargetMachine::createMCAsmParser(const MCSubtargetInfo &STI,
+                                   MCAsmParser &Parser, const MCInstrInfo &MII,
+                                   const MCTargetOptions &Options) const {
+  return TheTarget.createMCAsmParser(STI, Parser, MII, Options);
+}
+
+MCDisassembler *
+MCTargetMachine::createMCDisassembler(const MCSubtargetInfo &STI,
+                                      MCContext &Ctx) const {
+  return TheTarget.createMCDisassembler(*this, STI, Ctx);
+}
+
+MCInstPrinter *MCTargetMachine::createMCInstPrinter(
+    unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII,
+    const MCRegisterInfo &MRI) const {
+  return TheTarget.createMCInstPrinter(TheTriple, SyntaxVariant, MAI, MII, MRI);
+}
+
+MCCodeEmitter *MCTargetMachine::createMCCodeEmitter(const MCInstrInfo &II,
+                                                    const MCRegisterInfo &MRI,
+                                                    MCContext &Ctx) const {
+  return TheTarget.createMCCodeEmitter(II, MRI, Ctx);
+}
+
+MCStreamer *MCTargetMachine::createMCObjectStreamer(
+    MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS,
+    MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll,
+    bool DWARFMustBeAtTheEnd) const {
+  return TheTarget.createMCObjectStreamer(TheTriple, Ctx, TAB, OS, Emitter, STI,
+                                          RelaxAll, DWARFMustBeAtTheEnd);
+}
+
+MCStreamer *MCTargetMachine::createAsmStreamer(
+    MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
+    bool IsVerboseAsm, bool UseDwarfDirectory, MCInstPrinter *InstPrint,
+    MCCodeEmitter *CE, MCAsmBackend *TAB, bool ShowInst) const {
+  return TheTarget.createAsmStreamer(Ctx, std::move(OS), IsVerboseAsm,
+                                     UseDwarfDirectory, InstPrint, CE, TAB,
+                                     ShowInst);
+}
+
+MCStreamer *MCTargetMachine::createNullStreamer(MCContext &Ctx) const {
+  return TheTarget.createNullStreamer(Ctx);
+}
+
+MCTargetStreamer *
+MCTargetMachine::createNullTargetStreamer(MCStreamer &S) const {
+  return TheTarget.createNullTargetStreamer(S);
+}

lib/Object/IRObjectFile.cpp

 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetAsmParser.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 using namespace object;
 
 IRObjectFile::IRObjectFile(MemoryBufferRef Object, std::unique_ptr<Module> Mod)
     : SymbolicFile(Binary::ID_IR, Object), M(std::move(Mod)) {
   Mang.reset(new Mangler());
 
   const std::string &InlineAsm = M->getModuleInlineAsm();
   if (InlineAsm.empty())
     return;
 
   Triple TT(M->getTargetTriple());
   std::string Err;
   const Target *T = TargetRegistry::lookupTarget(TT.str(), Err);
   if (!T)
     return;
 
-  std::unique_ptr<MCRegisterInfo> MRI(T->createMCRegInfo(TT.str()));
+  std::unique_ptr<MCTargetMachine> MTM(T->createMCTargetMachine(TT));
+  if (!MTM)
+    return;
+
+  std::unique_ptr<MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
   if (!MRI)
     return;
 
-  std::unique_ptr<MCAsmInfo> MAI(T->createMCAsmInfo(*MRI, TT.str()));
+  std::unique_ptr<MCAsmInfo> MAI(MTM->createMCAsmInfo(*MRI));
   if (!MAI)
     return;
 
-  std::unique_ptr<MCSubtargetInfo> STI(
-      T->createMCSubtargetInfo(TT.str(), "", ""));
+  std::unique_ptr<MCSubtargetInfo> STI(MTM->createMCSubtargetInfo("", ""));
   if (!STI)
     return;
 
-  std::unique_ptr<MCInstrInfo> MCII(T->createMCInstrInfo());
+  std::unique_ptr<MCInstrInfo> MCII(MTM->createMCInstrInfo());
   if (!MCII)
     return;
 
   MCObjectFileInfo MOFI;
   MCContext MCCtx(MAI.get(), MRI.get(), &MOFI);
   MOFI.InitMCObjectFileInfo(TT, Reloc::Default, CodeModel::Default, MCCtx);
   std::unique_ptr<RecordStreamer> Streamer(new RecordStreamer(MCCtx));
-  T->createNullTargetStreamer(*Streamer);
+  MTM->createNullTargetStreamer(*Streamer);
 
   std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(InlineAsm));
   SourceMgr SrcMgr;
   SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc());
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(SrcMgr, MCCtx, *Streamer, *MAI));
 
   MCTargetOptions MCOptions;
   std::unique_ptr<MCTargetAsmParser> TAP(
-      T->createMCAsmParser(*STI, *Parser, *MCII, MCOptions));
+      MTM->createMCAsmParser(*STI, *Parser, *MCII, MCOptions));
   if (!TAP)
     return;
 
   Parser->setTargetParser(*TAP);
   if (Parser->Run(false))
     return;
 
   for (auto &KV : *Streamer) {

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 
 #include "AArch64GenDisassemblerTables.inc"
 #include "AArch64GenInstrInfo.inc"
 
 #define Success llvm::MCDisassembler::Success
 #define Fail llvm::MCDisassembler::Fail
 #define SoftFail llvm::MCDisassembler::SoftFail
 
-static MCDisassembler *createAArch64Disassembler(const Target &T,
+static MCDisassembler *createAArch64Disassembler(const MCTargetMachine &,
                                                  const MCSubtargetInfo &STI,
                                                  MCContext &Ctx) {
   return new AArch64Disassembler(STI, Ctx);
 }
 
 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                  ArrayRef<uint8_t> Bytes,
                                                  uint64_t Address,
                                                  raw_ostream &OS,
                                                  raw_ostream &CS) const {

lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

 
 namespace {
 
 class AArch64AsmBackend : public MCAsmBackend {
   static const unsigned PCRelFlagVal =
       MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
 
 public:
-  AArch64AsmBackend(const Target &T) : MCAsmBackend() {}
+  AArch64AsmBackend() : MCAsmBackend() {}
 
   unsigned getNumFixupKinds() const override {
     return AArch64::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
class DarwinAArch64AsmBackend : public AArch64AsmBackend {
   /// \brief Encode compact unwind stack adjustment for frameless functions.
   /// See UNWIND_AArch64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
   /// The stack size always needs to be 16 byte aligned.
   uint32_t encodeStackAdjustment(uint32_t StackSize) const {
     return (StackSize / 16) << 12;
   }
 
 public:
-  DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
-      : AArch64AsmBackend(T), MRI(MRI) {}
+  DarwinAArch64AsmBackend(const MCRegisterInfo &MRI)
+      : AArch64AsmBackend(), MRI(MRI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
                                          MachO::CPU_SUBTYPE_ARM64_ALL);
   }
 
   /// \brief Generate the compact unwind encoding from the CFI directives.
   uint32_t generateCompactUnwindEncoding(

 
 namespace {
 
 class ELFAArch64AsmBackend : public AArch64AsmBackend {
 public:
   uint8_t OSABI;
   bool IsLittleEndian;
 
-  ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
-    : AArch64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
+  ELFAArch64AsmBackend(uint8_t OSABI, bool IsLittleEndian)
+      : AArch64AsmBackend(), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian);
   }
 
   void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
                          const MCFixup &Fixup, const MCFragment *DF,
                          const MCValue &Target, uint64_t &Value,
void ELFAArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
   if (!IsLittleEndian && Fixup.getKind() == FK_Data_4) {
     if (isByteSwappedFixup(Fixup.getValue()))
       Value = ByteSwap_32(unsigned(Value));
   }
   AArch64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
 }
 }
 
-MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
+MCAsmBackend *llvm::createAArch64leAsmBackend(const MCTargetMachine &,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TheTriple,
                                               StringRef CPU) {
   if (TheTriple.isOSBinFormatMachO())
-    return new DarwinAArch64AsmBackend(T, MRI);
+    return new DarwinAArch64AsmBackend(MRI);
 
   assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-  return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
+  return new ELFAArch64AsmBackend(OSABI, /*IsLittleEndian=*/true);
 }
 
-MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
+MCAsmBackend *llvm::createAArch64beAsmBackend(const MCTargetMachine &,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TheTriple,
                                               StringRef CPU) {
   assert(TheTriple.isOSBinFormatELF() &&
          "Big endian is only supported for ELF targets!");
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-  return new ELFAArch64AsmBackend(T, OSABI,
+  return new ELFAArch64AsmBackend(OSABI,
                                   /*IsLittleEndian=*/false);
 }

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCInstPrinter;
 class MCRegisterInfo;
 class MCObjectWriter;
 class MCStreamer;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class MCTargetStreamer;
 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheAArch64leTarget;
 extern Target TheAArch64beTarget;
 extern Target TheARM64Target;
 
 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
                                           const MCRegisterInfo &MRI,
                                           MCContext &Ctx);
-MCAsmBackend *createAArch64leAsmBackend(const Target &T,
+MCAsmBackend *createAArch64leAsmBackend(const MCTargetMachine &MTM,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TT, StringRef CPU);
-MCAsmBackend *createAArch64beAsmBackend(const Target &T,
+MCAsmBackend *createAArch64beAsmBackend(const MCTargetMachine &MTM,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI,
                                              bool IsLittleEndian);
 
 MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 #include "AArch64ELFStreamer.h"
 #include "AArch64MCAsmInfo.h"
 #include "InstPrinter/AArch64InstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AArch64GenInstrInfo.inc"
 
return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                              DWARFMustBeAtTheEnd,
                              /*LabelSections*/ true);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeAArch64TargetMC() {
   for (Target *T :
        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

public:
   }
 
   void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
 
 };
 
 class AMDGPUAsmBackend : public MCAsmBackend {
 public:
-  AMDGPUAsmBackend(const Target &T)
-    : MCAsmBackend() {}
+  AMDGPUAsmBackend() : MCAsmBackend() {}
 
   unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value, bool IsPCRel) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     return false;

 //===----------------------------------------------------------------------===//
 
 namespace {
 
 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
   bool Is64Bit;
 
 public:
-  ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) :
-      AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
+  ELFAMDGPUAsmBackend(bool Is64Bit) : AMDGPUAsmBackend(), Is64Bit(Is64Bit) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createAMDGPUELFObjectWriter(Is64Bit, OS);
   }
 };
 
 } // end anonymous namespace
 
-MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
+MCAsmBackend *llvm::createAMDGPUAsmBackend(const MCTargetMachine &MTM,
                                            const MCRegisterInfo &MRI,
                                            const Triple &TT, StringRef CPU) {
-  Triple TargetTriple(TT);
-
   // Use 64-bit ELF for amdgcn
-  return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
+  return new ELFAMDGPUAsmBackend(TT.getArch() == Triple::amdgcn);
 }

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class Target;
 class Triple;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheAMDGPUTarget;
 extern Target TheGCNTarget;
 
 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
                                        const MCRegisterInfo &MRI,
                                        MCContext &Ctx);
 
 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
                                      const MCRegisterInfo &MRI,
                                      MCContext &Ctx);
 
-MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
+MCAsmBackend *createAMDGPUAsmBackend(const MCTargetMachine &MTM,
+                                     const MCRegisterInfo &MRI,
                                      const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
                                             raw_pwrite_stream &OS);
 } // End llvm namespace
 
 #define GET_REGINFO_ENUM
 #include "AMDGPUGenRegisterInfo.inc"
 
 #define GET_INSTRINFO_ENUM
 #include "AMDGPUGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_ENUM
 #include "AMDGPUGenSubtargetInfo.inc"
 
 #endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

 #include "InstPrinter/AMDGPUInstPrinter.h"
 #include "SIDefines.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AMDGPUGenInstrInfo.inc"
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
   if (T.getOS() == Triple::AMDHSA)
     return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 
   return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 }
 
 extern "C" void LLVMInitializeAMDGPUTargetMC() {
   for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
 
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 #include "ARMGenDisassemblerTables.inc"
 
-static MCDisassembler *createARMDisassembler(const Target &T,
+static MCDisassembler *createARMDisassembler(const MCTargetMachine &,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
   return new ARMDisassembler(STI, Ctx);
 }
 
-static MCDisassembler *createThumbDisassembler(const Target &T,
+static MCDisassembler *createThumbDisassembler(const MCTargetMachine &,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
   return new ThumbDisassembler(STI, Ctx);
 }
 
 // Post-decoding checks
 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
                                             uint64_t Address, raw_ostream &OS,

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

 
 namespace {
 
 class ARMAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo *STI;
   bool isThumbMode;    // Currently emitting Thumb code.
   bool IsLittleEndian; // Big or little endian.
 public:
-  ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
+  ARMAsmBackend(const Triple &TT, bool IsLittle)
       : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
         isThumbMode(TT.getArchName().startswith("thumb")),
         IsLittleEndian(IsLittle) {}
 
   ~ARMAsmBackend() override { delete STI; }
 
   unsigned getNumFixupKinds() const override {
     return ARM::NumTargetFixupKinds;

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

case ARM::AK_ARMV6M:
     return MachO::CPU_SUBTYPE_ARM_V6M;
   case ARM::AK_ARMV7M:
     return MachO::CPU_SUBTYPE_ARM_V7M;
   case ARM::AK_ARMV7EM:
     return MachO::CPU_SUBTYPE_ARM_V7EM;
   }
 }
 
-MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
-                                        const MCRegisterInfo &MRI,
+MCAsmBackend *llvm::createARMAsmBackend(const MCRegisterInfo &MRI,
                                         const Triple &TheTriple, StringRef CPU,
                                         bool isLittle) {
   switch (TheTriple.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
   case Triple::MachO: {
     MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
-    return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS);
+    return new ARMAsmBackendDarwin(TheTriple, MRI, CS);
   }
   case Triple::COFF:
     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, TheTriple);
+    return new ARMAsmBackendWinCOFF(TheTriple);
   case Triple::ELF:
     assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
     uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-    return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
+    return new ARMAsmBackendELF(TheTriple, OSABI, isLittle);
   }
 }
 
-MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
+MCAsmBackend *llvm::createARMLEAsmBackend(const MCTargetMachine &,
                                           const MCRegisterInfo &MRI,
                                           const Triple &TT, StringRef CPU) {
-  return createARMAsmBackend(T, MRI, TT, CPU, true);
+  return createARMAsmBackend(MRI, TT, CPU, true);
 }
 
-MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
+MCAsmBackend *llvm::createARMBEAsmBackend(const MCTargetMachine &,
                                           const MCRegisterInfo &MRI,
                                           const Triple &TT, StringRef CPU) {
-  return createARMAsmBackend(T, MRI, TT, CPU, false);
+  return createARMAsmBackend(MRI, TT, CPU, false);
 }
 
-MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
+MCAsmBackend *llvm::createThumbLEAsmBackend(const MCTargetMachine &,
                                             const MCRegisterInfo &MRI,
                                             const Triple &TT, StringRef CPU) {
-  return createARMAsmBackend(T, MRI, TT, CPU, true);
+  return createARMAsmBackend(MRI, TT, CPU, true);
 }
 
-MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
+MCAsmBackend *llvm::createThumbBEAsmBackend(const MCTargetMachine &,
                                             const MCRegisterInfo &MRI,
                                             const Triple &TT, StringRef CPU) {
-  return createARMAsmBackend(T, MRI, TT, CPU, false);
+  return createARMAsmBackend(MRI, TT, CPU, false);
 }

lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h

 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
   const MCRegisterInfo &MRI;
 public:
   const MachO::CPUSubTypeARM Subtype;
-  ARMAsmBackendDarwin(const Target &T, const Triple &TT,
-                      const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
-      : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) {
+  ARMAsmBackendDarwin(const Triple &TT, const MCRegisterInfo &MRI,
+                      MachO::CPUSubTypeARM st)
+      : ARMAsmBackend(TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) {
     HasDataInCodeSupport = true;
   }
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPU_TYPE_ARM,
                                      Subtype);
   }
 
   uint32_t generateCompactUnwindEncoding(
       ArrayRef<MCCFIInstruction> Instrs) const override;
 };
 }
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h

 #ifndef LLVM_LIB_TARGET_ARM_ELFARMASMBACKEND_H
 #define LLVM_LIB_TARGET_ARM_ELFARMASMBACKEND_H
 
 using namespace llvm;
 namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
-                   bool IsLittle)
-      : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
+  ARMAsmBackendELF(const Triple &TT, uint8_t OSABI, bool IsLittle)
+      : ARMAsmBackend(TT, IsLittle), OSABI(OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMELFObjectWriter(OS, OSABI, isLittle());
   }
 };
 }
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h

 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKENDWINCOFF_H
 #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDWINCOFF_H
 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
-      : ARMAsmBackend(T, TheTriple, true) {}
+  ARMAsmBackendWinCOFF(const Triple &TheTriple)
+      : ARMAsmBackend(TheTriple, true) {}
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
   }
 };
 }
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class MCContext;
 class MCInstrInfo;
 class MCInstPrinter;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCStreamer;
 class MCRelocationInfo;
+class MCTargetMachine;
 class MCTargetStreamer;
 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheARMLETarget, TheThumbLETarget;

 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
-MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU,
-                                  bool IsLittleEndian);
-
-MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+MCAsmBackend *createARMAsmBackend(const MCRegisterInfo &MRI, const Triple &TT,
+                                  StringRef CPU, bool IsLittleEndian);
 
-MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+MCAsmBackend *createARMLEAsmBackend(const MCTargetMachine &MTM,
+                                    const MCRegisterInfo &MRI, const Triple &TT,
+                                    StringRef CPU);
+
+MCAsmBackend *createARMBEAsmBackend(const MCTargetMachine &MTM,
+                                    const MCRegisterInfo &MRI, const Triple &TT,
+                                    StringRef CPU);
 
-MCAsmBackend *createThumbLEAsmBackend(const Target &T,
+MCAsmBackend *createThumbLEAsmBackend(const MCTargetMachine &MTM,
                                       const MCRegisterInfo &MRI,
                                       const Triple &TT, StringRef CPU);
 
-MCAsmBackend *createThumbBEAsmBackend(const Target &T,
+MCAsmBackend *createThumbBEAsmBackend(const MCTargetMachine &MTM,
                                       const MCRegisterInfo &MRI,
                                       const Triple &TT, StringRef CPU);
 
 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
 // object file.
 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
                                      raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll);

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_MC_DESC
 #include "ARMGenRegisterInfo.inc"

 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
   return new ARMMCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeARMTargetMC() {
   for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
                     &TheThumbBETarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);

lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

void BPFAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
   }
 }
 
 MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
   return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
 }
 }
 
-MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
+MCAsmBackend *llvm::createBPFAsmBackend(const MCTargetMachine &MTM,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TT, StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/true);
 }
 
-MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
+MCAsmBackend *llvm::createBPFbeAsmBackend(const MCTargetMachine &MTM,
                                           const MCRegisterInfo &MRI,
                                           const Triple &TT, StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/false);
 }

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheBPFleTarget;
 extern Target TheBPFbeTarget;
 extern Target TheBPFTarget;
 
 MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
-MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU);
-MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+MCAsmBackend *createBPFAsmBackend(const MCTargetMachine &MTM,
+                                  const MCRegisterInfo &MRI, const Triple &TT,
+                                  StringRef CPU);
+MCAsmBackend *createBPFbeAsmBackend(const MCTargetMachine &MTM,
+                                    const MCRegisterInfo &MRI, const Triple &TT,
+                                    StringRef CPU);
 
 MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
                                          uint8_t OSABI, bool IsLittleEndian);
 }
 
 // Defines symbolic names for BPF registers.  This defines a mapping from
 // register name to register number.
 //

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

 #include "BPFMCTargetDesc.h"
 #include "BPFMCAsmInfo.h"
 #include "InstPrinter/BPFInstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC
 #include "BPFGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "BPFGenSubtargetInfo.inc"
static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new BPFInstPrinter(MAI, MII, MRI);
   return 0;
 }
 
 extern "C" void LLVMInitializeBPFTargetMC() {
   for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);

lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "hexagon-disassembler"
 
 #include "Hexagon.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonInstPrinter.h"
 #include "MCTargetDesc/HexagonMCChecker.h"
-#include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-#include "MCTargetDesc/HexagonInstPrinter.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "llvm/ADT/StringExtras.h"
-#include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/MemoryObject.h"
-#include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/raw_ostream.h"
 #include <vector>
 
 using namespace llvm;
 using namespace Hexagon;
 
 typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 namespace {
 /// \brief Hexagon disassembler for all Hexagon platforms.
 class HexagonDisassembler : public MCDisassembler {
 public:
   std::unique_ptr<MCInstrInfo const> const MCII;
   std::unique_ptr<MCInst *> CurrentBundle;
   HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
-                      MCInstrInfo const *MCII)
-      : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}
+                      std::unique_ptr<const MCInstrInfo> MCII)
+      : MCDisassembler(STI, Ctx), MCII(std::move(MCII)),
+        CurrentBundle(new MCInst *) {}
 
   DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
                                     ArrayRef<uint8_t> Bytes, uint64_t Address,
                                     raw_ostream &VStream, raw_ostream &CStream,
                                     bool &Complete) const;
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &VStream,
static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
                                    const void *Decoder);
 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
                                    const void *Decoder);
 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
                                     const void *Decoder);
 
 #include "HexagonGenDisassemblerTables.inc"
 
-static MCDisassembler *createHexagonDisassembler(const Target &T,
+static MCDisassembler *createHexagonDisassembler(const MCTargetMachine &MCTM,
                                                  const MCSubtargetInfo &STI,
                                                  MCContext &Ctx) {
-  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
+  std::unique_ptr<const MCInstrInfo> MII(MCTM.createMCInstrInfo());
+  return new HexagonDisassembler(STI, Ctx, std::move(MII));
 }
 
 extern "C" void LLVMInitializeHexagonDisassembler() {
   TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
                                          createHexagonDisassembler);
 }
 
 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCAsmLayout.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 using namespace Hexagon;
 
 #define DEBUG_TYPE "hexagon-asm-backend"
 
 namespace {
 
 class HexagonAsmBackend : public MCAsmBackend {
   uint8_t OSABI;
   StringRef CPU;
   mutable uint64_t relaxedCnt;
   std::unique_ptr <MCInstrInfo> MCII;
   std::unique_ptr <MCInst *> RelaxTarget;
   MCInst * Extender;
 public:
-  HexagonAsmBackend(Target const &T,  uint8_t OSABI, StringRef CPU) :
-    OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
+  HexagonAsmBackend(const MCTargetMachine &MCTM, uint8_t OSABI, StringRef CPU)
+      : OSABI(OSABI), MCII(MCTM.createMCInstrInfo()), RelaxTarget(new MCInst *),
         Extender(nullptr) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createHexagonELFObjectWriter(OS, OSABI, CPU);
   }
 
   void setExtender(MCContext &Context) const {
     if (Extender == nullptr)
       const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
while(Count) {
       OW->write32(Nopcode | ParseBits);
     }
     return true;
   }
 };
 } // end anonymous namespace
 
 namespace llvm {
-MCAsmBackend *createHexagonAsmBackend(Target const &T,
+MCAsmBackend *createHexagonAsmBackend(const MCTargetMachine &MTM,
                                       MCRegisterInfo const & /*MRI*/,
                                       const Triple &TT, StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  return new HexagonAsmBackend(T, OSABI, CPU);
+  return new HexagonAsmBackend(MTM, OSABI, CPU);
 }
 }

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

 struct InstrStage;
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class Target;
 class Triple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheHexagonTarget;
 extern cl::opt<bool> HexagonDisableCompound;
 extern cl::opt<bool> HexagonDisableDuplex;
 extern const InstrStage HexagonStages[];
 
 MCInstrInfo *createHexagonMCInstrInfo();
 
 MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
                                           MCRegisterInfo const &MRI,
                                           MCContext &MCT);
 
-MCAsmBackend *createHexagonAsmBackend(Target const &T,
+MCAsmBackend *createHexagonAsmBackend(const MCTargetMachine &MTM,
                                       MCRegisterInfo const &MRI,
                                       const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI, StringRef CPU);
 
 } // End llvm namespace
 

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC

 
 static MCTargetStreamer *
 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
   return new HexagonTargetELFStreamer(S, STI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeHexagonTargetMC() {
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheHexagonTarget);
+
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
                                         createHexagonMCCodeGenInfo);
 
   // Register the MC instruction info.

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

 
 #include "MSP430MCTargetDesc.h"
 #include "InstPrinter/MSP430InstPrinter.h"
 #include "MSP430MCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "MSP430GenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new MSP430InstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 extern "C" void LLVMInitializeMSP430TargetMC() {
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheMSP430Target);
+
   // Register the MC asm info.
   RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target,
                                         createMSP430MCCodeGenInfo);
 
   // Register the MC instruction info.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
                                        const void *Decoder);
 
 namespace llvm {
 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
               TheMips64elTarget;
 }
 
-static MCDisassembler *createMipsDisassembler(
-                       const Target &T,
+static MCDisassembler *createMipsDisassembler(const MCTargetMachine &,
                                               const MCSubtargetInfo &STI,
                                               MCContext &Ctx) {
   return new MipsDisassembler(STI, Ctx, true);
 }
 
-static MCDisassembler *createMipselDisassembler(
-                       const Target &T,
+static MCDisassembler *createMipselDisassembler(const MCTargetMachine &,
                                                 const MCSubtargetInfo &STI,
                                                 MCContext &Ctx) {
   return new MipsDisassembler(STI, Ctx, false);
 }
 
 extern "C" void LLVMInitializeMipsDisassembler() {
   // Register the disassembler.
   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
                                          createMipsDisassembler);
   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

 class MCObjectWriter;
 
 class MipsAsmBackend : public MCAsmBackend {
   Triple::OSType OSType;
   bool IsLittle; // Big or little endian
   bool Is64Bit;  // 32 or 64 bit words
 
 public:
-  MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
-                 bool Is64Bit)
+  MipsAsmBackend(Triple::OSType OSType, bool IsLittle, bool Is64Bit)
       : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value, bool IsPCRel) const override;
 
   bool getFixupKind(StringRef Name, MCFixupKind &MappedKind) const override;

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
   // At this point we'll ignore the value returned by adjustFixupValue as
   // we are only checking if the fixup can be applied correctly. We have
   // access to MCContext from here which allows us to report a fatal error
   // with *possibly* a source code location.
   (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
 }
 
 // MCAsmBackend
-MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
+MCAsmBackend *llvm::createMipsAsmBackendEL32(const MCTargetMachine &MTM,
                                              const MCRegisterInfo &MRI,
                                              const Triple &TT, StringRef CPU) {
-  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
+  return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ true,
                             /*Is64Bit*/ false);
 }
 
-MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
+MCAsmBackend *llvm::createMipsAsmBackendEB32(const MCTargetMachine &MTM,
                                              const MCRegisterInfo &MRI,
                                              const Triple &TT, StringRef CPU) {
-  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
+  return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ false);
 }
 
-MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
+MCAsmBackend *llvm::createMipsAsmBackendEL64(const MCTargetMachine &MTM,
                                              const MCRegisterInfo &MRI,
                                              const Triple &TT, StringRef CPU) {
-  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
+  return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
 }
 
-MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
+MCAsmBackend *llvm::createMipsAsmBackendEB64(const MCTargetMachine &MTM,
                                              const MCRegisterInfo &MRI,
                                              const Triple &TT, StringRef CPU) {
-  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
+  return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ true);
 }

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheMipsTarget;
 extern Target TheMipselTarget;
 extern Target TheMips64Target;
 extern Target TheMips64elTarget;
 
 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
                                          const MCRegisterInfo &MRI,
                                          MCContext &Ctx);
 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
                                          const MCRegisterInfo &MRI,
                                          MCContext &Ctx);
 
-MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
+MCAsmBackend *createMipsAsmBackendEB32(const MCTargetMachine &MTM,
                                        const MCRegisterInfo &MRI,
                                        const Triple &TT, StringRef CPU);
-MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
+MCAsmBackend *createMipsAsmBackendEL32(const MCTargetMachine &MTM,
                                        const MCRegisterInfo &MRI,
                                        const Triple &TT, StringRef CPU);
-MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
+MCAsmBackend *createMipsAsmBackendEB64(const MCTargetMachine &MTM,
                                        const MCRegisterInfo &MRI,
                                        const Triple &TT, StringRef CPU);
-MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
+MCAsmBackend *createMipsAsmBackendEL64(const MCTargetMachine &MTM,
                                        const MCRegisterInfo &MRI,
                                        const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
                                           bool IsLittleEndian, bool Is64Bit);
 
 namespace MIPS_MC {
 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 #include "MipsMCTargetDesc.h"
 #include "MipsTargetStreamer.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;

 static MCTargetStreamer *
 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
   return new MipsTargetELFStreamer(S, STI);
 }
 
 extern "C" void LLVMInitializeMipsTargetMC() {
   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
                     &TheMips64elTarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);

lib/Target/Mips/MipsAsmPrinter.cpp

 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetOptions.h"
 #include <string>
 
 using namespace llvm;
void MipsAsmPrinter::EmitFPCallStub(
     const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
   MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
   using namespace Mips16HardFloatInfo;
   bool LE = getDataLayout().isLittleEndian();
   // Construct a local MCSubtargetInfo here.
   // This is because the MachineFunction won't exist (but have not yet been
   // freed) and since we're at the global level we can use the default
   // constructed subtarget.
-  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
-      TM.getTargetTriple().str(), TM.getTargetCPU(),
-      TM.getTargetFeatureString()));
+  std::unique_ptr<MCSubtargetInfo> STI(
+      TM.getMCTargetMachine()->createMCSubtargetInfo(
+          TM.getTargetCPU(), TM.getTargetFeatureString()));
 
   //
   // .global xxxx
   //
   OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
   const char *RetType;
   //
   // make the comment field identifying the return and parameter

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

 
 #include "NVPTXMCTargetDesc.h"
 #include "InstPrinter/NVPTXInstPrinter.h"
 #include "NVPTXMCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "NVPTXGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
   if (SyntaxVariant == 0)
     return new NVPTXInstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeNVPTXTargetMC() {
   for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

public:
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &VStream,
                               raw_ostream &CStream) const override;
 };
 } // end anonymous namespace
 
-static MCDisassembler *createPPCDisassembler(const Target &T,
+static MCDisassembler *createPPCDisassembler(const MCTargetMachine &,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
   return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
 }
 
-static MCDisassembler *createPPCLEDisassembler(const Target &T,
+static MCDisassembler *createPPCLEDisassembler(const MCTargetMachine &,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
   return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
 }
 
 extern "C" void LLVMInitializePowerPCDisassembler() {
   // Register the disassembler for each target.
   TargetRegistry::RegisterMCDisassembler(ThePPC32Target,

lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachO.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
public:
     MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
       bool is64 = getPointerSize() == 8;
       return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI);
     }
   };
 
 } // end anonymous namespace
 
-MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
+MCAsmBackend *llvm::createPPCAsmBackend(const MCTargetMachine &MTM,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TT, StringRef CPU) {
   if (TT.isOSDarwin())
-    return new DarwinPPCAsmBackend(T);
+    return new DarwinPPCAsmBackend(MTM.getTarget());
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
-  return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
+  return new ELFPPCAsmBackend(MTM.getTarget(), IsLittleEndian, OSABI);
 }

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class Target;
 class Triple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target ThePPC32Target;
 extern Target ThePPC64Target;
 extern Target ThePPC64LETarget;
 
 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 
-MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU);
+MCAsmBackend *createPPCAsmBackend(const MCTargetMachine &MTM,
+                                  const MCRegisterInfo &MRI, const Triple &TT,
+                                  StringRef CPU);
 
 /// Construct an PPC ELF object writer.
 MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                          bool IsLittleEndian, uint8_t OSABI);
 /// Construct a PPC Mach-O object writer.
 MCObjectWriter *createPPCMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                           uint32_t CPUType,
                                           uint32_t CPUSubtype);

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCSymbolELF.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
 }
 
 extern "C" void LLVMInitializePowerPCTargetMC() {
   for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);

lib/Target/PowerPC/PPCAsmPrinter.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"

 void PPCDarwinAsmPrinter::
 EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
   bool isPPC64 = getDataLayout().getPointerSizeInBits() == 64;
 
   // Construct a local MCSubtargetInfo and shadow EmitToStreamer here.
   // This is because the MachineFunction won't exist (but have not yet been
   // freed) and since we're at the global level we can use the default
   // constructed subtarget.
-  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
-      TM.getTargetTriple().str(), TM.getTargetCPU(),
-      TM.getTargetFeatureString()));
+  std::unique_ptr<MCSubtargetInfo> STI(
+      TM.getMCTargetMachine()->createMCSubtargetInfo(
+          TM.getTargetCPU(), TM.getTargetFeatureString()));
   auto EmitToStreamer = [&STI] (MCStreamer &S, const MCInst &Inst) {
     S.EmitInstruction(Inst, *STI);
   };
 
   const TargetLoweringObjectFileMachO &TLOFMacho =
       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
 
   // .lazy_symbol_pointer

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               raw_ostream &CStream) const override;
 };
 }
 
 namespace llvm {
 extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
 }
 
-static MCDisassembler *createSparcDisassembler(const Target &T,
+static MCDisassembler *createSparcDisassembler(const MCTargetMachine &,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
   return new SparcDisassembler(STI, Ctx);
 }
 
 
 extern "C" void LLVMInitializeSparcDisassembler() {
   // Register the disassembler.

lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCAsmBackend.h"
 #include "MCTargetDesc/SparcFixupKinds.h"
 #include "MCTargetDesc/SparcMCTargetDesc.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   switch (Kind) {
   default:
public:
     MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
       uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
       return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
     }
   };
 
 } // end anonymous namespace
 
-MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
+MCAsmBackend *llvm::createSparcAsmBackend(const MCTargetMachine &MTM,
                                           const MCRegisterInfo &MRI,
                                           const Triple &TT, StringRef CPU) {
-  return new ELFSparcAsmBackend(T, TT.getOS());
+  return new ELFSparcAsmBackend(MTM.getTarget(), TT.getOS());
 }

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h

 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class Target;
 class Triple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheSparcTarget;
 extern Target TheSparcV9Target;
 extern Target TheSparcelTarget;
 
 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
-MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+MCAsmBackend *createSparcAsmBackend(const MCTargetMachine &MTM,
+                                    const MCRegisterInfo &MRI, const Triple &TT,
+                                    StringRef CPU);
 MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                            bool IsLIttleEndian, uint8_t OSABI);
 } // End llvm namespace
 
 // Defines symbolic names for Sparc registers.  This defines a mapping from
 // register name to register number.
 //
 #define GET_REGINFO_ENUM

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

 #include "SparcMCTargetDesc.h"
 #include "InstPrinter/SparcInstPrinter.h"
 #include "SparcMCAsmInfo.h"
 #include "SparcTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SparcGenInstrInfo.inc"
 

 
 extern "C" void LLVMInitializeSparcTargetMC() {
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo);
   RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo);
   RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo);
 
   for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
 
     // Register the MC register info.
     TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
 
     // Register the MC subtarget info.
     TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo);

lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp

public:
 
   DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &VStream,
                               raw_ostream &CStream) const override;
 };
 } // end anonymous namespace
 
-static MCDisassembler *createSystemZDisassembler(const Target &T,
+static MCDisassembler *createSystemZDisassembler(const MCTargetMachine &,
                                                  const MCSubtargetInfo &STI,
                                                  MCContext &Ctx) {
   return new SystemZDisassembler(STI, Ctx);
 }
 
 extern "C" void LLVMInitializeSystemZDisassembler() {
   // Register the disassembler.
   TargetRegistry::RegisterMCDisassembler(TheSystemZTarget,

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

 
 bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
                                        MCObjectWriter *OW) const {
   for (uint64_t I = 0; I != Count; ++I)
     OW->write8(7);
   return true;
 }
 
-MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
+MCAsmBackend *llvm::createSystemZMCAsmBackend(const MCTargetMachine &,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TT, StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

 
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class StringRef;
 class Target;
 class Triple;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheSystemZTarget;
 
inline unsigned getRegAsVR128(unsigned Reg) {
   return VR128Regs[getFirstReg(Reg)];
 }
 } // end namespace SystemZMC
 
 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
                                           const MCRegisterInfo &MRI,
                                           MCContext &Ctx);
 
-MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
+MCAsmBackend *createSystemZMCAsmBackend(const MCTargetMachine &MTM,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
 } // end namespace llvm
 
 // Defines symbolic names for SystemZ registers.
 // This defines a mapping from register name to register number.

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

 #include "SystemZMCTargetDesc.h"
 #include "InstPrinter/SystemZInstPrinter.h"
 #include "SystemZMCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SystemZGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   return new SystemZInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSystemZTargetMC() {
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheSystemZTarget);
+
   // Register the MCAsmInfo.
   TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget,
                                     createSystemZMCAsmInfo);
 
   // Register the MCCodeGenInfo.
   TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
                                         createSystemZMCCodeGenInfo);
 

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCObjectWriter;
 class MCStreamer;
 class MCSubtargetInfo;
+class MCTargetMachine;
 class MCTargetStreamer;
 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 
 extern Target TheWebAssemblyTarget32;
 extern Target TheWebAssemblyTarget64;
 
-MCAsmBackend *createWebAssemblyAsmBackend(const Target &T,
+MCAsmBackend *createWebAssemblyAsmBackend(const MCTargetMachine &MTM,
                                           const MCRegisterInfo &MRI,
                                           StringRef TT, StringRef CPU);
 
 } // end namespace llvm
 
 // Defines symbolic names for WebAssembly registers. This defines a mapping from
 // register name to register number.
 //

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

 #include "WebAssemblyMCTargetDesc.h"
 #include "InstPrinter/WebAssemblyInstPrinter.h"
 #include "WebAssemblyMCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-target-desc"
 
 #define GET_INSTRINFO_MC_DESC
 #include "WebAssemblyGenInstrInfo.inc"
createWebAssemblyMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
                                const MCRegisterInfo &MRI) {
   assert(SyntaxVariant == 0);
   return new WebAssemblyInstPrinter(MAI, MII, MRI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeWebAssemblyTargetMC() {
   for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createWebAssemblyMCInstrInfo);
 
     // Register the MCInstPrinter.
     TargetRegistry::RegisterMCInstPrinter(*T, createWebAssemblyMCInstPrinter);
   }
 }

lib/Target/X86/Disassembler/LLVMBuild.txt

 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
 [component_0]
 type = Library
 name = X86Disassembler
 parent = X86
-required_libraries = MCDisassembler Support X86Info
+required_libraries = MC MCDisassembler Support X86Info
 add_to_library_groups = X86

lib/Target/X86/Disassembler/X86Disassembler.h

 
 namespace X86Disassembler {
 
 /// Generic disassembler for all X86 platforms. All each platform class should
 /// have to do is subclass the constructor, and provide a different
 /// disassemblerMode value.
 class X86GenericDisassembler : public MCDisassembler {
   std::unique_ptr<const MCInstrInfo> MII;
+
 public:
   X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
                          std::unique_ptr<const MCInstrInfo> MII);
+
 public:
   DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &vStream,
                               raw_ostream &cStream) const override;
 
 private:
   DisassemblerMode              fMode;
 };
 
 } // namespace X86Disassembler
 
 } // namespace llvm
 
 #endif

lib/Target/X86/Disassembler/X86Disassembler.cpp

 #include "X86Disassembler.h"
 #include "X86DisassemblerDecoder.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 using namespace llvm::X86Disassembler;
 
 #define DEBUG_TYPE "x86-disassembler"

 
 }
 
 static bool translateInstruction(MCInst &target,
                                 InternalInstruction &source,
                                 const MCDisassembler *Dis);
 
 X86GenericDisassembler::X86GenericDisassembler(
-                                         const MCSubtargetInfo &STI,
-                                         MCContext &Ctx,
-                                         std::unique_ptr<const MCInstrInfo> MII)
+    const MCSubtargetInfo &STI, MCContext &Ctx,
     : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
   const FeatureBitset &FB = STI.getFeatureBits();
   if (FB[X86::Mode16Bit]) {
     fMode = MODE_16BIT;
     return;
   } else if (FB[X86::Mode32Bit]) {
     fMode = MODE_32BIT;
     return;
   } else if (FB[X86::Mode64Bit]) {
if (Op.encoding != ENCODING_NONE) {
         return true;
       }
     }
   }
 
   return false;
 }
 
-static MCDisassembler *createX86Disassembler(const Target &T,
+static MCDisassembler *createX86Disassembler(const MCTargetMachine &MCTM,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
-  std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
+  std::unique_ptr<const MCInstrInfo> MII(MCTM.createMCInstrInfo());
   return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
 }
 
 extern "C" void LLVMInitializeX86Disassembler() {
   // Register the disassembler.
   TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
                                          createX86Disassembler);
   TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
                                          createX86Disassembler);
 }

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
     : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
 };
 
 class X86AsmBackend : public MCAsmBackend {
   const StringRef CPU;
   bool HasNopl;
   const uint64_t MaxNopLength;
 public:
-  X86AsmBackend(const Target &T, StringRef CPU)
+  X86AsmBackend(StringRef CPU)
       : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) {
     HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
               CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
               CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
               CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
               CPU != "c3" && CPU != "c3-2";
   }
 

 
 /* *** */
 
 namespace {
 
 class ELFX86AsmBackend : public X86AsmBackend {
 public:
   uint8_t OSABI;
-  ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : X86AsmBackend(T, CPU), OSABI(OSABI) {}
+  ELFX86AsmBackend(uint8_t OSABI, StringRef CPU)
+      : X86AsmBackend(CPU), OSABI(OSABI) {}
 };
 
 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-    : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_32AsmBackend(uint8_t OSABI, StringRef CPU)
+      : ELFX86AsmBackend(OSABI, CPU) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
   }
 };
 
 class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_X32AsmBackend(uint8_t OSABI, StringRef CPU)
+      : ELFX86AsmBackend(OSABI, CPU) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
                                     ELF::EM_X86_64);
   }
 };
 
 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_IAMCUAsmBackend(uint8_t OSABI, StringRef CPU)
+      : ELFX86AsmBackend(OSABI, CPU) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
                                     ELF::EM_IAMCU);
   }
 };
 
 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-    : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_64AsmBackend(uint8_t OSABI, StringRef CPU)
+      : ELFX86AsmBackend(OSABI, CPU) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
   }
 };
 
 class WindowsX86AsmBackend : public X86AsmBackend {
   bool Is64Bit;
 
 public:
-  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
-    : X86AsmBackend(T, CPU)
-    , Is64Bit(is64Bit) {
-  }
+  WindowsX86AsmBackend(bool is64Bit, StringRef CPU)
+      : X86AsmBackend(CPU), Is64Bit(is64Bit) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86WinCOFFObjectWriter(OS, Is64Bit);
   }
 };
 
 namespace CU {
 
uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
     }
 
     assert((permutationEncoding & 0x3FF) == permutationEncoding &&
            "Invalid compact register encoding!");
     return permutationEncoding;
   }
 
 public:
-  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
-                      bool Is64Bit)
-    : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
+  DarwinX86AsmBackend(const MCRegisterInfo &MRI, StringRef CPU, bool Is64Bit)
+      : X86AsmBackend(CPU), MRI(MRI), Is64Bit(Is64Bit) {
     memset(SavedRegs, 0, sizeof(SavedRegs));
     OffsetSize = Is64Bit ? 8 : 4;
     MoveInstrSize = Is64Bit ? 3 : 2;
     StackDivide = Is64Bit ? 8 : 4;
   }
 };
 
 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
 public:
-  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                         StringRef CPU)
-      : DarwinX86AsmBackend(T, MRI, CPU, false) {}
+  DarwinX86_32AsmBackend(const MCRegisterInfo &MRI, StringRef CPU)
+      : DarwinX86AsmBackend(MRI, CPU, false) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
                                      MachO::CPU_TYPE_I386,
                                      MachO::CPU_SUBTYPE_I386_ALL);
   }
 
   /// \brief Generate the compact unwind encoding for the CFI instructions.
   uint32_t generateCompactUnwindEncoding(
                              ArrayRef<MCCFIInstruction> Instrs) const override {
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
   const MachO::CPUSubTypeX86 Subtype;
 public:
-  DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                         StringRef CPU, MachO::CPUSubTypeX86 st)
-      : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
+  DarwinX86_64AsmBackend(const MCRegisterInfo &MRI, StringRef CPU,
+                         MachO::CPUSubTypeX86 st)
+      : DarwinX86AsmBackend(MRI, CPU, true), Subtype(st) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
                                      MachO::CPU_TYPE_X86_64, Subtype);
   }
 
   /// \brief Generate the compact unwind encoding for the CFI instructions.
   uint32_t generateCompactUnwindEncoding(
                              ArrayRef<MCCFIInstruction> Instrs) const override {
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 } // end anonymous namespace
 
-MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
+MCAsmBackend *llvm::createX86_32AsmBackend(const MCTargetMachine &MTM,
                                            const MCRegisterInfo &MRI,
                                            const Triple &TheTriple,
                                            StringRef CPU) {
   if (TheTriple.isOSBinFormatMachO())
-    return new DarwinX86_32AsmBackend(T, MRI, CPU);
+    return new DarwinX86_32AsmBackend(MRI, CPU);
 
   if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
-    return new WindowsX86AsmBackend(T, false, CPU);
+    return new WindowsX86AsmBackend(false, CPU);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.isOSIAMCU())
-    return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
+    return new ELFX86_IAMCUAsmBackend(OSABI, CPU);
 
-  return new ELFX86_32AsmBackend(T, OSABI, CPU);
+  return new ELFX86_32AsmBackend(OSABI, CPU);
 }
 
-MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
+MCAsmBackend *llvm::createX86_64AsmBackend(const MCTargetMachine &MTM,
                                            const MCRegisterInfo &MRI,
                                            const Triple &TheTriple,
                                            StringRef CPU) {
   if (TheTriple.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
         StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
-    return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
+    return new DarwinX86_64AsmBackend(MRI, CPU, CS);
   }
 
   if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
-    return new WindowsX86AsmBackend(T, true, CPU);
+    return new WindowsX86AsmBackend(true, CPU);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.getEnvironment() == Triple::GNUX32)
-    return new ELFX86_X32AsmBackend(T, OSABI, CPU);
-  return new ELFX86_64AsmBackend(T, OSABI, CPU);
+    return new ELFX86_X32AsmBackend(OSABI, CPU);
+  return new ELFX86_64AsmBackend(OSABI, CPU);
 }

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCRelocationInfo;
 class MCStreamer;
+class MCTargetMachine;
 class Target;
 class Triple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheX86_32Target, TheX86_64Target;
 

 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 
-MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
+MCAsmBackend *createX86_32AsmBackend(const MCTargetMachine &MTM,
+                                     const MCRegisterInfo &MRI,
                                      const Triple &TT, StringRef CPU);
-MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
+MCAsmBackend *createX86_64AsmBackend(const MCTargetMachine &MTM,
+                                     const MCRegisterInfo &MRI,
                                      const Triple &TT, StringRef CPU);
 
 /// Construct an X86 Windows COFF machine code streamer which will generate
 /// PE/COFF format object files.
 ///
 /// Takes ownership of \p AB and \p CE.
 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
                                      raw_pwrite_stream &OS, MCCodeEmitter *CE,

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

 #include "X86MCAsmInfo.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #if _MSC_VER
 #include <intrin.h>
 #endif

 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
   return new MCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeX86TargetMC() {
   for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
+    RegisterMCTargetMachine<MCTargetMachine> Z(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
 
     // Register the MC codegen info.
     RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);

lib/Target/X86/X86MCInstLower.cpp

 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 namespace {
 
 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
 class X86MCInstLower {
   MCContext &Ctx;
namespace llvm {
    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
 
   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
 
   void
   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
     MF = &F;
-    CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
+    CodeEmitter.reset(TM.getMCTargetMachine()->createMCCodeEmitter(
         *MF->getSubtarget().getInstrInfo(),
         *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
   }
 
   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
                                                    const MCSubtargetInfo &STI) {
     if (InShadow) {
       SmallString<256> Code;

lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(
 
   return Fail;
 }
 
 namespace llvm {
   extern Target TheXCoreTarget;
 }
 
-static MCDisassembler *createXCoreDisassembler(const Target &T,
+static MCDisassembler *createXCoreDisassembler(const MCTargetMachine &,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
   return new XCoreDisassembler(STI, Ctx);
 }
 
 extern "C" void LLVMInitializeXCoreDisassembler() {
   // Register the disassembler.
   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
                                          createXCoreDisassembler);
 }

lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

 #include "XCoreMCTargetDesc.h"
 #include "InstPrinter/XCoreInstPrinter.h"
 #include "XCoreMCAsmInfo.h"
 #include "XCoreTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "XCoreGenInstrInfo.inc"
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm) {
   return new XCoreTargetAsmStreamer(S, OS);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeXCoreTargetMC() {
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheXCoreTarget);
+
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget,
                                         createXCoreMCCodeGenInfo);
 
   // Register the MC instruction info.

tools/dsymutil/DwarfLinker.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include <string>
 #include <tuple>

 
 /// \brief The Dwarf streaming logic
 ///
 /// All interactions with the MC layer that is used to build the debug
 /// information binary representation are handled in this class.
 class DwarfStreamer {
   /// \defgroup MCObjects MC layer objects constructed by the streamer
   /// @{
+  std::unique_ptr<MCTargetMachine> MTM;
   std::unique_ptr<MCRegisterInfo> MRI;
   std::unique_ptr<MCAsmInfo> MAI;
   std::unique_ptr<MCObjectFileInfo> MOFI;
   std::unique_ptr<MCContext> MC;
   MCAsmBackend *MAB; // Owned by MCStreamer
   std::unique_ptr<MCInstrInfo> MII;
   std::unique_ptr<MCSubtargetInfo> MSTI;
   MCCodeEmitter *MCE; // Owned by MCStreamer
bool DwarfStreamer::init(Triple TheTriple, StringRef OutputFilename) {
   // Get the target.
   const Target *TheTarget =
       TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr);
   if (!TheTarget)
     return error(ErrorStr, Context);
   TripleName = TheTriple.getTriple();
 
   // Create all the MC Objects.
-  MRI.reset(TheTarget->createMCRegInfo(TripleName));
+  MTM.reset(TheTarget->createMCTargetMachine(TheTriple));
+  if (!MTM)
+    return error(Twine("no MC target machine for target ") + TripleName, Context);
+
+  MRI.reset(MTM->createMCRegisterInfo());
   if (!MRI)
     return error(Twine("no register info for target ") + TripleName, Context);
 
-  MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  MAI.reset(MTM->createMCAsmInfo(*MRI));
   if (!MAI)
     return error("no asm info for target " + TripleName, Context);
 
   MOFI.reset(new MCObjectFileInfo);
   MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
   MOFI->InitMCObjectFileInfo(TheTriple, Reloc::Default, CodeModel::Default,
                              *MC);
 
-  MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "");
+  MAB = MTM->createMCAsmBackend(*MRI, "");
   if (!MAB)
     return error("no asm backend for target " + TripleName, Context);
 
-  MII.reset(TheTarget->createMCInstrInfo());
+  MII.reset(MTM->createMCInstrInfo());
   if (!MII)
     return error("no instr info info for target " + TripleName, Context);
 
-  MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+  MSTI.reset(MTM->createMCSubtargetInfo("", ""));
   if (!MSTI)
     return error("no subtarget info for target " + TripleName, Context);
 
-  MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
+  MCE = MTM->createMCCodeEmitter(*MII, *MRI, *MC);
   if (!MCE)
     return error("no code emitter for target " + TripleName, Context);
 
   // Create the output file.
   std::error_code EC;
   OutFile =
       llvm::make_unique<raw_fd_ostream>(OutputFilename, EC, sys::fs::F_None);
   if (EC)
     return error(Twine(OutputFilename) + ": " + EC.message(), Context);
 
-  MS = TheTarget->createMCObjectStreamer(TheTriple, *MC, *MAB, *OutFile, MCE,
-                                         *MSTI, false,
-                                         /*DWARFMustBeAtTheEnd*/ false);
+  MS = MTM->createMCObjectStreamer(*MC, *MAB, *OutFile, MCE, *MSTI, false,
   if (!MS)
     return error("no object streamer for target " + TripleName, Context);
 
   // Finally create the AsmPrinter we'll use to emit the DIEs.
   TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions()));
   if (!TM)
     return error("no target machine for target " + TripleName, Context);
 

tools/llvm-mc/Disassembler.cpp

 //===----------------------------------------------------------------------===//
 
 #include "Disassembler.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 typedef std::pair<std::vector<unsigned char>, std::vector<const char *>>
while (SkipToToken(Str)) {
     ByteArray.second.push_back(Value.data());
     Str = Str.substr(Next);
   }
 
   return false;
 }
 
 int Disassembler::disassemble(const Target &T,
-                              const std::string &Triple,
+                              const std::string &TripleStr,
                               MCSubtargetInfo &STI,
                               MCStreamer &Streamer,
                               MemoryBuffer &Buffer,
                               SourceMgr &SM,
                               raw_ostream &Out) {
+  Triple TT(TripleStr);
+  std::unique_ptr<const MCTargetMachine> MTM(T.createMCTargetMachine(TT));
+  if (!MTM) {
+    errs() << "error: no register info for target " << TripleStr << "\n";
+    return -1;
+  }
 
-  std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple));
+  std::unique_ptr<const MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
   if (!MRI) {
-    errs() << "error: no register info for target " << Triple << "\n";
+    errs() << "error: no register info for target " << TripleStr << "\n";
     return -1;
   }
 
-  std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, Triple));
+  std::unique_ptr<const MCAsmInfo> MAI(MTM->createMCAsmInfo(*MRI));
   if (!MAI) {
-    errs() << "error: no assembly info for target " << Triple << "\n";
+    errs() << "error: no assembly info for target " << TripleStr << "\n";
+    return -1;
+  }
+
+  std::unique_ptr<const MCInstrInfo> MII(MTM->createMCInstrInfo());
+  if (!MII) {
+    errs() << "error: no instruction info for target " << TripleStr << "\n";
     return -1;
   }
 
   // Set up the MCContext for creating symbols and MCExpr's.
   MCContext Ctx(MAI.get(), MRI.get(), nullptr);
 
   std::unique_ptr<const MCDisassembler> DisAsm(
-    T.createMCDisassembler(STI, Ctx));
+      MTM->createMCDisassembler(STI, Ctx));
   if (!DisAsm) {
-    errs() << "error: no disassembler for target " << Triple << "\n";
+    errs() << "error: no disassembler for target " << TripleStr << "\n";
     return -1;
   }
 
   // Set up initial section manually here
   Streamer.InitSections(false);
 
   bool ErrorOccurred = false;
 

tools/llvm-mc/llvm-mc.cpp

 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/AsmLexer.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetAsmParser.h"
 #include "llvm/MC/MCTargetOptionsCommandFlags.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/FileUtilities.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
for(auto &I: DefineSymbol){
     auto Symbol = Context.getOrCreateSymbol(Pair.first);
     Parser.getStreamer().EmitAssignment(Symbol,
                                         MCConstantExpr::create(Value, Context));
   }
   return 0;
 }
 
 static int AssembleInput(const char *ProgName, const Target *TheTarget,
-                         SourceMgr &SrcMgr, MCContext &Ctx, MCStreamer &Str,
-                         MCAsmInfo &MAI, MCSubtargetInfo &STI,
-                         MCInstrInfo &MCII, MCTargetOptions &MCOptions) {
+                         const MCTargetMachine &MTM, SourceMgr &SrcMgr,
+                         MCContext &Ctx, MCStreamer &Str, MCAsmInfo &MAI,
+                         MCSubtargetInfo &STI, MCInstrInfo &MCII,
+                         MCTargetOptions &MCOptions) {
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(SrcMgr, Ctx, Str, MAI));
   std::unique_ptr<MCTargetAsmParser> TAP(
-      TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions));
+      MTM.createMCAsmParser(STI, *Parser, MCII, MCOptions));
 
   if (!TAP) {
     errs() << ProgName
            << ": error: this target does not support assembly parsing.\n";
     return 1;
   }
 
   int SymbolResult = fillCommandLineSymbols(*Parser);
int main(int argc, char **argv) {
 
   // Tell SrcMgr about this buffer, which is what the parser will pick up.
   SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
 
   // Record the location of the include directories so that the lexer can find
   // it later.
   SrcMgr.setIncludeDirs(IncludeDirs);
 
-  std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
+  Triple TT(TripleName);
+  std::unique_ptr<MCTargetMachine> MTM(TheTarget->createMCTargetMachine(TT));
+  assert(MTM && "Unable to create target register info!");
+
+  std::unique_ptr<MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
   assert(MRI && "Unable to create target register info!");
 
-  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  std::unique_ptr<MCAsmInfo> MAI(MTM->createMCAsmInfo(*MRI));
   assert(MAI && "Unable to create target asm info!");
 
   if (CompressDebugSections) {
     if (!zlib::isAvailable()) {
       errs() << ProgName
              << ": build tools with zlib to enable -compress-debug-sections";
       return 1;
     }
int main(int argc, char **argv) {
   std::unique_ptr<tool_output_file> Out = GetOutputStream();
   if (!Out)
     return 1;
 
   std::unique_ptr<buffer_ostream> BOS;
   raw_pwrite_stream *OS = &Out->os();
   std::unique_ptr<MCStreamer> Str;
 
-  std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
+  std::unique_ptr<MCInstrInfo> MCII(MTM->createMCInstrInfo());
   std::unique_ptr<MCSubtargetInfo> STI(
-      TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
+      MTM->createMCSubtargetInfo(MCPU, FeaturesStr));
 
   MCInstPrinter *IP = nullptr;
   if (FileType == OFT_AssemblyFile) {
-    IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant,
-                                        *MAI, *MCII, *MRI);
+    IP = MTM->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI);
 
     // Set the display preference for hex vs. decimal immediates.
     IP->setPrintImmHex(PrintImmHex);
 
     // Set up the AsmStreamer.
     MCCodeEmitter *CE = nullptr;
     MCAsmBackend *MAB = nullptr;
     if (ShowEncoding) {
-      CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
-      MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
+      CE = MTM->createMCCodeEmitter(*MCII, *MRI, Ctx);
+      MAB = MTM->createMCAsmBackend(*MRI, MCPU);
     }
     auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
-    Str.reset(TheTarget->createAsmStreamer(
-        Ctx, std::move(FOut), /*asmverbose*/ true,
-        /*useDwarfDirectory*/ true, IP, CE, MAB, ShowInst));
+    Str.reset(MTM->createAsmStreamer(Ctx, std::move(FOut), /*asmverbose*/ true,
+                                     /*useDwarfDirectory*/ true, IP, CE, MAB,
+                                     ShowInst));
 
   } else if (FileType == OFT_Null) {
-    Str.reset(TheTarget->createNullStreamer(Ctx));
+    Str.reset(MTM->createNullStreamer(Ctx));
   } else {
     assert(FileType == OFT_ObjectFile && "Invalid file type!");
 
     // Don't waste memory on names of temp labels.
     Ctx.setUseNamesOnTempLabels(false);
 
     if (!Out->os().supportsSeeking()) {
       BOS = make_unique<buffer_ostream>(Out->os());
       OS = BOS.get();
     }
 
-    MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
-    MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
-    Str.reset(TheTarget->createMCObjectStreamer(TheTriple, Ctx, *MAB, *OS, CE,
-                                                *STI, RelaxAll,
-                                                /*DWARFMustBeAtTheEnd*/ false));
+    MCCodeEmitter *CE = MTM->createMCCodeEmitter(*MCII, *MRI, Ctx);
+    MCAsmBackend *MAB = MTM->createMCAsmBackend(*MRI, MCPU);
+    Str.reset(MTM->createMCObjectStreamer(Ctx, *MAB, *OS, CE, *STI, RelaxAll,
     if (NoExecStack)
       Str->InitSections(true);
   }
 
   int Res = 1;
   bool disassemble = false;
   switch (Action) {
   case AC_AsLex:
     Res = AsLexInput(SrcMgr, *MAI, Out->os());
     break;
   case AC_Assemble:
-    Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI,
-                        *MCII, MCOptions);
+    Res = AssembleInput(ProgName, TheTarget, *MTM, SrcMgr, Ctx, *Str, *MAI,
+                        *STI, *MCII, MCOptions);
     break;
   case AC_MDisassemble:
     assert(IP && "Expected assembly output");
     IP->setUseMarkup(1);
     disassemble = true;
     break;
   case AC_Disassemble:
     disassemble = true;

tools/llvm-objdump/MachODump.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/MachOUniversal.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/FormattedStream.h"
static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
   const Target *TheTarget = GetTarget(MachOOF, &McpuDefault, &ThumbTarget);
   if (!TheTarget) {
     // GetTarget prints out stuff.
     return;
   }
   if (MCPU.empty() && McpuDefault)
     MCPU = McpuDefault;
 
-  std::unique_ptr<const MCInstrInfo> InstrInfo(TheTarget->createMCInstrInfo());
-  std::unique_ptr<const MCInstrInfo> ThumbInstrInfo;
-  if (ThumbTarget)
-    ThumbInstrInfo.reset(ThumbTarget->createMCInstrInfo());
-
   // Package up features to be passed to target/subtarget
   std::string FeaturesStr;
   if (MAttrs.size()) {
     SubtargetFeatures Features;
     for (unsigned i = 0; i != MAttrs.size(); ++i)
       Features.AddFeature(MAttrs[i]);
     FeaturesStr = Features.getString();
   }
 
   // Set up disassembler.
-  std::unique_ptr<const MCRegisterInfo> MRI(
-      TheTarget->createMCRegInfo(TripleName));
-  std::unique_ptr<const MCAsmInfo> AsmInfo(
-      TheTarget->createMCAsmInfo(*MRI, TripleName));
+  Triple TT(TripleName);
+  std::unique_ptr<const MCTargetMachine> MTM(
+      TheTarget->createMCTargetMachine(TT));
+  std::unique_ptr<const MCInstrInfo> InstrInfo(MTM->createMCInstrInfo());
+  std::unique_ptr<const MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
+  std::unique_ptr<const MCAsmInfo> AsmInfo(MTM->createMCAsmInfo(*MRI));
   std::unique_ptr<const MCSubtargetInfo> STI(
-      TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
+      MTM->createMCSubtargetInfo(MCPU, FeaturesStr));
   MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr);
-  std::unique_ptr<MCDisassembler> DisAsm(
-      TheTarget->createMCDisassembler(*STI, Ctx));
+  std::unique_ptr<MCDisassembler> DisAsm(MTM->createMCDisassembler(*STI, Ctx));
   std::unique_ptr<MCSymbolizer> Symbolizer;
   struct DisassembleInfo SymbolizerInfo;
   std::unique_ptr<MCRelocationInfo> RelInfo(
       TheTarget->createMCRelocationInfo(TripleName, Ctx));
   if (RelInfo) {
     Symbolizer.reset(TheTarget->createMCSymbolizer(
         TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
         &SymbolizerInfo, &Ctx, std::move(RelInfo)));
     DisAsm->setSymbolizer(std::move(Symbolizer));
   }
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
-  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
+  std::unique_ptr<MCInstPrinter> IP(
+      MTM->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
   // Set the display preference for hex vs. decimal immediates.
   IP->setPrintImmHex(PrintImmHex);
   // Comment stream and backing vector.
   SmallString<128> CommentsToEmit;
   raw_svector_ostream CommentStream(CommentsToEmit);
   // FIXME: Setting the CommentStream in the InstPrinter is problematic in that
   // if it is done then arm64 comments for string literals don't get printed
   // and some constant get printed instead and not setting it causes intel
   // (32-bit and 64-bit) comments printed with different spacing before the
   // comment causing different diffs with the 'C' disassembler library API.
   // IP->setCommentStream(CommentStream);
 
   if (!AsmInfo || !STI || !DisAsm || !IP) {
     errs() << "error: couldn't initialize disassembler for target "
            << TripleName << '\n';
     return;
   }
 
   // Set up thumb disassembler.
+  std::unique_ptr<const MCTargetMachine> ThumbMTM;
+  std::unique_ptr<const MCInstrInfo> ThumbInstrInfo;
   std::unique_ptr<const MCRegisterInfo> ThumbMRI;
   std::unique_ptr<const MCAsmInfo> ThumbAsmInfo;
   std::unique_ptr<const MCSubtargetInfo> ThumbSTI;
   std::unique_ptr<MCDisassembler> ThumbDisAsm;
   std::unique_ptr<MCInstPrinter> ThumbIP;
   std::unique_ptr<MCContext> ThumbCtx;
   std::unique_ptr<MCSymbolizer> ThumbSymbolizer;
   struct DisassembleInfo ThumbSymbolizerInfo;
   std::unique_ptr<MCRelocationInfo> ThumbRelInfo;
   if (ThumbTarget) {
-    ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName));
-    ThumbAsmInfo.reset(
-        ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName));
-    ThumbSTI.reset(
-        ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MCPU, FeaturesStr));
+    Triple ThumbTT(ThumbTripleName);
+    ThumbMTM.reset(ThumbTarget->createMCTargetMachine(ThumbTT));
+    ThumbMRI.reset(ThumbMTM->createMCRegisterInfo());
+    ThumbAsmInfo.reset(ThumbMTM->createMCAsmInfo(*ThumbMRI));
+    ThumbSTI.reset(ThumbMTM->createMCSubtargetInfo(MCPU, FeaturesStr));
     ThumbCtx.reset(new MCContext(ThumbAsmInfo.get(), ThumbMRI.get(), nullptr));
-    ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx));
+    ThumbDisAsm.reset(ThumbMTM->createMCDisassembler(*ThumbSTI, *ThumbCtx));
     MCContext *PtrThumbCtx = ThumbCtx.get();
     ThumbRelInfo.reset(
         ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx));
     if (ThumbRelInfo) {
       ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer(
           ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
           &ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo)));
       ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer));
     }
     int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect();
-    ThumbIP.reset(ThumbTarget->createMCInstPrinter(
-        Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo,
-        *ThumbInstrInfo, *ThumbMRI));
+    ThumbInstrInfo.reset(ThumbMTM->createMCInstrInfo());
+    ThumbIP.reset(ThumbMTM->createMCInstPrinter(
+        ThumbAsmPrinterVariant, *ThumbAsmInfo, *ThumbInstrInfo, *ThumbMRI));
     // Set the display preference for hex vs. decimal immediates.
     ThumbIP->setPrintImmHex(PrintImmHex);
   }
 
   if (ThumbTarget && (!ThumbAsmInfo || !ThumbSTI || !ThumbDisAsm || !ThumbIP)) {
     errs() << "error: couldn't initialize disassembler for target "
            << ThumbTripleName << '\n';
     return;

tools/llvm-objdump/llvm-objdump.cpp

 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCRelocationInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/Archive.h"
 #include "llvm/Object/ELFObjectFile.h"
 #include "llvm/Object/COFF.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
   std::string FeaturesStr;
   if (MAttrs.size()) {
     SubtargetFeatures Features;
     for (unsigned i = 0; i != MAttrs.size(); ++i)
       Features.AddFeature(MAttrs[i]);
     FeaturesStr = Features.getString();
   }
 
-  std::unique_ptr<const MCRegisterInfo> MRI(
-      TheTarget->createMCRegInfo(TripleName));
+  Triple TT(TripleName);
+  std::unique_ptr<const MCTargetMachine> MTM(
+      TheTarget->createMCTargetMachine(TT));
+  if (!MTM) {
+    errs() << "error: no MC target machine for target " << TripleName << "\n";
+    return;
+  }
+
+  std::unique_ptr<const MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
   if (!MRI) {
     errs() << "error: no register info for target " << TripleName << "\n";
     return;
   }
 
   // Set up disassembler.
-  std::unique_ptr<const MCAsmInfo> AsmInfo(
-      TheTarget->createMCAsmInfo(*MRI, TripleName));
+  std::unique_ptr<const MCAsmInfo> AsmInfo(MTM->createMCAsmInfo(*MRI));
   if (!AsmInfo) {
     errs() << "error: no assembly info for target " << TripleName << "\n";
     return;
   }
 
   std::unique_ptr<const MCSubtargetInfo> STI(
-      TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
+      MTM->createMCSubtargetInfo(MCPU, FeaturesStr));
   if (!STI) {
     errs() << "error: no subtarget info for target " << TripleName << "\n";
     return;
   }
 
-  std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
+  std::unique_ptr<const MCInstrInfo> MII(MTM->createMCInstrInfo());
   if (!MII) {
     errs() << "error: no instruction info for target " << TripleName << "\n";
     return;
   }
 
   std::unique_ptr<const MCObjectFileInfo> MOFI(new MCObjectFileInfo);
   MCContext Ctx(AsmInfo.get(), MRI.get(), MOFI.get());
 
-  std::unique_ptr<MCDisassembler> DisAsm(
-    TheTarget->createMCDisassembler(*STI, Ctx));
+  std::unique_ptr<MCDisassembler> DisAsm(MTM->createMCDisassembler(*STI, Ctx));
 
   if (!DisAsm) {
     errs() << "error: no disassembler for target " << TripleName << "\n";
     return;
   }
 
   std::unique_ptr<const MCInstrAnalysis> MIA(
-      TheTarget->createMCInstrAnalysis(MII.get()));
+      MTM->createMCInstrAnalysis(MII.get()));
 
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
-  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI));
+  std::unique_ptr<MCInstPrinter> IP(
+      MTM->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI));
   if (!IP) {
     errs() << "error: no instruction printer for target " << TripleName
       << '\n';
     return;
   }
   IP->setPrintImmHex(PrintImmHex);
-  PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName));
+  PrettyPrinter &PIP = selectPrettyPrinter(TT);
 
   StringRef Fmt = Obj->getBytesInAddress() > 4 ? "\t\t%016" PRIx64 ":  " :
                                                  "\t\t\t%08" PRIx64 ":  ";
 
   // Create a mapping, RelocSecs = SectionRelocMap[S], where sections
   // in RelocSecs contain the relocations for section S.
   std::error_code EC;
   std::map<SectionRef, SmallVector<SectionRef, 1>> SectionRelocMap;

tools/llvm-rtdyld/llvm-rtdyld.cpp

 #include "llvm/ExecutionEngine/RuntimeDyldChecker.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/SymbolSize.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/DynamicLibrary.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Memory.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
const Target *TheTarget =
     TargetRegistry::lookupTarget("", TheTriple, ErrorStr);
   if (!TheTarget) {
     llvm::errs() << "Error accessing target '" << TripleName << "': "
                  << ErrorStr << "\n";
     return 1;
   }
   TripleName = TheTriple.getTriple();
 
-  std::unique_ptr<MCSubtargetInfo> STI(
-    TheTarget->createMCSubtargetInfo(TripleName, MCPU, ""));
+  std::unique_ptr<MCTargetMachine> MTM(TheTarget->createMCTargetMachine(TheTriple));
+  assert(MTM && "Unable to create MC target machine!");
+
+  std::unique_ptr<MCSubtargetInfo> STI(MTM->createMCSubtargetInfo(MCPU, ""));
   assert(STI && "Unable to create subtarget info!");
 
-  std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
+  std::unique_ptr<MCRegisterInfo> MRI(MTM->createMCRegisterInfo());
   assert(MRI && "Unable to create target register info!");
 
-  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  std::unique_ptr<MCAsmInfo> MAI(MTM->createMCAsmInfo(*MRI));
   assert(MAI && "Unable to create target asm info!");
 
   MCContext Ctx(MAI.get(), MRI.get(), nullptr);
 
+  std::unique_ptr<MCInstrInfo> MII(MTM->createMCInstrInfo());
+
   std::unique_ptr<MCDisassembler> Disassembler(
-    TheTarget->createMCDisassembler(*STI, Ctx));
+      MTM->createMCDisassembler(*STI, Ctx));
   assert(Disassembler && "Unable to create disassembler!");
 
-  std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
-
   std::unique_ptr<MCInstPrinter> InstPrinter(
-      TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI));
+      MTM->createMCInstPrinter(0, *MAI, *MII, *MRI));
 
   // Load any dylibs requested on the command line.
   loadDylibs();
 
   // Instantiate a dynamic linker.
   TrivialMemoryManager MemMgr;
   doPreallocation(MemMgr);
   RuntimeDyld Dyld(MemMgr, MemMgr);