Virtualize createMCAsmInfo and add MCTargetMachine subclasses.

[dsanders]

Summary

This allows each MCTargetMachine to pass different information to their
MCAsmInfo subclasses. Each target has been updated to do this.

It also removes the need for each target to register their MCAsmInfo
subclasses since registering MCTargetMachine accomplishes this.

Target-specific changes:

• Sparc: There were two create*MCAsmInfo() functions which were identical aside from one constant. These constructors have been merged together while preserving this difference.
• Mips: Areas where checking for 64-bit is incorrect have been marked with FIXME comments.

Depends on D13860

[dsanders]

ping

[dsanders]

ping

[dsanders]

Refresh patch.

[dsanders]

Correct bad 'arc diff' command

[dsanders]

Refresh patch correctly.

include/llvm/MC/MCTargetMachine.h

 
 public:
   MCTargetMachine(const Target &T, const Triple &TT);
   virtual ~MCTargetMachine() {}
 
   const Target &getTarget() const { return TheTarget; }
 
   /// Create a MCAsmInfo implementation.
-  virtual MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const;
+  virtual MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const = 0;
 
   /// Create a MCCodeGenInfo implementation.
   virtual MCCodeGenInfo *createMCCodeGenInfo(Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) const;
 
   /// Create a MCInstrInfo implementation.
   virtual MCInstrInfo *createMCInstrInfo() const;

include/llvm/Support/TargetRegistry.h

 /// part of their initialization.
 class Target {
 public:
   friend struct TargetRegistry;
   friend class MCTargetMachine;
 
   typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
-  typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
-                                          const Triple &TT);
   typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
                                                   CodeGenOpt::Level OL);
   typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
   typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
   typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
   typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
private:
   const char *Name;
 
   /// ShortDesc - A short description of the target.
   const char *ShortDesc;
 
   /// HasJIT - Whether this target supports the JIT.
   bool HasJIT;
 
-  /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
-  /// registered.
-  MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
-
   /// MCCodeGenInfoCtorFn - Constructor function for this target's
   /// MCCodeGenInfo, if registered.
   MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;
 
   /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
   /// if registered.
   MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
 
public:
   /// hasMCAsmBackend - Check if this target supports .o generation.
   bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
 
   /// @}
   /// @name Feature Constructors
   /// @{
 
 protected:
-  /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
-  /// target triple.
-  ///
-  /// \param TheTriple This argument is used to determine the target machine
-  /// feature set; it should always be provided. Generally this should be
-  /// either the target triple from the module, or the target triple of the
-  /// host if that does not exist.
-  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
-                             StringRef TheTriple) const {
-    if (!MCAsmInfoCtorFn)
-      return nullptr;
-    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
-  }
-
   /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
   ///
   MCCodeGenInfo *createMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                      CodeModel::Model CM,
                                      CodeGenOpt::Level OL) const {
     if (!MCCodeGenInfoCtorFn)
       return nullptr;
     return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL);
struct TargetRegistry {
   /// string.
   /// @param ArchMatchFn - The arch match checking function for this target.
   /// @param HasJIT - Whether the target supports JIT code
   /// generation.
   static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
                              Target::ArchMatchFnTy ArchMatchFn,
                              bool HasJIT = false);
 
-  /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
-  /// given target.
-  ///
-  /// Clients are responsible for ensuring that registration doesn't occur
-  /// while another thread is attempting to access the registry. Typically
-  /// this is done by initializing all targets at program startup.
-  ///
-  /// @param T - The target being registered.
-  /// @param Fn - A function to construct a MCAsmInfo for the target.
-  static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
-    T.MCAsmInfoCtorFn = Fn;
-  }
-
   /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the
   /// given target.
   ///
   /// Clients are responsible for ensuring that registration doesn't occur
   /// while another thread is attempting to access the registry. Typically
   /// this is done by initializing all targets at program startup.
   ///
   /// @param T - The target being registered.
RegisterTarget(Target &T, const char *Name, const char *Desc) {
     TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT);
   }
 
   static bool getArchMatch(Triple::ArchType Arch) {
     return Arch == TargetArchType;
   }
 };
 
-/// RegisterMCAsmInfo - Helper template for registering a target assembly info
-/// implementation.  This invokes the static "Create" method on the class to
-/// actually do the construction.  Usage:
-///
-/// extern "C" void LLVMInitializeFooTarget() {
-///   extern Target TheFooTarget;
-///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
-/// }
-template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
-  RegisterMCAsmInfo(Target &T) {
-    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
-  }
-
-private:
-  static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
-                              const Triple &TT) {
-    return new MCAsmInfoImpl(TT);
-  }
-};
-
-/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
-/// implementation.  This invokes the specified function to do the
-/// construction.  Usage:
-///
-/// extern "C" void LLVMInitializeFooTarget() {
-///   extern Target TheFooTarget;
-///   RegisterMCAsmInfoFn X(TheFooTarget, TheFunction);
-/// }
-struct RegisterMCAsmInfoFn {
-  RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
-    TargetRegistry::RegisterMCAsmInfo(T, Fn);
-  }
-};
-
 /// RegisterMCCodeGenInfo - Helper template for registering a target codegen
 /// info
 /// implementation.  This invokes the static "Create" method on the class
 /// to actually do the construction.  Usage:
 ///
 /// extern "C" void LLVMInitializeFooTarget() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);

lib/MC/MCTargetMachine.cpp

 
 #include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 MCTargetMachine::MCTargetMachine(const Target &T, const Triple &TT)
     : TheTarget(T), TheTriple(TT) {}
 
-MCAsmInfo *MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
-  return TheTarget.createMCAsmInfo(MRI, TheTriple.str());
-}
-
 MCCodeGenInfo *
 MCTargetMachine::createMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
                                      CodeGenOpt::Level OL) const {
   return TheTarget.createMCCodeGenInfo(TheTriple.str(), RM, CM, OL);
 }
 
 MCInstrInfo *MCTargetMachine::createMCInstrInfo() const {
   return TheTarget.createMCInstrInfo();

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h

 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCASMINFO_H
 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
 class MCStreamer;
-class Target;
-class Triple;
 
 struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin {
   explicit AArch64MCAsmInfoDarwin();
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
-  explicit AArch64MCAsmInfoELF(const Triple &T);
+  explicit AArch64MCAsmInfoELF(bool IsLittleEndian);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

 //===-- AArch64MCAsmInfo.cpp - AArch64 asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the AArch64MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
 enum AsmWriterVariantTy {
   Default = -1,
const MCExpr *AArch64MCAsmInfoDarwin::getExprForPersonalitySymbol(
   const MCExpr *Res =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOT, Context);
   MCSymbol *PCSym = Context.createTempSymbol();
   Streamer.EmitLabel(PCSym);
   const MCExpr *PC = MCSymbolRefExpr::create(PCSym, Context);
   return MCBinaryExpr::createSub(Res, PC, Context);
 }
 
-AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
-  if (T.getArch() == Triple::aarch64_be)
-    IsLittleEndian = false;
+AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(bool IsLittleEndian_) {
+  IsLittleEndian = IsLittleEndian_;
 
   // We prefer NEON instructions to be printed in the short form.
   AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant;
 
   PointerSize = 8;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides AArch64 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCTargetDesc.h"
 #include "AArch64ELFStreamer.h"
-#include "AArch64MCAsmInfo.h"
+#include "AArch64MCTargetMachine.h"
 #include "InstPrinter/AArch64InstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AArch64GenInstrInfo.inc"
 

 }
 
 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
   return X;
 }
 
-static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TheTriple) {
-  MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO())
-    MAI = new AArch64MCAsmInfoDarwin();
-  else {
-    assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
-    MAI = new AArch64MCAsmInfoELF(TheTriple);
-  }
-
-  // Initial state of the frame pointer is SP.
-  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
-  MAI->addInitialFrameState(Inst);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) &&
          "Only expect Darwin and ELF targets");
 
   if (CM == CodeModel::Default)
return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                              DWARFMustBeAtTheEnd,
                              /*LabelSections*/ true);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeAArch64TargetMC() {
   for (Target *T :
        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
+    RegisterMCTargetMachine<AArch64MCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
 
     // Register the MC register info.

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h

+//===-- AArch64MCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the AArch64 specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class AArch64MCTargetMachine : public MCTargetMachine {
+  AArch64MCTargetMachine(const AArch64MCTargetMachine &) = delete;
+  void operator=(const AArch64MCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+
+public:
+  AArch64MCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.cpp

+//===-- AArch64MCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "AArch64MCAsmInfo.h"
+#include "AArch64MCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for AArch64 registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "AArch64GenRegisterInfo.inc"
+
+AArch64MCTargetMachine::AArch64MCTargetMachine(const Target &T,
+                                               const Triple &TT)
+    : MCTargetMachine(T, TT),
+      IsLittleEndian(TT.getArch() != Triple::aarch64_be) {}
+
+MCAsmInfo *
+AArch64MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI;
+  if (TheTriple.isOSBinFormatMachO())
+    MAI = new AArch64MCAsmInfoDarwin();
+  else {
+    assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
+    MAI = new AArch64MCAsmInfoELF(IsLittleEndian);
+  }
+
+  // Initial state of the frame pointer is SP.
+  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
+  MAI->addInitialFrameState(Inst);
+
+  return MAI;
+}

lib/Target/AArch64/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMAArch64Desc
   AArch64AsmBackend.cpp
   AArch64ELFObjectWriter.cpp
   AArch64ELFStreamer.cpp
   AArch64MCAsmInfo.cpp
   AArch64MCCodeEmitter.cpp
   AArch64MCExpr.cpp
   AArch64MCTargetDesc.cpp
+  AArch64MCTargetMachine.cpp
   AArch64MachObjectWriter.cpp
   AArch64TargetStreamer.cpp
 )
 add_dependencies(LLVMAArch64Desc AArch64CommonTableGen)
 
 # Hack: we need to include 'main' target directory to grab private headers
 include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h

 /// \file
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
-namespace llvm {
-
-class Triple;
 
+namespace llvm {
 // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo,
 // you will need to make sure your new class sets PrivateGlobalPrefix to
 // a prefix that won't appear in a function name.  The default value
 // for PrivateGlobalPrefix is 'L', so it will consider any function starting
 // with 'L' as a local symbol.
 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit AMDGPUMCAsmInfo(const Triple &TT);
+  explicit AMDGPUMCAsmInfo();
   bool shouldOmitSectionDirective(StringRef SectionName) const override;
 };
 } // namespace llvm
 #endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

 //===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 /// \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCAsmInfo.h"
 
 using namespace llvm;
-AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
+AMDGPUMCAsmInfo::AMDGPUMCAsmInfo() : MCAsmInfoELF() {
   HasSingleParameterDotFile = false;
   //===------------------------------------------------------------------===//
   MaxInstLength = 16;
   SeparatorString = "\n";
   CommentString = ";";
   PrivateLabelPrefix = "";
   InlineAsmStart = ";#ASMSTART";
   InlineAsmEnd = ";#ASMEND";

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// \brief This file provides AMDGPU specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCTargetDesc.h"
 #include "AMDGPUELFStreamer.h"
-#include "AMDGPUMCAsmInfo.h"
 #include "AMDGPUTargetStreamer.h"
+#include "AMDGPUMCTargetMachine.h"
 #include "InstPrinter/AMDGPUInstPrinter.h"
 #include "SIDefines.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AMDGPUGenInstrInfo.inc"
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
   if (T.getOS() == Triple::AMDHSA)
     return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 
   return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 }
 
 extern "C" void LLVMInitializeAMDGPUTargetMC() {
   for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-    RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
+    RegisterMCTargetMachine<AMDGPUMCTargetMachine> Y(*T);
 
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.h

+//===-- AMDGPUMCTargetMachine.h - Define MCTargetMachine --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the AMDGPU specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class AMDGPUMCTargetMachine : public MCTargetMachine {
+  AMDGPUMCTargetMachine(const AMDGPUMCTargetMachine &) = delete;
+  void operator=(const AMDGPUMCTargetMachine &) = delete;
+
+public:
+  AMDGPUMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetMachine.cpp

+//===-- AMDGPUMCTargetMachine.cpp - Define MCTargetMachine ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUMCAsmInfo.h"
+#include "AMDGPUMCTargetMachine.h"
+
+using namespace llvm;
+
+AMDGPUMCTargetMachine::AMDGPUMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT) {}
+
+MCAsmInfo *
+AMDGPUMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return new AMDGPUMCAsmInfo();
+}

lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt

 
 add_llvm_library(LLVMAMDGPUDesc
   AMDGPUAsmBackend.cpp
   AMDGPUELFObjectWriter.cpp
   AMDGPUELFStreamer.cpp
   AMDGPUMCCodeEmitter.cpp
   AMDGPUMCTargetDesc.cpp
+  AMDGPUMCTargetMachine.cpp
   AMDGPUMCAsmInfo.cpp
   AMDGPUTargetStreamer.cpp
   R600MCCodeEmitter.cpp
   SIMCCodeEmitter.cpp
   )

lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h

 //===-- ARMMCAsmInfo.h - ARM asm properties --------------------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declaration of the ARMMCAsmInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
+  explicit ARMMCAsmInfoDarwin(bool IsLittleEndian_, Triple::OSType OS);
 };
 
 class ARMELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit ARMELFMCAsmInfo(const Triple &TT);
+  explicit ARMELFMCAsmInfo(bool IsLittleEndian_, Triple::OSType OS);
 
   void setUseIntegratedAssembler(bool Value) override;
 };
 
 class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:

lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

 //===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the ARMMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 void ARMMCAsmInfoDarwin::anchor() { }
 
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
-    IsLittleEndian = false;
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(bool IsLittleEndian_,
+                                       Triple::OSType OS) {
+  IsLittleEndian = IsLittleEndian_;
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
   UseDataRegionDirectives = true;
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  ExceptionsType = TheTriple.isWatchOS() ? ExceptionHandling::DwarfCFI
+  ExceptionsType = OS == Triple::WatchOS ? ExceptionHandling::DwarfCFI
                                          : ExceptionHandling::SjLj;
 
   UseIntegratedAssembler = true;
 }
 
 void ARMELFMCAsmInfo::anchor() { }
 
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
-    IsLittleEndian = false;
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(bool IsLittleEndian_, Triple::OSType OS) {
+  IsLittleEndian = IsLittleEndian_;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  switch (TheTriple.getOS()) {
+  switch (OS) {
   case Triple::Bitrig:
   case Triple::NetBSD:
     ExceptionsType = ExceptionHandling::DwarfCFI;
     break;
   default:
     ExceptionsType = ExceptionHandling::ARM;
     break;
   }

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides ARM specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMBaseInfo.h"
-#include "ARMMCAsmInfo.h"
 #include "ARMMCTargetDesc.h"
+#include "ARMMCTargetMachine.h"
 #include "InstPrinter/ARMInstPrinter.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_MC_DESC
 #include "ARMGenRegisterInfo.inc"

 }
 
 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
   return X;
 }
 
-static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
-    MAI = new ARMMCAsmInfoDarwin(TheTriple);
-  else if (TheTriple.isWindowsMSVCEnvironment())
-    MAI = new ARMCOFFMCAsmInfoMicrosoft();
-  else if (TheTriple.isOSWindows())
-    MAI = new ARMCOFFMCAsmInfoGNU();
-  else
-    MAI = new ARMELFMCAsmInfo(TheTriple);
-
-  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
-  MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
     RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
   }

 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
   return new ARMMCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeARMTargetMC() {
   for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
                     &TheThumbBETarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
+    RegisterMCTargetMachine<ARMMCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
 
     // Register the MC register info.

lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h

+//===-- ARMMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the ARM specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class ARMMCTargetMachine : public MCTargetMachine {
+  ARMMCTargetMachine(const ARMMCTargetMachine &) = delete;
+  void operator=(const ARMMCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+
+public:
+  ARMMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.cpp

+//===-- ARMMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARMMCAsmInfo.h"
+#include "ARMMCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for ARM registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
+ARMMCTargetMachine::ARMMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT),
+      IsLittleEndian(TheTriple.getArch() != Triple::armeb &&
+                     TheTriple.getArch() != Triple::thumbeb) {}
+
+MCAsmInfo *
+ARMMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI;
+  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
+    MAI = new ARMMCAsmInfoDarwin(IsLittleEndian, TheTriple.getOS());
+  else if (TheTriple.isWindowsMSVCEnvironment())
+    MAI = new ARMCOFFMCAsmInfoMicrosoft();
+  else if (TheTriple.isOSWindows())
+    MAI = new ARMCOFFMCAsmInfoGNU();
+  else
+    MAI = new ARMELFMCAsmInfo(IsLittleEndian, TheTriple.getOS());
+
+  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
+  MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
+
+  return MAI;
+}

lib/Target/ARM/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMARMDesc
   ARMAsmBackend.cpp
   ARMELFObjectWriter.cpp
   ARMELFObjectWriter.cpp
   ARMELFStreamer.cpp
   ARMMachObjectWriter.cpp
   ARMMachORelocationInfo.cpp
   ARMMCAsmInfo.cpp
   ARMMCCodeEmitter.cpp
   ARMMCExpr.cpp
   ARMMCTargetDesc.cpp
+  ARMMCTargetMachine.cpp
   ARMTargetStreamer.cpp
   ARMUnwindOpAsm.cpp
   ARMWinCOFFObjectWriter.cpp
   ARMWinCOFFStreamer.cpp
   )

lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h

 //===-- BPFMCAsmInfo.h - BPF asm properties -------------------*- C++ -*--====//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declaration of the BPFMCAsmInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 
-#include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 
 namespace llvm {
 class Target;
-class Triple;
 
 class BPFMCAsmInfo : public MCAsmInfo {
 public:
-  explicit BPFMCAsmInfo(const Triple &TT) {
-    if (TT.getArch() == Triple::bpfeb)
-      IsLittleEndian = false;
+  explicit BPFMCAsmInfo(bool IsLittleEndian_) {
+    IsLittleEndian = IsLittleEndian_;
 
     PrivateGlobalPrefix = ".L";
     WeakRefDirective = "\t.weak\t";
 
     UsesELFSectionDirectiveForBSS = true;
     HasSingleParameterDotFile = false;
     HasDotTypeDotSizeDirective = false;
 
     SupportsDebugInformation = true;
   }
 };
 }
 
 #endif

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

 //===-- BPFMCTargetDesc.cpp - BPF Target Descriptions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides BPF specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "BPF.h"
 #include "BPFMCTargetDesc.h"
-#include "BPFMCAsmInfo.h"
+#include "BPFMCTargetMachine.h"
 #include "InstPrinter/BPFInstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC
 #include "BPFGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "BPFGenSubtargetInfo.inc"
static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new BPFInstPrinter(MAI, MII, MRI);
   return 0;
 }
 
 extern "C" void LLVMInitializeBPFTargetMC() {
   for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
+    RegisterMCTargetMachine<BPFMCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);
 
     // Register the MC register info.

lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h

+//===-- BPFMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the BPF specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class BPFMCTargetMachine : public MCTargetMachine {
+  BPFMCTargetMachine(const BPFMCTargetMachine &) = delete;
+  void operator=(const BPFMCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+
+public:
+  BPFMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.cpp

+//===-- BPFMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "BPFMCAsmInfo.h"
+#include "BPFMCTargetMachine.h"
+
+using namespace llvm;
+
+BPFMCTargetMachine::BPFMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT), IsLittleEndian(TT.getArch() != Triple::bpfeb) {}
+
+MCAsmInfo *
+BPFMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return new BPFMCAsmInfo(IsLittleEndian);
+}

lib/Target/BPF/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMBPFDesc
   BPFMCTargetDesc.cpp
+  BPFMCTargetMachine.cpp
   BPFAsmBackend.cpp
   BPFMCCodeEmitter.cpp
   BPFELFObjectWriter.cpp
   )

lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMHexagonDesc
   HexagonAsmBackend.cpp
   HexagonELFObjectWriter.cpp
   HexagonInstPrinter.cpp
   HexagonMCAsmInfo.cpp
   HexagonMCChecker.cpp
   HexagonMCCodeEmitter.cpp
   HexagonMCCompound.cpp
   HexagonMCDuplexInfo.cpp
   HexagonMCELFStreamer.cpp
   HexagonMCExpr.cpp
   HexagonMCInstrInfo.cpp
   HexagonMCShuffler.cpp
   HexagonMCTargetDesc.cpp
+  HexagonMCTargetMachine.cpp
   HexagonShuffler.cpp
   )
 
 add_dependencies(LLVMHexagonDesc HexagonCommonTableGen)

lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h

 //===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declaration of the HexagonMCAsmInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 
-#include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class HexagonMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit HexagonMCAsmInfo(const Triple &TT);
+  explicit HexagonMCAsmInfo();
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

 
 #include "HexagonMCAsmInfo.h"
 
 using namespace llvm;
 
 // Pin the vtable to this file.
 void HexagonMCAsmInfo::anchor() {}
 
-HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
+HexagonMCAsmInfo::HexagonMCAsmInfo() {
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   Data64bitsDirective = nullptr;  // .xword is only supported by V9.
   ZeroDirective = "\t.skip\t";
   CommentString = "//";
 
   LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;
   InlineAsmStart = "# InlineAsm Start";
   InlineAsmEnd = "# InlineAsm End";
   ZeroDirective = "\t.space\t";
   AscizDirective = "\t.string\t";
 
   SupportsDebugInformation = true;
   UsesELFSectionDirectiveForBSS  = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 }

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides Hexagon specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "HexagonMCTargetDesc.h"
 #include "Hexagon.h"
-#include "HexagonMCAsmInfo.h"
 #include "HexagonMCELFStreamer.h"
+#include "HexagonMCTargetMachine.h"
 #include "MCTargetDesc/HexagonInstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
     HexagonMCELFStreamer &HexagonELFStreamer =
         static_cast<HexagonMCELFStreamer &>(getStreamer());
     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
         Symbol, Size, ByteAlignment, AccessSize);
   }
 };
 }
 
-static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
-
-  // VirtualFP = (R30 + #0).
-  MCCFIInstruction Inst =
-      MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
-  MAI->addInitialFrameState(Inst);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   // For the time being, use static relocations, since there's really no
   // support for PIC yet.
   X->initMCCodeGenInfo(Reloc::Static, CM, OL);

 
 static MCTargetStreamer *
 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
   return new HexagonTargetELFStreamer(S, STI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeHexagonTargetMC() {
-  RegisterMCTargetMachine<MCTargetMachine> Y(TheHexagonTarget);
-
-  // Register the MC asm info.
-  RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
+  RegisterMCTargetMachine<HexagonMCTargetMachine> Y(TheHexagonTarget);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
                                         createHexagonMCCodeGenInfo);
 
   // Register the MC instruction info.
   TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
                                       createHexagonMCInstrInfo);

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.h

+//===-- HexagonMCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Hexagon specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class HexagonMCTargetMachine : public MCTargetMachine {
+  HexagonMCTargetMachine(const HexagonMCTargetMachine &) = delete;
+  void operator=(const HexagonMCTargetMachine &) = delete;
+
+public:
+  HexagonMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetMachine.cpp

+//===-- HexagonMCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "HexagonMCAsmInfo.h"
+#include "HexagonMCTargetMachine.h"
+
+using namespace llvm;
+
+// Defines symbolic names for Hexagon registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "HexagonGenRegisterInfo.inc"
+
+HexagonMCTargetMachine::HexagonMCTargetMachine(const Target &T,
+                                               const Triple &TT)
+    : MCTargetMachine(T, TT) {}
+
+MCAsmInfo *
+HexagonMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI = new HexagonMCAsmInfo();
+
+  // VirtualFP = (R30 + #0).
+  MCCFIInstruction Inst =
+      MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
+  MAI->addInitialFrameState(Inst);
+
+  return MAI;
+}

lib/Target/MSP430/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMMSP430Desc
   MSP430MCTargetDesc.cpp
+  MSP430MCTargetMachine.cpp
   MSP430MCAsmInfo.cpp
   )

lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class MSP430MCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MSP430MCAsmInfo(const Triple &TT);
+  explicit MSP430MCAsmInfo();
 };
 
 } // namespace llvm
 
 #endif

lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MCAsmInfo.h"
 using namespace llvm;
 
 void MSP430MCAsmInfo::anchor() { }
 
-MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
+MSP430MCAsmInfo::MSP430MCAsmInfo() {
   PointerSize = CalleeSaveStackSlotSize = 2;
 
   CommentString = ";";
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
 }

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

 //===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides MSP430 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MCTargetDesc.h"
 #include "InstPrinter/MSP430InstPrinter.h"
-#include "MSP430MCAsmInfo.h"
+#include "MSP430MCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "MSP430GenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new MSP430InstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 extern "C" void LLVMInitializeMSP430TargetMC() {
-  RegisterMCTargetMachine<MCTargetMachine> Y(TheMSP430Target);
-
-  // Register the MC asm info.
-  RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
+  RegisterMCTargetMachine<MSP430MCTargetMachine> Y(TheMSP430Target);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target,
                                         createMSP430MCCodeGenInfo);
 
   // Register the MC instruction info.
   TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
 

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.h

+//===-- MSP430MCTargetMachine.h - Define MCTargetMachine --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the MSP430 specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_MSP430_MSP430MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_MSP430_MSP430MCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class MSP430MCTargetMachine : public MCTargetMachine {
+  MSP430MCTargetMachine(const MSP430MCTargetMachine &) = delete;
+  void operator=(const MSP430MCTargetMachine &) = delete;
+
+public:
+  MSP430MCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetMachine.cpp

-//===-- MSP430MCAsmInfo.cpp - MSP430 asm properties -----------------------===//
+//===-- MSP430MCTargetMachine.cpp - Define MCTargetMachine ------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the declarations of the MSP430MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MCAsmInfo.h"
-using namespace llvm;
-
-void MSP430MCAsmInfo::anchor() { }
+#include "MSP430MCTargetMachine.h"
 
-MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
-  PointerSize = CalleeSaveStackSlotSize = 2;
+using namespace llvm;
 
-  CommentString = ";";
+MSP430MCTargetMachine::MSP430MCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT) {}
 
-  AlignmentIsInBytes = false;
-  UsesELFSectionDirectiveForBSS = true;
+MCAsmInfo *
+MSP430MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return new MSP430MCAsmInfo();
 }

lib/Target/Mips/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMMipsDesc
   MipsABIInfo.cpp
   MipsABIFlagsSection.cpp
   MipsAsmBackend.cpp
   MipsELFObjectWriter.cpp
   MipsELFStreamer.cpp
   MipsMCAsmInfo.cpp
   MipsMCCodeEmitter.cpp
   MipsMCExpr.cpp
   MipsMCTargetDesc.cpp
+  MipsMCTargetMachine.cpp
   MipsNaClELFStreamer.cpp
   MipsOptionRecord.cpp
   MipsTargetStreamer.cpp
   )

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class MipsMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MipsMCAsmInfo(const Triple &TheTriple);
+  explicit MipsMCAsmInfo(bool IsLittleEndian_, bool IsArch64Bit);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

 //===-- MipsMCAsmInfo.cpp - Mips Asm Properties ---------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MipsMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 
 using namespace llvm;
 
 void MipsMCAsmInfo::anchor() { }
 
-MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::mips) ||
-      (TheTriple.getArch() == Triple::mips64))
-    IsLittleEndian = false;
-
-  if ((TheTriple.getArch() == Triple::mips64el) ||
-      (TheTriple.getArch() == Triple::mips64)) {
-    PointerSize = CalleeSaveStackSlotSize = 8;
-  }
+MipsMCAsmInfo::MipsMCAsmInfo(bool IsLittleEndian_, bool IsArch64Bit) {
+  IsLittleEndian = IsLittleEndian_;
+
+  // FIXME: This should use MipsABIInfo::ArePtrs64bit().
+  if (IsArch64Bit)
+    PointerSize = 8;
+
+  // FIXME: This should use MipsABIInfo::AreGprs64bit().
+  if (IsArch64Bit)
+    CalleeSaveStackSlotSize = 8;
 
   AlignmentIsInBytes          = false;
   Data16bitsDirective         = "\t.2byte\t";
   Data32bitsDirective         = "\t.4byte\t";
   Data64bitsDirective         = "\t.8byte\t";
   PrivateGlobalPrefix         = "$";
   PrivateLabelPrefix          = "$";
   CommentString               = "#";
   ZeroDirective               = "\t.space\t";
   GPRel32Directive            = "\t.gpword\t";
   GPRel64Directive            = "\t.gpdword\t";
   UseAssignmentForEHBegin = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   DwarfRegNumForCFI = true;
 }

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides Mips specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "InstPrinter/MipsInstPrinter.h"
 #include "MipsELFStreamer.h"
-#include "MipsMCAsmInfo.h"
 #include "MipsMCNaCl.h"
 #include "MipsMCTargetDesc.h"
+#include "MipsMCTargetMachine.h"
 #include "MipsTargetStreamer.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;

 }
 
 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
-                                      const Triple &TT) {
-  MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
-
-  unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
-  MAI->addInitialFrameState(Inst);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                               CodeModel::Model CM,
                                               CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (CM == CodeModel::JITDefault)
     RM = Reloc::Static;
   else if (RM == Reloc::Default)
     RM = Reloc::PIC_;

 static MCTargetStreamer *
 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
   return new MipsTargetELFStreamer(S, STI);
 }
 
 extern "C" void LLVMInitializeMipsTargetMC() {
   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
                     &TheMips64elTarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
+    RegisterMCTargetMachine<MipsMCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
 
     // Register the MC register info.

lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h

+//===-- MipsMCTargetMachine.h - Define MCTargetMachine ----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Mips specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class MipsMCTargetMachine : public MCTargetMachine {
+  MipsMCTargetMachine(const MipsMCTargetMachine &) = delete;
+  void operator=(const MipsMCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+  bool IsArch64Bit;
+
+public:
+  MipsMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.cpp

+//===-- MipsMCTargetMachine.cpp - Define MCTargetMachine --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "MipsMCAsmInfo.h"
+#include "MipsMCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for Mips registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "MipsGenRegisterInfo.inc"
+
+MipsMCTargetMachine::MipsMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT), IsLittleEndian(TT.getArch() != Triple::mips &&
+                                             TT.getArch() != Triple::mips64),
+      // FIXME: This is incorrect but it preserves existing behaviour for now.
+      //        We want to use the ABI instead but we must have clang pass an
+      //        initialized MCTargetOptions first.
+      IsArch64Bit(TT.getArch() == Triple::mips64 ||
+                  TT.getArch() == Triple::mips64el) {}
+
+MCAsmInfo *
+MipsMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI = new MipsMCAsmInfo(IsLittleEndian, IsArch64Bit);
+
+  unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
+  MAI->addInitialFrameState(Inst);
+
+  return MAI;
+}

lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMNVPTXDesc
   NVPTXMCAsmInfo.cpp
   NVPTXMCTargetDesc.cpp
+  NVPTXMCTargetMachine.cpp
   )

lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 #define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
-class Target;
-class Triple;
-
 class NVPTXMCAsmInfo : public MCAsmInfo {
   virtual void anchor();
 
 public:
-  explicit NVPTXMCAsmInfo(const Triple &TheTriple);
+  explicit NVPTXMCAsmInfo(bool IsArch64Bit);
 };
 } // namespace llvm
 
 #endif

lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp

 //===-- NVPTXMCAsmInfo.cpp - NVPTX asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the NVPTXMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 // -debug-compile - Command line option to inform opt and llc passes to
 // compile for debugging
 static cl::opt<bool> CompileForDebugging("debug-compile",
                                          cl::desc("Compile for debugging"),
                                          cl::Hidden, cl::init(false));
 
 void NVPTXMCAsmInfo::anchor() {}
 
-NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) {
-  if (TheTriple.getArch() == Triple::nvptx64) {
+NVPTXMCAsmInfo::NVPTXMCAsmInfo(bool IsArch64Bit) {
+  if (IsArch64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
-  }
 
   CommentString = "//";
 
   HasSingleParameterDotFile = false;
 
   InlineAsmStart = " inline asm";
   InlineAsmEnd = " inline asm";
 

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

 //===-- NVPTXMCTargetDesc.cpp - NVPTX Target Descriptions -------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides NVPTX specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCTargetDesc.h"
 #include "InstPrinter/NVPTXInstPrinter.h"
-#include "NVPTXMCAsmInfo.h"
+#include "NVPTXMCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "NVPTXGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
   if (SyntaxVariant == 0)
     return new NVPTXInstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeNVPTXTargetMC() {
   for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
+    RegisterMCTargetMachine<NVPTXMCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);
 
     // Register the MC register info.

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h

+//===-- NVPTXMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the NVPTX specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_NVPTX_NVPTXMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class NVPTXMCTargetMachine : public MCTargetMachine {
+  NVPTXMCTargetMachine(const NVPTXMCTargetMachine &) = delete;
+  void operator=(const NVPTXMCTargetMachine &) = delete;
+
+  bool IsArch64Bit;
+
+public:
+  NVPTXMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.cpp

+//===-- NVPTXMCTargetMachine.cpp - Define MCTargetMachine -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "NVPTXMCAsmInfo.h"
+#include "NVPTXMCTargetMachine.h"
+
+using namespace llvm;
+
+NVPTXMCTargetMachine::NVPTXMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT), IsArch64Bit(TT.getArch() == Triple::nvptx64) {}
+
+MCAsmInfo *
+NVPTXMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return new NVPTXMCAsmInfo(IsArch64Bit);
+}

lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMPowerPCDesc
   PPCAsmBackend.cpp
   PPCMCTargetDesc.cpp
+  PPCMCTargetMachine.cpp
   PPCMCAsmInfo.cpp
   PPCMCCodeEmitter.cpp
   PPCMCExpr.cpp
   PPCPredicates.cpp
   PPCMachObjectWriter.cpp
   PPCELFObjectWriter.cpp
   )

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &);
+  explicit PPCMCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6);
 };
 
 class PPCELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &);
+  explicit PPCELFMCAsmInfo(bool Is64Bit, bool IsLittleEndian_);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

 //===-- PPCMCAsmInfo.cpp - PPC asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MCAsmInfoDarwin properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 
 using namespace llvm;
 
 void PPCMCAsmInfoDarwin::anchor() { }
 
-PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
-  if (is64Bit) {
+PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool Is64Bit,
+                                       bool IsMacOSXVersionLt10_6) {
+  if (Is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
-  }
   IsLittleEndian = false;
 
   CommentString = ";";
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
-  if (!is64Bit)
+  if (!Is64Bit)
     Data64bitsDirective = nullptr; // We can't emit a 64-bit unit in PPC32 mode.
 
   AssemblerDialect = 1;           // New-Style mnemonics.
   SupportsDebugInformation= true; // Debug information.
 
-  // The installed assembler for OSX < 10.6 lacks some directives.
-  // FIXME: this should really be a check on the assembler characteristics
-  // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (IsMacOSXVersionLt10_6)
     HasWeakDefCanBeHiddenDirective = false;
 
   UseIntegratedAssembler = true;
 }
 
 void PPCELFMCAsmInfo::anchor() { }
 
-PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) {
+PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool Is64Bit, bool IsLittleEndian_) {
   // FIXME: This is not always needed. For example, it is not needed in the
   // v2 abi.
   NeedsLocalForSize = true;
 
-  if (is64Bit) {
+  if (Is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
-  }
-  IsLittleEndian = T.getArch() == Triple::ppc64le;
+  IsLittleEndian = IsLittleEndian_;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   CommentString = "#";
 
   // Uses '.section' before '.bss' directive
   UsesELFSectionDirectiveForBSS = true;  
 
   // Debug Information
   SupportsDebugInformation = true;
 
   DollarIsPC = true;
 
   // Set up DWARF directives
   MinInstAlignment = 4;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
     
   ZeroDirective = "\t.space\t";
-  Data64bitsDirective = is64Bit ? "\t.quad\t" : nullptr;
+  Data64bitsDirective = Is64Bit ? "\t.quad\t" : nullptr;
   AssemblerDialect = 1;           // New-Style mnemonics.
   LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;
 
   UseIntegratedAssembler = true;
 }
 

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

 //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides PowerPC specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCTargetDesc.h"
 #include "InstPrinter/PPCInstPrinter.h"
-#include "PPCMCAsmInfo.h"
+#include "PPCMCTargetMachine.h"
 #include "PPCTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCSymbolELF.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
   return X;
 }
 
 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
-                  TheTriple.getArch() == Triple::ppc64le);
-
-  MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin())
-    MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
-  else
-    MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
-
-  // Initial state of the frame pointer is R1.
-  unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
-  MCCFIInstruction Inst =
-      MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
-  MAI->addInitialFrameState(Inst);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   if (RM == Reloc::Default) {
     if (TT.isOSDarwin())
       RM = Reloc::DynamicNoPIC;
static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
 }
 
 extern "C" void LLVMInitializePowerPCTargetMC() {
   for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
+    RegisterMCTargetMachine<PPCMCTargetMachine> Y(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);
 
     // Register the MC register info.

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h

+//===-- PPCMCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the PowerPC specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_POWERPC_PPCMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_POWERPC_PPCMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class PPCMCTargetMachine : public MCTargetMachine {
+  PPCMCTargetMachine(const PPCMCTargetMachine &) = delete;
+  void operator=(const PPCMCTargetMachine &) = delete;
+
+  bool IsPPC64;
+  bool IsLittleEndian;
+
+public:
+  PPCMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.cpp

+//===-- PPCMCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCMCAsmInfo.h"
+#include "PPCMCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for PowerPC registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "PPCGenRegisterInfo.inc"
+
+PPCMCTargetMachine::PPCMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT),
+      IsPPC64(TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le),
+      IsLittleEndian(TT.getArch() == Triple::ppc64le) {}
+
+MCAsmInfo *
+PPCMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI;
+  if (TheTriple.isOSDarwin()) {
+    // The installed assembler for OSX < 10.6 lacks some directives.
+    // FIXME: this should really be a check on the assembler characteristics
+    // rather than OS version
+    MAI = new PPCMCAsmInfoDarwin(
+        IsPPC64, TheTriple.isMacOSX() && TheTriple.isMacOSXVersionLT(10, 6));
+  } else
+    MAI = new PPCELFMCAsmInfo(IsPPC64, IsLittleEndian);
+
+  // Initial state of the frame pointer is R1.
+  unsigned Reg = IsPPC64 ? PPC::X1 : PPC::R1;
+  MCCFIInstruction Inst =
+      MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
+  MAI->addInitialFrameState(Inst);
+
+  return MAI;
+}

lib/Target/Sparc/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMSparcDesc
   SparcAsmBackend.cpp
   SparcELFObjectWriter.cpp
   SparcMCAsmInfo.cpp
   SparcMCCodeEmitter.cpp
   SparcMCTargetDesc.cpp
+  SparcMCTargetMachine.cpp
   SparcMCExpr.cpp
   SparcTargetStreamer.cpp
   )

lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class SparcELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit SparcELFMCAsmInfo(const Triple &TheTriple);
+  explicit SparcELFMCAsmInfo(bool IsV9, bool IsLittleEndian_);
   const MCExpr*
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
   const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
                                     unsigned Encoding,
                                     MCStreamer &Streamer) const override;
 
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp

 //===-- SparcMCAsmInfo.cpp - Sparc asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the SparcMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMCAsmInfo.h"
 #include "SparcMCExpr.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCStreamer.h"
 
 using namespace llvm;
 
 void SparcELFMCAsmInfo::anchor() {}
 
-SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) {
-  bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
-  IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
+SparcELFMCAsmInfo::SparcELFMCAsmInfo(bool IsV9, bool IsLittleEndian_) {
+  IsLittleEndian = IsLittleEndian_;
 
-  if (isV9) {
+  if (IsV9)
     PointerSize = CalleeSaveStackSlotSize = 8;
-  }
 
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   // .xword is only supported by V9.
-  Data64bitsDirective = (isV9) ? "\t.xword\t" : nullptr;
+  Data64bitsDirective = IsV9 ? "\t.xword\t" : nullptr;
   ZeroDirective = "\t.skip\t";
   CommentString = "!";
   SupportsDebugInformation = true;
 
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   SunStyleELFSectionSwitchSyntax = true;
   UsesELFSectionDirectiveForBSS = true;

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

 //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides Sparc specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMCTargetDesc.h"
 #include "InstPrinter/SparcInstPrinter.h"
-#include "SparcMCAsmInfo.h"
+#include "SparcMCTargetMachine.h"
 #include "SparcTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SparcGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "SparcGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "SparcGenRegisterInfo.inc"
 
-static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
-  MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
-  unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
-  MAI->addInitialFrameState(Inst);
-  return MAI;
-}
-
-static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
-  unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
-  MAI->addInitialFrameState(Inst);
-  return MAI;
-}
-
 static MCInstrInfo *createSparcMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitSparcMCInstrInfo(X);
   return X;
 }
 
 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI) {
   return new SparcInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSparcTargetMC() {
-  // Register the MC asm info.
-  RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo);
-  RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo);
-  RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo);
-
   for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
+    RegisterMCTargetMachine<SparcMCTargetMachine> Y(*T);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
 
     // Register the MC register info.
     TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
 
     // Register the MC subtarget info.

lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h

+//===-- SparcMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Sparc specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class SparcMCTargetMachine : public MCTargetMachine {
+  SparcMCTargetMachine(const SparcMCTargetMachine &) = delete;
+  void operator=(const SparcMCTargetMachine &) = delete;
+
+  bool IsV9;
+  bool IsLittleEndian;
+
+public:
+  SparcMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.cpp

+//===-- SparcMCTargetMachine.cpp - Define MCTargetMachine -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "SparcMCAsmInfo.h"
+#include "SparcMCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for Sparc registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "SparcGenRegisterInfo.inc"
+
+SparcMCTargetMachine::SparcMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT), IsV9(TT.getArch() == Triple::sparcv9),
+      IsLittleEndian(TheTriple.getArch() == Triple::sparcel) {}
+
+MCAsmInfo *
+SparcMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI = new SparcELFMCAsmInfo(IsV9, IsLittleEndian);
+  unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
+  MCCFIInstruction Inst =
+      MCCFIInstruction::createDefCfa(nullptr, Reg, IsV9 ? 2047 : 0);
+  MAI->addInitialFrameState(Inst);
+  return MAI;
+}

lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMSystemZDesc
   SystemZMCAsmBackend.cpp
   SystemZMCAsmInfo.cpp
   SystemZMCCodeEmitter.cpp
   SystemZMCObjectWriter.cpp
   SystemZMCTargetDesc.cpp
+  SystemZMCTargetMachine.cpp
   )

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h

 //====-- SystemZMCAsmInfo.h - SystemZ asm properties -----------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
-#include "llvm/Support/Compiler.h"
 
 namespace llvm {
-class Triple;
-
 class SystemZMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit SystemZMCAsmInfo(const Triple &TT);
+  explicit SystemZMCAsmInfo();
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp

 //===-- SystemZMCAsmInfo.cpp - SystemZ asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 
 using namespace llvm;
 
-SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
+SystemZMCAsmInfo::SystemZMCAsmInfo() {
   PointerSize = 8;
   CalleeSaveStackSlotSize = 8;
   IsLittleEndian = false;
 
   CommentString = "#";
   ZeroDirective = "\t.space\t";
   Data64bitsDirective = "\t.quad\t";
   UsesELFSectionDirectiveForBSS = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   UseIntegratedAssembler = true;
 }

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMCTargetDesc.h"
 #include "InstPrinter/SystemZInstPrinter.h"
-#include "SystemZMCAsmInfo.h"
+#include "SystemZMCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SystemZGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
for (unsigned I = 0; I < 32; ++I) {
       Map[VR64Regs[I]] = I;
       Map[VR128Regs[I]] = I;
     }
   }
   assert(Reg < SystemZ::NUM_TARGET_REGS);
   return Map[Reg];
 }
 
-static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
-  MCCFIInstruction Inst =
-      MCCFIInstruction::createDefCfa(nullptr,
-                                     MRI.getDwarfRegNum(SystemZ::R15D, true),
-                                     SystemZMC::CFAOffsetFromInitialSP);
-  MAI->addInitialFrameState(Inst);
-  return MAI;
-}
-
 static MCInstrInfo *createSystemZMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitSystemZMCInstrInfo(X);
   return X;
 }
 
 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   return new SystemZInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSystemZTargetMC() {
-  RegisterMCTargetMachine<MCTargetMachine> Y(TheSystemZTarget);
-
-  // Register the MCAsmInfo.
-  TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget,
-                                    createSystemZMCAsmInfo);
+  RegisterMCTargetMachine<SystemZMCTargetMachine> Y(TheSystemZTarget);
 
   // Register the MCCodeGenInfo.
   TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
                                         createSystemZMCCodeGenInfo);
 
   // Register the MCCodeEmitter.
   TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget,
                                         createSystemZMCCodeEmitter);

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.h

+//===-- SystemZMCTargetMachine.h - Define MCTargetMachine -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the SystemZ specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class SystemZMCTargetMachine : public MCTargetMachine {
+  SystemZMCTargetMachine(const SystemZMCTargetMachine &) = delete;
+  void operator=(const SystemZMCTargetMachine &) = delete;
+
+public:
+  SystemZMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetMachine.cpp

+//===-- SystemZMCTargetMachine.cpp - Define MCTargetMachine -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "SystemZMCAsmInfo.h"
+#include "SystemZMCTargetDesc.h"
+#include "SystemZMCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+SystemZMCTargetMachine::SystemZMCTargetMachine(const Target &T,
+                                               const Triple &TT)
+    : MCTargetMachine(T, TT) {}
+
+MCAsmInfo *
+SystemZMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI = new SystemZMCAsmInfo();
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
+      nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true),
+      SystemZMC::CFAOffsetFromInitialSP);
+  MAI->addInitialFrameState(Inst);
+  return MAI;
+}

lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMWebAssemblyDesc
   WebAssemblyMCAsmInfo.cpp
   WebAssemblyMCTargetDesc.cpp
+  WebAssemblyMCTargetMachine.cpp
 )

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCASMINFO_H
 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
-
-class Triple;
-
 class WebAssemblyMCAsmInfo final : public MCAsmInfo {
 public:
-  explicit WebAssemblyMCAsmInfo(const Triple &T);
+  explicit WebAssemblyMCAsmInfo(bool IsArch64Bit);
   ~WebAssemblyMCAsmInfo() override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp

 //===-- WebAssemblyMCAsmInfo.cpp - WebAssembly asm properties -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief This file contains the declarations of the WebAssemblyMCAsmInfo
 /// properties.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-asm-info"
 
 WebAssemblyMCAsmInfo::~WebAssemblyMCAsmInfo() {}
 
-WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T) {
-  PointerSize = CalleeSaveStackSlotSize = T.isArch64Bit() ? 8 : 4;
+WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(bool IsArch64Bit) {
+  PointerSize = CalleeSaveStackSlotSize = IsArch64Bit ? 8 : 4;
 
   // TODO: What should MaxInstLength be?
 
   PrivateGlobalPrefix = "";
   PrivateLabelPrefix = "";
 
   UseDataRegionDirectives = true;
 

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

 //===-- WebAssemblyMCTargetDesc.cpp - WebAssembly Target Descriptions -----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief This file provides WebAssembly-specific target descriptions.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyMCTargetDesc.h"
 #include "InstPrinter/WebAssemblyInstPrinter.h"
-#include "WebAssemblyMCAsmInfo.h"
+#include "WebAssemblyMCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-target-desc"
 
 #define GET_INSTRINFO_MC_DESC
 #include "WebAssemblyGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "WebAssemblyGenRegisterInfo.inc"
 
-static MCAsmInfo *createWebAssemblyMCAsmInfo(const MCRegisterInfo &MRI,
-                                             const Triple &TT) {
-  return new WebAssemblyMCAsmInfo(TT);
-}
-
 static MCInstrInfo *createWebAssemblyMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitWebAssemblyMCInstrInfo(X);
   return X;
 }
 
 static MCInstPrinter *
 createWebAssemblyMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
                                const MCAsmInfo &MAI, const MCInstrInfo &MII,
                                const MCRegisterInfo &MRI) {
   assert(SyntaxVariant == 0);
   return new WebAssemblyInstPrinter(MAI, MII, MRI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeWebAssemblyTargetMC() {
   for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) {
-    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo);
+    RegisterMCTargetMachine<WebAssemblyMCTargetMachine> Y(*T);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createWebAssemblyMCInstrInfo);
 
     // Register the MCInstPrinter.
     TargetRegistry::RegisterMCInstPrinter(*T, createWebAssemblyMCInstPrinter);
   }
 }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h

+//===-- WebAssemblyMCTargetMachine.h - Define MCTargetMachine ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the WebAssembly specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class WebAssemblyMCTargetMachine : public MCTargetMachine {
+  WebAssemblyMCTargetMachine(const WebAssemblyMCTargetMachine &) = delete;
+  void operator=(const WebAssemblyMCTargetMachine &) = delete;
+
+  bool IsArch64Bit;
+
+public:
+  WebAssemblyMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.cpp

+//===-- WebAssemblyMCTargetMachine.cpp - Define MCTargetMachine -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "WebAssemblyMCAsmInfo.h"
+#include "WebAssemblyMCTargetMachine.h"
+
+using namespace llvm;
+
+WebAssemblyMCTargetMachine::WebAssemblyMCTargetMachine(const Target &T,
+                                                       const Triple &TT)
+    : MCTargetMachine(T, TT), IsArch64Bit(TT.isArch64Bit()) {}
+
+MCAsmInfo *
+WebAssemblyMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  return new WebAssemblyMCAsmInfo(IsArch64Bit);
+}

lib/Target/X86/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMX86Desc
   X86AsmBackend.cpp
   X86MCTargetDesc.cpp
+  X86MCTargetMachine.cpp
   X86MCAsmInfo.cpp
   X86MCCodeEmitter.cpp
   X86MachObjectWriter.cpp
   X86ELFObjectWriter.cpp
   X86WinCOFFStreamer.cpp
   X86WinCOFFObjectWriter.cpp
   X86MachORelocationInfo.cpp
   X86ELFRelocationInfo.cpp
   )

lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h

 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class X86MCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit X86MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86MCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6);
 };
 
 struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin {
-  explicit X86_64MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86_64MCAsmInfoDarwin(bool Is64Bit, bool IsMacOSXVersionLt10_6);
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 class X86ELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit X86ELFMCAsmInfo(const Triple &Triple);
+  explicit X86ELFMCAsmInfo(bool Is64Bit, bool IsX32);
 };
 
 class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoMicrosoft(const Triple &Triple);
+  explicit X86MCAsmInfoMicrosoft(bool Is64Bit);
 };
 
 class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoGNUCOFF(const Triple &Triple);
+  explicit X86MCAsmInfoGNUCOFF(bool Is64Bit);
 };
 } // namespace llvm
 
 #endif

lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp

 //===-- X86MCAsmInfo.cpp - X86 asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the X86MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ELF.h"
 using namespace llvm;
 

 
 static cl::opt<bool>
 MarkedJTDataRegions("mark-data-regions", cl::init(false),
   cl::desc("Mark code section jump table data regions."),
   cl::Hidden);
 
 void X86MCAsmInfoDarwin::anchor() { }
 
-X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
-  if (is64Bit)
+X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(bool Is64Bit,
+                                       bool IsMacOSXVersionLt10_6) {
+  if (Is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
-  if (!is64Bit)
+  if (!Is64Bit)
     Data64bitsDirective = nullptr;       // we can't emit a 64-bit unit
 
   // Use ## as a comment string so that .s files generated by llvm can go
   // through the GCC preprocessor without causing an error.  This is needed
   // because "clang foo.s" runs the C preprocessor, which is usually reserved
   // for .S files on other systems.  Perhaps this is because the file system
   // wasn't always case preserving or something.
   CommentString = "##";
 
   SupportsDebugInformation = true;
   UseDataRegionDirectives = MarkedJTDataRegions;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   // old assembler lacks some directives
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (IsMacOSXVersionLt10_6)
     HasWeakDefCanBeHiddenDirective = false;
 
   // Assume ld64 is new enough that the abs-ified FDE relocs may be used
   // (actually, must, since otherwise the non-extern relocations we produce
   // overwhelm ld64's tiny little mind and it fails).
   DwarfFDESymbolsUseAbsDiff = true;
 
   UseIntegratedAssembler = true;
 }
 
-X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
-  : X86MCAsmInfoDarwin(Triple) {
-}
+X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(bool Is64Bit,
+                                             bool IsMacOSXVersionLt10_6)
+    : X86MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6) {}
 
 void X86ELFMCAsmInfo::anchor() { }
 
-X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
-  bool isX32 = T.getEnvironment() == Triple::GNUX32;
-
+X86ELFMCAsmInfo::X86ELFMCAsmInfo(bool Is64Bit, bool IsX32) {
   // For ELF, x86-64 pointer size depends on the ABI.
   // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64
   // with the x32 ABI, pointer size remains the default 4.
-  PointerSize = (is64Bit && !isX32) ? 8 : 4;
+  PointerSize = (Is64Bit && !IsX32) ? 8 : 4;
 
   // OTOH, stack slot size is always 8 for x86-64, even with the x32 ABI.
-  CalleeSaveStackSlotSize = is64Bit ? 8 : 4;
+  CalleeSaveStackSlotSize = Is64Bit ? 8 : 4;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   // Debug Information
   SupportsDebugInformation = true;
 
X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
   const MCExpr *Res =
     MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOTPCREL, Context);
   const MCExpr *Four = MCConstantExpr::create(4, Context);
   return MCBinaryExpr::createAdd(Res, Four, Context);
 }
 
 void X86MCAsmInfoMicrosoft::anchor() { }
 
-X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(bool Is64Bit) {
+  if (Is64Bit) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
   } else {
     // 32-bit X86 doesn't use CFI, so this isn't a real encoding type. It's just
     // a place holder that the Windows EHStreamer looks for to suppress CFI
     // output. In particular, usesWindowsCFI() returns false.
     WinEHEncodingType = WinEH::EncodingType::X86;
   }
 
   ExceptionsType = ExceptionHandling::WinEH;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   AllowAtInName = true;
 
   UseIntegratedAssembler = true;
 }
 
 void X86MCAsmInfoGNUCOFF::anchor() { }
 
-X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
-  assert(Triple.isOSWindows() && "Windows is the only supported COFF target");
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(bool Is64Bit) {
+  if (Is64Bit) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
     ExceptionsType = ExceptionHandling::WinEH;
   } else {
     ExceptionsType = ExceptionHandling::DwarfCFI;
   }
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   UseIntegratedAssembler = true;
 }

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides X86 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCTargetDesc.h"
 #include "InstPrinter/X86ATTInstPrinter.h"
 #include "InstPrinter/X86IntelInstPrinter.h"
-#include "X86MCAsmInfo.h"
+#include "X86MCTargetMachine.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #if _MSC_VER
 #include <intrin.h>
 #endif
static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
 
   MCRegisterInfo *X = new MCRegisterInfo();
   InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
                         X86_MC::getDwarfRegFlavour(TT, true), RA);
   X86_MC::InitLLVM2SEHRegisterMapping(X);
   return X;
 }
 
-static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
-
-  MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO()) {
-    if (is64Bit)
-      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
-    else
-      MAI = new X86MCAsmInfoDarwin(TheTriple);
-  } else if (TheTriple.isOSBinFormatELF()) {
-    // Force the use of an ELF container.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
-  } else if (TheTriple.isWindowsMSVCEnvironment() ||
-             TheTriple.isWindowsCoreCLREnvironment()) {
-    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
-  } else if (TheTriple.isOSCygMing() ||
-             TheTriple.isWindowsItaniumEnvironment()) {
-    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
-  } else {
-    // The default is ELF.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
-  }
-
-  // Initialize initial frame state.
-  // Calculate amount of bytes used for return address storing
-  int stackGrowth = is64Bit ? -8 : -4;
-
-  // Initial state of the frame pointer is esp+stackGrowth.
-  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
-      nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
-  MAI->addInitialFrameState(Inst);
-
-  // Add return address to move list
-  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
-  MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
-      nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
-  MAI->addInitialFrameState(Inst2);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   bool is64Bit = TT.getArch() == Triple::x86_64;
 
   if (RM == Reloc::Default) {

 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
   return new MCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeX86TargetMC() {
   for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
-    RegisterMCTargetMachine<MCTargetMachine> Z(*T);
-
-    // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
+    RegisterMCTargetMachine<X86MCTargetMachine> Z(*T);
 
     // Register the MC codegen info.
     RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
 
     // Register the MC register info.

lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h

+//===-- X86MCTargetMachine.h - Define MCTargetMachine -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the X86 specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class X86MCTargetMachine : public MCTargetMachine {
+  X86MCTargetMachine(const X86MCTargetMachine &) = delete;
+  void operator=(const X86MCTargetMachine &) = delete;
+
+  bool Is64Bit;
+
+public:
+  X86MCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/X86/MCTargetDesc/X86MCTargetMachine.cpp

+//===-- X86MCTargetMachine.cpp - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86MCAsmInfo.h"
+#include "X86MCTargetMachine.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for X86 registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "X86GenRegisterInfo.inc"
+
+X86MCTargetMachine::X86MCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT), Is64Bit(TheTriple.getArch() == Triple::x86_64) {}
+
+MCAsmInfo *
+X86MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  bool IsX32 = TheTriple.getEnvironment() == Triple::GNUX32;
+  MCAsmInfo *MAI;
+
+  if (TheTriple.isOSBinFormatMachO()) {
+    bool IsMacOSXVersionLt10_6 =
+        TheTriple.isMacOSX() && TheTriple.isMacOSXVersionLT(10, 6);
+    if (Is64Bit)
+      MAI = new X86_64MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6);
+    else
+      MAI = new X86MCAsmInfoDarwin(Is64Bit, IsMacOSXVersionLt10_6);
+  } else if (TheTriple.isOSBinFormatELF()) {
+    // Force the use of an ELF container.
+    MAI = new X86ELFMCAsmInfo(Is64Bit, IsX32);
+  } else if (TheTriple.isWindowsMSVCEnvironment() ||
+             TheTriple.isWindowsCoreCLREnvironment()) {
+    MAI = new X86MCAsmInfoMicrosoft(Is64Bit);
+  } else if (TheTriple.isOSCygMing() ||
+             TheTriple.isWindowsItaniumEnvironment()) {
+    assert(TheTriple.isOSWindows() &&
+           "Windows is the only supported COFF target");
+    MAI = new X86MCAsmInfoGNUCOFF(Is64Bit);
+  } else {
+    // The default is ELF.
+    MAI = new X86ELFMCAsmInfo(Is64Bit, IsX32);
+  }
+
+  // Initialize initial frame state.
+  // Calculate amount of bytes used for return address storing
+  int stackGrowth = Is64Bit ? -8 : -4;
+
+  // Initial state of the frame pointer is esp+stackGrowth.
+  unsigned StackPtr = Is64Bit ? X86::RSP : X86::ESP;
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
+      nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
+  MAI->addInitialFrameState(Inst);
+
+  // Add return address to move list
+  unsigned InstPtr = Is64Bit ? X86::RIP : X86::EIP;
+  MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
+      nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
+  MAI->addInitialFrameState(Inst2);
+
+  return MAI;
+}

lib/Target/XCore/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMXCoreDesc
   XCoreMCTargetDesc.cpp
+  XCoreMCTargetMachine.cpp
   XCoreMCAsmInfo.cpp
   )

lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 #define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
-
 class XCoreMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit XCoreMCAsmInfo(const Triple &TT);
+  explicit XCoreMCAsmInfo();
 };
 
 } // namespace llvm
 
 #endif

lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp

 //===-- XCoreMCAsmInfo.cpp - XCore asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "XCoreMCAsmInfo.h"
 using namespace llvm;
 
 void XCoreMCAsmInfo::anchor() { }
 
-XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) {
+XCoreMCAsmInfo::XCoreMCAsmInfo() {
   SupportsDebugInformation = true;
   Data16bitsDirective = "\t.short\t";
   Data32bitsDirective = "\t.long\t";
   Data64bitsDirective = nullptr;
   ZeroDirective = "\t.space\t";
   CommentString = "#";
 
   AscizDirective = ".asciiz";

lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

 //===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides XCore specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "XCoreMCTargetDesc.h"
 #include "InstPrinter/XCoreInstPrinter.h"
-#include "XCoreMCAsmInfo.h"
+#include "XCoreMCTargetMachine.h"
 #include "XCoreTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "XCoreGenInstrInfo.inc"
static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
   return X;
 }
 
 static MCSubtargetInfo *
 createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
-  MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
-
-  // Initial state of the frame pointer is SP.
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0);
-  MAI->addInitialFrameState(Inst);
-
-  return MAI;
-}
-
 static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     RM = Reloc::Static;
   }
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm) {
   return new XCoreTargetAsmStreamer(S, OS);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeXCoreTargetMC() {
-  RegisterMCTargetMachine<MCTargetMachine> Y(TheXCoreTarget);
-
-  // Register the MC asm info.
-  RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);
+  RegisterMCTargetMachine<XCoreMCTargetMachine> Y(TheXCoreTarget);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget,
                                         createXCoreMCCodeGenInfo);
 
   // Register the MC instruction info.
   TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
 

lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.h

+//===-- XCoreMCTargetMachine.h - Define MCTargetMachine ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the XCore specific subclass of MCTargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XCORE_XCOREMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_XCORE_XCOREMCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class XCoreMCTargetMachine : public MCTargetMachine {
+  XCoreMCTargetMachine(const XCoreMCTargetMachine &) = delete;
+  void operator=(const XCoreMCTargetMachine &) = delete;
+
+public:
+  XCoreMCTargetMachine(const Target &T, const Triple &TT);
+
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const override;
+};
+}
+
+#endif

lib/Target/XCore/MCTargetDesc/XCoreMCTargetMachine.cpp

+//===-- XCoreMCTargetMachine.cpp - Define MCTargetMachine --  ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "XCoreMCTargetMachine.h"
+#include "XCoreMCAsmInfo.h"
+
+using namespace llvm;
+
+// Defines symbolic names for XCore registers.  This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "XCoreGenRegisterInfo.inc"
+
+XCoreMCTargetMachine::XCoreMCTargetMachine(const Target &T, const Triple &TT)
+    : MCTargetMachine(T, TT) {}
+
+MCAsmInfo *
+XCoreMCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const {
+  MCAsmInfo *MAI = new XCoreMCAsmInfo();
+
+  // Initial state of the frame pointer is SP.
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0);
+  MAI->addInitialFrameState(Inst);
+
+  return MAI;
+}