Refactor: Simplify boolean conditional return statements in lib/Target/PowerPC

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/PowerPC/PPCISelLowering.cpp

11204

Push the negate through

[wschmidt]

With Craig's suggestion, LGTM.

[LegalizeAdulthood]

lib/Target/PowerPC/PPCISelLowering.cpp

11204

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Can someone commit this for me, please? Thanks.

Richard Thomson <[e-mail]>

[LegalizeAdulthood]

Update from latest.
Update from comments.
I do not have commit access.

lib/Target/PowerPC/PPCFastISel.cpp

 
 // Determine whether the type Ty is simple enough to be handled by
 // fast-isel as a load target, and return its equivalent machine type in VT.
 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
   if (isTypeLegal(Ty, VT)) return true;
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
-    return true;
-  }
-
-  return false;
+  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32;
 }
 
 bool PPCFastISel::isValueAvailable(const Value *V) const {
   if (!isa<Instruction>(V))
     return true;
 
   const auto *I = cast<Instruction>(V);
-  if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
-    return true;
-
-  return false;
+  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
 }
 
 // Given a value Obj, create an Address object Addr that represents its
 // address.  Return false if we can't handle it.
 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
   const User *U = nullptr;
   unsigned Opcode = Instruction::UserOp1;
   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
bool PPCFastISel::SelectStore(const Instruction *I) {
   if (SrcReg == 0)
     return false;
 
   // See if we can handle this address.
   Address Addr;
   if (!PPCComputeAddress(I->getOperand(1), Addr))
     return false;
 
-  if (!PPCEmitStore(VT, SrcReg, Addr))
-    return false;
-
-  return true;
+  return PPCEmitStore(VT, SrcReg, Addr);
 }
 
 // Attempt to fast-select a branch instruction.
 bool PPCFastISel::SelectBranch(const Instruction *I) {
   const BranchInst *BI = cast<BranchInst>(I);
   MachineBasicBlock *BrBB = FuncInfo.MBB;
   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

for (ValueRotInfo &VRI : ValueRotsVec) {
               EffRLAmt += 32;
           } else {
             return false;
           }
         } else if (VRI.Repl32 != BG.Repl32) {
           return false;
         }
 
-        if (VRI.RLAmt != EffRLAmt)
-          return false;
-
-        return true;
+        return VRI.RLAmt == EffRLAmt;
       };
 
       for (auto &BG : BitGroups) {
         if (!MatchingBG(BG))
           continue;
 
         if (BG.StartIdx <= BG.EndIdx) {
           for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)

lib/Target/PowerPC/PPCISelLowering.cpp

 
 /// \brief Returns true if it is beneficial to convert a load of a constant
 /// to just the constant itself.
 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                           Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
-  if (BitSize == 0 || BitSize > 64)
-    return false;
-  return true;
+  return !(BitSize == 0 || BitSize > 64);
 }
 
 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;
   unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
   unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
   return NumBits1 == 64 && NumBits2 == 32;

lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::SubsumesPredicate(
 
   if (P1 == P2)
     return true;
 
   // Does P1 subsume P2, e.g. GE subsumes GT.
   if (P1 == PPC::PRED_LE &&
       (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
     return true;
-  if (P1 == PPC::PRED_GE &&
-      (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
-    return true;
-
-  return false;
+  return P1 == PPC::PRED_GE &&
+      (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ);
 }
 
 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
                                     std::vector<MachineOperand> &Pred) const {
   // Note: At the present time, the contents of Pred from this function is
   // unused by IfConversion. This implementation follows ARM by pushing the
   // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
   // predicate, instructions defining CTR or CTR8 are also included as

lib/Target/PowerPC/PPCRegisterInfo.cpp

bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
 
   // If we need to realign the stack, then the stack pointer can no longer
   // serve as an offset into the caller's stack space. As a result, we need a
   // base pointer.
   return needsStackRealignment(MF);
 }
 
 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
-  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
-    return false;
-
-  return true;
+  return !MF.getFunction()->hasFnAttribute("no-realign-stack");
 }
 
 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const Function *F = MF.getFunction();
   unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||

lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

private:
 
   // Dump a description of the entries in the swap vector.
   void dumpSwapVector();
 
   // Return true iff the given register is in the given class.
   bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       return RC->hasSubClassEq(MRI->getRegClass(Reg));
-    if (RC->contains(Reg))
-      return true;
-    return false;
+    return RC->contains(Reg);
   }
 
   // Return true iff the given register is a full vector register.
   bool isVecReg(unsigned Reg) {
     return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
             isRegInClass(Reg, &PPC::VRRCRegClass));
   }