[globalisel][unittests] Make it a compiler error to not call setUp() to avoid future rotten green tests

[dsanders]

Summary

Have setUp() return the target machine so that the test has to call it to be able
to use it in the if(!TM)

Also, rename setUp() to avoid potential mix up with SetUp() from gtest

[bogner]

The title/summary seems a bit confusing. The interesting part of this change is having the set up function return a target machine so it's impossible to miss - IMO renaming it is incidental. This seems reasonable to do, but I think it'd be better titled something along the lines of "Return a target machine from the test setup so that it's structurally required"

[dsanders]

In D99692#2662702, @bogner wrote:

The title/summary seems a bit confusing. The interesting part of this change is having the set up function return a target machine so it's impossible to miss - IMO renaming it is incidental. This seems reasonable to do, but I think it'd be better titled something along the lines of "Return a target machine from the test setup so that it's structurally required"

Sure I can swap them around. Thanks

[probinson]

I wasn't sure whether setUp() was supposed to be SetUp() or not. Good to have that confusion go away!

[dsanders]

Looks like phabricator noticed the revert but not the recommit. Here's the recommit:

bc21c7baaf00 [globalisel][unittests] Make it a compiler error to not call setUp() to avoid future rotten green tests

I forgot to update my local commit message to the phabricator one before committing the first time around

llvm/unittests/CodeGen/GlobalISel/CSETest.cpp

 //===- CSETest.cpp -----------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "GISelMITest.h"
 #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
 #include "gtest/gtest.h"
 
 namespace {
 
 TEST_F(AArch64GISelMITest, TestCSE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s16{LLT::scalar(16)};
   LLT s32{LLT::scalar(32)};
   auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
   auto MIBInput1 = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[1]});
   auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
auto ExtractMIB1 = CSEB.buildInstr(TargetOpcode::G_EXTRACT, {s16},
                                      {Copies[0], static_cast<uint64_t>(0)});
   auto ExtractMIB2 = CSEB.buildInstr(TargetOpcode::G_EXTRACT, {s16},
                                      {Copies[0], static_cast<uint64_t>(1)});
   EXPECT_EQ(&*ExtractMIB, &*ExtractMIB1);
   EXPECT_NE(&*ExtractMIB, &*ExtractMIB2);
 }
 
 TEST_F(AArch64GISelMITest, TestCSEConstantConfig) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s16{LLT::scalar(16)};
   auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
   auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
   auto MIBZero = B.buildConstant(s16, 0);
   GISelCSEInfo CSEInfo;
TEST_F(AArch64GISelMITest, TestCSEConstantConfig) {
 
   // Check G_IMPLICIT_DEF
   auto Undef0 = CSEB.buildUndef(s16);
   auto Undef1 = CSEB.buildUndef(s16);
   EXPECT_EQ(&*Undef0, &*Undef1);
 }
 
 TEST_F(AArch64GISelMITest, TestCSEImmediateNextCSE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s32{LLT::scalar(32)};
   // We want to check that when the CSE hit is on the next instruction, i.e. at
   // the current insert pt, that the insertion point is moved ahead of the
   // instruction.
 

llvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp

 #include "llvm/CodeGen/MachineFunction.h"
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 namespace {
 
 TEST_F(AArch64GISelMITest, FoldWithBuilder) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   // Try to use the FoldableInstructionsBuilder to build binary ops.
   ConstantFoldingMIRBuilder CFB(B.getState());
   LLT s32 = LLT::scalar(32);
   int64_t Cst;
   auto MIBCAdd =
       CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
auto MIBCSext2 =
                       {CFB1.buildConstant(s32, 0x80), uint64_t(8)});
   // This should be a constant now.
   match = mi_match(MIBCSext2.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(-0x80, Cst);
 }
 
 TEST_F(AArch64GISelMITest, FoldBinOp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s32{LLT::scalar(32)};
   auto MIBCst1 = B.buildConstant(s32, 16);
   auto MIBCst2 = B.buildConstant(s32, 9);
   auto MIBFCst1 = B.buildFConstant(s32, 1.0000001);
   auto MIBFCst2 = B.buildFConstant(s32, 2.0);
TEST_F(AArch64GISelMITest, FoldBinOp) {
   EXPECT_EQ(7ULL, FoldGSremInt.getValue().getLimitedValue());
   Optional<APInt> FoldGSremMix =
       ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1.getReg(0),
                         MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSremMix.hasValue());
   EXPECT_EQ(16ULL, FoldGSremMix.getValue().getLimitedValue());
 }
 
-} // namespace
+} // namespace
 

llvm/unittests/CodeGen/GlobalISel/GISelMITest.h

protected:
 
   /// Prepare a target specific LLVMTargetMachine.
   virtual std::unique_ptr<LLVMTargetMachine> createTargetMachine() const = 0;
 
   /// Get the stub sample MIR test function.
   virtual void getTargetTestModuleString(SmallString<512> &S,
                                          StringRef MIRFunc) const = 0;
 
-  void setUp(StringRef ExtraAssembly = "") {
-    TM = createTargetMachine();
-    if (!TM)
-      return;
+  LLVMTargetMachine *
+  createTargetMachineAndModule(StringRef ExtraAssembly = "") {
+    TheTM = createTargetMachine();
+    if (!TheTM)
+      return nullptr;
 
     SmallString<512> MIRString;
     getTargetTestModuleString(MIRString, ExtraAssembly);
 
-    ModuleMMIPair = createDummyModule(Context, *TM, MIRString, "func");
+    ModuleMMIPair = createDummyModule(Context, *TheTM, MIRString, "func");
     MF = getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
     collectCopies(Copies, MF);
     EntryMBB = &*MF->begin();
     B.setMF(*MF);
     MRI = &MF->getRegInfo();
     B.setInsertPt(*EntryMBB, EntryMBB->end());
+    return TheTM.get();
   }
 
   LLVMContext Context;
-  std::unique_ptr<LLVMTargetMachine> TM;
+  std::unique_ptr<LLVMTargetMachine> TheTM;
   MachineFunction *MF;
   std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
       ModuleMMIPair;
   SmallVector<Register, 4> Copies;
   MachineBasicBlock *EntryMBB;
   MachineIRBuilder B;
   MachineRegisterInfo *MRI;
 };

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

 //===- KnownBitsTest.cpp -------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "GISelMITest.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 
 TEST_F(AArch64GISelMITest, TestKnownBitsCst) {
   StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 1\n"
                         "  %4:_(s8) = COPY %3\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   unsigned DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
   EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
 
   KnownBits Res2 = Info.getKnownBits(DstReg);
   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) {
   StringRef MIRString = "  %10:gpr32 = MOVi32imm 1\n"
                         "  %4:_(s32) = COPY %10\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   unsigned DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIRString = "  bb.10:\n"
                         "\n"
                         "  bb.11:\n"
                         "  %12:_(s8) = G_CONSTANT i8 2\n"
                         "  G_BR %bb.12\n"
                         "\n"
                         "  bb.12:\n"
                         "  %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n"
                         "  %14:_(s8) = COPY %13\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIRString = "  bb.10:\n"
                         "\n"
                         "  bb.11:\n"
                         "  %12:_(s8) = G_CONSTANT i8 2\n"
                         "  G_BR %bb.12\n"
                         "\n"
                         "  bb.12:\n"
                         "  %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n"
                         "  %14:_(s8) = COPY %13\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIRString =
       "\n"
       "  bb.11:\n"
       "  %12:_(s64) = G_CONSTANT i64 2\n"
       "  G_BR %bb.12\n"
       "\n"
       "  bb.12:\n"
       "  %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n"
       "  %14:_(s64) = COPY %13\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIRString =
       "  bb.11:\n"
       "  %12:_(s8) = G_CONSTANT i8 2\n"
       "  G_BR %bb.12\n"
       "\n"
       "  bb.12:\n"
       "  %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n"
       "  %14:_(s8) = COPY %13\n"
       "  G_BR %bb.12\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIRString = "  bb.10:\n"
                         "  %10:_(s8) = G_CONSTANT i8 5\n"
                         "  %11:_(s8) = G_CONSTANT i8 1\n"
                         "\n"
                         "  bb.12:\n"
                         "  %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n"
                         "  %14:_(s8) = G_LSHR %13, %11\n"
                         "  %15:_(s8) = COPY %14\n"
                         "  G_BR %bb.12\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF, /*MaxDepth=*/24);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) {
   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) {
   StringRef MIRString = "  %3:_(s16) = G_CONSTANT i16 256\n"
                         "  %4:_(p0) = G_INTTOPTR %3\n"
                         "  %5:_(s32) = G_PTRTOINT %4\n"
                         "  %6:_(s32) = COPY %5\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ(256u, Res.One.getZExtValue());
TEST_F(AArch64GISelMITest, TestKnownBitsAND) {
    %mask2:_(s8) = G_CONSTANT i8 32
    %mask3:_(s8) = G_CONSTANT i8 24
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %and:_(s8) = G_AND %val0, %val1
    %copy_and:_(s8) = COPY %and
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsOR) {
    %mask2:_(s8) = G_CONSTANT i8 32
    %mask3:_(s8) = G_CONSTANT i8 24
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %or:_(s8) = G_OR %val0, %val1
    %copy_or:_(s8) = COPY %or
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsXOR) {
    %mask2:_(s8) = G_CONSTANT i8 32
    %mask3:_(s8) = G_CONSTANT i8 24
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %xor:_(s8) = G_XOR %val0, %val1
    %copy_xor:_(s8) = COPY %xor
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   // Xor KnowBits does not track if we are doing xor of unknown bit with itself
   // or negated itself.
   //   00??1?10
   // ^ 00?11000
   // = 00??0?10
   EXPECT_EQ(0x02u, Res.One.getZExtValue());
   EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsXORConstant) {
   StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 4\n"
                         "  %4:_(s8) = G_CONSTANT i8 7\n"
                         "  %5:_(s8) = G_XOR %3, %4\n"
                         "  %6:_(s8) = COPY %5\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ(3u, Res.One.getZExtValue());
TEST_F(AArch64GISelMITest, TestKnownBitsASHR) {
    %mask2:_(s8) = G_CONSTANT i8 204
    %mask3:_(s8) = G_CONSTANT i8 18
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %ashr1:_(s8) = G_ASHR %val1, %cst0
    %copy_ashr1:_(s8) = COPY %ashr1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsLSHR) {
    %mask2:_(s8) = G_CONSTANT i8 204
    %mask3:_(s8) = G_CONSTANT i8 18
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %lshr1:_(s8) = G_LSHR %val1, %cst0
    %copy_lshr1:_(s8) = COPY %lshr1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsSHL) {
    %mask1:_(s8) = G_CONSTANT i8 72
    %tmp:_(s8) = G_AND %unknown, %mask0
    %val:_(s8) = G_OR %tmp, %mask1
    %cst:_(s8) = G_CONSTANT i8 3
    %shl:_(s8) = G_SHL %val, %cst
    %copy_shl:_(s8) = COPY %shl
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsADD) {
    %mask2:_(s16) = G_CONSTANT i16 4096
    %mask3:_(s16) = G_CONSTANT i16 371
    %tmp1:_(s16) = G_AND %unknown, %mask2
    %val1:_(s16) = G_OR %tmp1, %mask3
    %add:_(s16) = G_ADD %val0, %val1
    %copy_add:_(s16) = COPY %add
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsSUB) {
    %mask2:_(s16) = G_CONSTANT i16 4096
    %mask3:_(s16) = G_CONSTANT i16 371
    %tmp1:_(s16) = G_AND %unknown, %mask2
    %val1:_(s16) = G_OR %tmp1, %mask3
    %sub:_(s16) = G_SUB %val0, %val1
    %copy_sub:_(s16) = COPY %sub
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsMUL) {
    %mask1:_(s16) = G_CONSTANT i16 18
    %tmp:_(s16) = G_AND %load0, %mask0
    %val0:_(s16) = G_OR %tmp, %mask1
    %cst:_(s16) = G_CONSTANT i16 12
    %mul:_(s16) = G_MUL %val0, %cst
    %copy_mul:_(s16) = COPY %mul
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);

 TEST_F(AArch64GISelMITest, TestKnownBitsICMP) {
   StringRef MIRString = R"(
    %cst0:_(s32) = G_CONSTANT i32 0
    %cst1:_(s32) = G_CONSTANT i32 1
    %icmp:_(s32) = G_ICMP intpred(ne), %cst0, %cst1
    %copy_icmp:_(s32) = COPY %icmp
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   // For targets that use 0 or 1 as icmp result in large register set high bits
   // to 0, does not analyze operands/compare predicate.
   EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
   EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsFCMP) {
   StringRef MIRString = R"(
    %cst0:_(s32) = G_FCONSTANT float 0.0
    %cst1:_(s32) = G_FCONSTANT float 1.0
    %fcmp:_(s32) = G_FCMP floatpred(one), %cst0, %cst1
    %copy_fcmp:_(s32) = COPY %fcmp
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsSelect) {
    %mask3:_(s8) = G_CONSTANT i8 36
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %cond:_(s1) = G_CONSTANT i1 false
    %select:_(s8) = G_SELECT %cond, %val0, %val1
    %copy_select:_(s8) = COPY %select
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
StringRef MIR = "  %3:_(s32) = G_TRUNC %0\n"
                   "  %14:_(p0) = G_INTTOPTR %7\n"
                   "  %16:_(s32) = G_PTRTOINT %14\n"
                   "  %8:_(s32) = G_SHL %3, %5\n"
                   "  %9:_(s32) = G_SHL %4, %5\n"
                   "  %10:_(s32) = G_OR %8, %6\n"
                   "  %11:_(s32) = G_OR %9, %16\n"
                   "  %12:_(s32) = G_MUL %10, %11\n"
                   "  %13:_(s32) = COPY %12\n";
-  setUp(MIR);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIR);
   if (!TM)
     return;
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Known = Info.getKnownBits(SrcReg);
   EXPECT_FALSE(Known.hasConflict());
   EXPECT_EQ(32u, Known.One.getZExtValue());
   EXPECT_EQ(95u, Known.Zero.getZExtValue());
   APInt Zeroes = Info.getKnownZeroes(SrcReg);
   EXPECT_EQ(Known.Zero, Zeroes);
 }
 
 TEST_F(AArch64GISelMITest, TestSignBitIsZero) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT S32 = LLT::scalar(32);
   auto SignBit = B.buildConstant(S32, 0x80000000);
   auto Zero = B.buildConstant(S32, 0);
 
   GISelKnownBits KnownBits(*MF);
StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 1\n"
                         "  %7:_(s8) = G_CONSTANT i8 127\n"
                         "  %8:_(s8) = COPY %7\n"
 
                         "  %9:_(s8) = G_CONSTANT i8 32\n"
                         "  %10:_(s8) = COPY %9\n"
 
                         "  %11:_(s8) = G_CONSTANT i8 -32\n"
                         "  %12:_(s8) = COPY %11\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg1 = Copies[Copies.size() - 5];
   Register CopyRegNeg1 = Copies[Copies.size() - 4];
   Register CopyReg127 = Copies[Copies.size() - 3];
   Register CopyReg32 = Copies[Copies.size() - 2];
   Register CopyRegNeg32 = Copies[Copies.size() - 1];
 
TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {
   StringRef MIRString = "  %3:_(p0) = G_IMPLICIT_DEF\n"
                         "  %4:_(s8) = G_LOAD %3 :: (load 1)\n"
                         "  %5:_(s32) = G_SEXT %4\n"
                         "  %6:_(s32) = COPY %5\n"
 
                         "  %7:_(s8) = G_CONSTANT i8 -1\n"
                         "  %8:_(s32) = G_SEXT %7\n"
                         "  %9:_(s32) = COPY %8\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopySextLoad = Copies[Copies.size() - 2];
   Register CopySextNeg1 = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
   EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));
TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) {
 
    %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9
    %copy_inreg9_sext:_(s32) = COPY %inreg9_sext
 
    %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31
    %copy_inreg31_sext:_(s32) = COPY %inreg31_sext
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyInReg7 = Copies[Copies.size() - 9];
   Register CopyInReg8 = Copies[Copies.size() - 8];
   Register CopyInReg9 = Copies[Copies.size() - 7];
   Register CopyInReg31 = Copies[Copies.size() - 6];
 
TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) {
 
    %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9
    %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext
 
    %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31
    %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyInReg1 = Copies[Copies.size() - 10];
   Register CopyInReg7 = Copies[Copies.size() - 9];
   Register CopyInReg8 = Copies[Copies.size() - 8];
   Register CopyInReg9 = Copies[Copies.size() - 7];
   Register CopyInReg31 = Copies[Copies.size() - 6];
StringRef MIRString = "  %3:_(p0) = G_IMPLICIT_DEF\n"
 
                         "  %7:_(s32) = G_CONSTANT i32 -1\n"
                         "  %8:_(s8) = G_TRUNC %7\n"
                         "  %9:_(s8) = COPY %8\n"
 
                         "  %10:_(s32) = G_CONSTANT i32 7\n"
                         "  %11:_(s8) = G_TRUNC %10\n"
                         "  %12:_(s8) = COPY %11\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyTruncLoad = Copies[Copies.size() - 3];
   Register CopyTruncNeg1 = Copies[Copies.size() - 2];
   Register CopyTrunc7 = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
StringRef MIRString =
     "  %8:_(s32) = COPY %7\n"
 
     "  %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n"
     "  %10:_(s32) = COPY %9\n"
 
     "  %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n"
     "  %12:_(s32) = COPY %11\n";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyLoadUByte = Copies[Copies.size() - 4];
   Register CopyLoadSByte = Copies[Copies.size() - 3];
   Register CopyLoadUShort = Copies[Copies.size() - 2];
   Register CopyLoadSShort = Copies[Copies.size() - 1];
 
StringRef MIRString =
     "  %8:_(p4) = COPY %7\n"
     "  %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"
     "  %10:_(p4) = COPY %9\n"
     "  %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"
     "  %12:_(p4) = COPY %11\n"
     "  %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"
     "  %14:_(p4) = COPY %13\n";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyDispatchPtr = Copies[Copies.size() - 5];
   Register CopyQueuePtr = Copies[Copies.size() - 4];
   Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];
   Register CopyImplicitArgPtr = Copies[Copies.size() - 2];
   Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];
TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {
 
   %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt
   %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask
 
   %or_pow2:_(s32) = G_OR %zero, %two
   %copy_or_pow2:_(s32) = COPY %or_pow2
 
 )MIR";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   GISelKnownBits KB(*MF);
 
   Register CopyZero = Copies[Copies.size() - 12];
   Register CopyOne = Copies[Copies.size() - 11];
   Register CopyTwo = Copies[Copies.size() - 10];

 
 TEST_F(AArch64GISelMITest, TestMetadata) {
   StringRef MIRString = "  %imp:_(p0) = G_IMPLICIT_DEF\n"
                         "  %load:_(s8) = G_LOAD %imp(p0) :: (load 1)\n"
                         "  %ext:_(s32) = G_ZEXT %load(s8)\n"
                         "  %cst:_(s32) = G_CONSTANT i32 1\n"
                         "  %and:_(s32) = G_AND %ext, %cst\n"
                         "  %copy:_(s32) = COPY %and(s32)\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
 
   // We need a load with a metadata range for this to break. Fudge the load in
StringRef MIRString = "  %c1:_(s16) = G_CONSTANT i16 1\n"
                         "  %x:_(s16) = G_IMPLICIT_DEF\n"
                         "  %y:_(s16) = G_AND %x, %c1\n"
                         "  %anyext:_(s32) = G_ANYEXT %y(s16)\n"
                         "  %r1:_(s32) = COPY %anyext\n"
                         "  %zext:_(s32) = G_ZEXT %y(s16)\n"
                         "  %r2:_(s32) = COPY %zext\n"
                         "  %sext:_(s32) = G_SEXT %y(s16)\n"
                         "  %r3:_(s32) = COPY %sext\n";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyRegAny = Copies[Copies.size() - 3];
   Register CopyRegZ = Copies[Copies.size() - 2];
   Register CopyRegS = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   MachineInstr *Copy;
TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {
    %copy_inreg3:_(s32) = COPY %inreg3
 
    ; Extending from a known set bit, overwriting all of the high set bits.
    ; 111...1110
    %inreg4:_(s32) = G_SEXT_INREG %ten, 2
    %copy_inreg4:_(s32) = COPY %inreg4
 
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   GISelKnownBits Info(*MF);
   KnownBits Res;
   auto GetKB = [&](unsigned Idx) {
     Register CopyReg = Copies[Idx];
     auto *Copy = MRI->getVRegDef(CopyReg);
     return Info.getKnownBits(Copy->getOperand(1).getReg());
TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {
    %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 2
    %copy_assert_sext3:_(s32) = COPY %assert_sext3
 
    ; Extending from a known set bit, overwriting all of the high set bits.
    ; 111...1110
    %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 2
    %copy_assert_sext4:_(s32) = COPY %assert_sext4
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   GISelKnownBits Info(*MF);
   KnownBits Res;
   auto GetKB = [&](unsigned Idx) {
     Register CopyReg = Copies[Idx];
     auto *Copy = MRI->getVRegDef(CopyReg);
     return Info.getKnownBits(Copy->getOperand(1).getReg());
TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
   StringRef MIRString = R"(
    %val0:_(s16) = G_CONSTANT i16 35224
    %val1:_(s16) = G_CONSTANT i16 17494
    %val2:_(s16) = G_CONSTANT i16 4659
    %val3:_(s16) = G_CONSTANT i16 43981
    %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3
    %mergecopy:_(s64) = COPY %merge
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   const uint64_t TestVal = UINT64_C(0xabcd123344568998);
   Register CopyMerge = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(CopyMerge);
   EXPECT_EQ(64u, Res.getBitWidth());
   EXPECT_EQ(TestVal, Res.One.getZExtValue());
   EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) {
   StringRef MIRString = R"(
    %val:_(s64) = G_CONSTANT i64 12379570962110515608
    %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val
    %part0:_(s16) = COPY %val0
    %part1:_(s16) = COPY %val1
    %part2:_(s16) = COPY %val2
    %part3:_(s16) = COPY %val3
 
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   const uint64_t TestVal = UINT64_C(0xabcd123344568998);
   GISelKnownBits Info(*MF);
 
   int Offset = -4;
   for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) {

 TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {
   StringRef MIRString = R"(
    %const:_(s32) = G_CONSTANT i32 287454020
    %bswap:_(s32) = G_BSWAP %const
    %bitreverse:_(s32) = G_BITREVERSE %const
    %copy_bswap:_(s32) = COPY %bswap
    %copy_bitreverse:_(s32) = COPY %bitreverse
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   const uint32_t TestVal = 0x11223344;
 
   Register CopyBSwap = Copies[Copies.size() - 2];
   Register CopyBitReverse = Copies[Copies.size() - 1];
 
TEST_F(AArch64GISelMITest, TestKnownBitsUMAX) {
    %mask6:_(s8) = G_CONSTANT i8 4
    %mask7:_(s8) = G_CONSTANT i8 11
    %tmp4:_(s8) = G_AND %unknown, %mask6
    %val4:_(s8) = G_OR %tmp4, %mask7
    %umax1:_(s8) = G_UMAX %val3, %val4
    %copy_umax1:_(s8) = COPY %umax1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   // Compares min/max of LHS and RHS, min uses 0 for unknown bits, max uses 1.

 TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {
   StringRef MIRString = R"(
    %val:_(s32) = COPY $w0
    %zext:_(s64) = G_ZEXT %val
    %const:_(s64) = G_CONSTANT i64 -256
    %umax:_(s64) = G_UMAX %zext, %const
    %copy_umax:_(s64) = COPY %umax
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyUMax = Copies[Copies.size() - 1];
   GISelKnownBits Info(*MF);
 
   KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
   EXPECT_EQ(64u, KnownUmax.getBitWidth());
TEST_F(AArch64GISelMITest, TestKnownBitsUMIN) {
    %mask2:_(s8) = G_CONSTANT i8 3
    %mask3:_(s8) = G_CONSTANT i8 12
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %umin:_(s8) = G_UMIN %val0, %val1
    %copy_umin:_(s8) = COPY %umin
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsSMAX) {
    %mask2:_(s8) = G_CONSTANT i8 1
    %mask3:_(s8) = G_CONSTANT i8 128
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %smax:_(s8) = G_SMAX %val0, %val1
    %copy_smax:_(s8) = COPY %smax
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsSMIN) {
    %mask2:_(s8) = G_CONSTANT i8 1
    %mask3:_(s8) = G_CONSTANT i8 128
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %smin:_(s8) = G_SMIN %val0, %val1
    %copy_smin:_(s8) = COPY %smin
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestInvalidQueries) {
    %src:_(s32) = COPY $w0
    %thirty2:_(s32) = G_CONSTANT i32 32
    %equalSized:_(s32) = G_SHL %src, %thirty2
    %copy1:_(s32) = COPY %equalSized
    %thirty3:_(s32) = G_CONSTANT i32 33
    %biggerSized:_(s32) = G_SHL %src, %thirty3
    %copy2:_(s32) = COPY %biggerSized
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register EqSizedCopyReg = Copies[Copies.size() - 2];
   MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
   Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
 
   Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
 
    %assert63:_(s64) = G_ASSERT_ZEXT %copy, 63
    %copy_assert63:_(s64) = COPY %assert63
 
    %assert3:_(s64) = G_ASSERT_ZEXT %copy, 3
    %copy_assert3:_(s64) = COPY %assert3
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyAssert8 = Copies[Copies.size() - 4];
   Register CopyAssert1 = Copies[Copies.size() - 3];
   Register CopyAssert63 = Copies[Copies.size() - 2];
   Register CopyAssert3 = Copies[Copies.size() - 1];
 

llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

TEST_F(AArch64GISelMITest, TestKnownBitsBuildVector) {
    %mask2:_(s8) = G_CONSTANT i8 146
    %mask3:_(s8) = G_CONSTANT i8 36
    %tmp1:_(s8) = G_AND %unknown, %mask2
    %val1:_(s8) = G_OR %tmp1, %mask3
    %vector:_(<2 x s8>) = G_BUILD_VECTOR %val0, %val1
    %copy_vector:_(<2 x s8>) = COPY %vector
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHI) {
    %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8)
    G_BR %bb.12
 
    bb.12:
    %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11
    %16:_(<2 x s8>) = COPY %15
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIToNonGenericReg) {
    %13:_(<2 x s16>) = G_BUILD_VECTOR %12:_(s16), %12:_(s16)
    G_BR %bb.12
 
    bb.12:
    %15:_(<2 x s16>) = PHI %10, %bb.10, %13(<2 x s16>), %bb.11
    %16:_(<2 x s16>) = COPY %15
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorUnknownPHI) {
    %13:_(<2 x s32>) = G_BUILD_VECTOR %12:_(s32), %12:_(s32)
    G_BR %bb.12
 
    bb.12:
    %14:_(<2 x s32>) = PHI %10(<2 x s32>), %bb.10, %13(<2 x s32>), %bb.11
    %15:_(<2 x s32>) = COPY %14
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIWithLoop) {
    G_BR %bb.12
 
    bb.12:
    %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11, %16(<2 x s8>), %bb.12
    %16:_(<2 x s8>) = COPY %15
    G_BR %bb.12
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorDecreasingCstPHIWithLoop) {
 
    bb.12:
    %13:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.12
    %14:_(<2 x s8>) = G_LSHR %13, %12
    %15:_(<2 x s8>) = COPY %14
    G_BR %bb.12
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   Register DstReg = FinalCopy->getOperand(0).getReg();
   GISelKnownBits Info(*MF, /*MaxDepth=*/24);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorAND) {
    %mask3:_(s8) = G_CONSTANT i8 24
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %and:_(<2 x s8>) = G_AND %val0, %val1
    %copy_and:_(<2 x s8>) = COPY %and
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorOR) {
    %mask3:_(s8) = G_CONSTANT i8 24
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %or:_(<2 x s8>) = G_OR %val0, %val1
    %copy_or:_(<2 x s8>) = COPY %or
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorXOR) {
    %mask3:_(s8) = G_CONSTANT i8 24
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %xor:_(<2 x s8>) = G_XOR %val0, %val1
    %copy_xor:_(<2 x s8>) = COPY %xor
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorXORConstant) {
    %8:_(<2 x s8>) = COPY %7
 
    %9:_(s8) = G_CONSTANT i8 12
    %10:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %9:_(s8)
    %11:_(<2 x s8>) = G_XOR %10, %6
    %12:_(<2 x s8>) = COPY %11
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   GISelKnownBits Info(*MF);
   Register CopySplatReg = Copies[Copies.size() - 2];
   MachineInstr *FinalSplatCopy = MRI->getVRegDef(CopySplatReg);
   Register SrcSplatReg = FinalSplatCopy->getOperand(1).getReg();
   KnownBits ResNonSplat = Info.getKnownBits(SrcSplatReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorASHR) {
    %mask3:_(s8) = G_CONSTANT i8 18
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %ashr1:_(<2 x s8>) = G_ASHR %val1, %cst0_splat
    %copy_ashr1:_(<2 x s8>) = COPY %ashr1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorLSHR) {
    %mask3:_(s8) = G_CONSTANT i8 18
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %lshr1:_(<2 x s8>) = G_LSHR %val1, %cst0_splat
    %copy_lshr1:_(<2 x s8>) = COPY %lshr1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSHL) {
    %tmp:_(<2 x s8>) = G_AND %unknown, %mask0_splat
    %val:_(<2 x s8>) = G_OR %tmp, %mask1_splat
    %cst:_(s8) = G_CONSTANT i8 3
    %cst_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst, %cst
    %shl:_(<2 x s8>) = G_SHL %val, %cst_splat
    %copy_shl:_(<2 x s8>) = COPY %shl
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorADD) {
    %mask3:_(s16) = G_CONSTANT i16 371
    %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat
    %add:_(<2 x s16>) = G_ADD %val0, %val1
    %copy_add:_(<2 x s16>) = COPY %add
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSUB) {
    %mask3:_(s16) = G_CONSTANT i16 371
    %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat
    %sub:_(<2 x s16>) = G_SUB %val0, %val1
    %copy_sub:_(<2 x s16>) = COPY %sub
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorMUL) {
    %tmp:_(<2 x s16>) = G_AND %unknown, %mask0_splat
    %val0:_(<2 x s16>) = G_OR %tmp, %mask1_splat
    %cst:_(s16) = G_CONSTANT i16 12
    %cst_splat:_(<2 x s16>) = G_BUILD_VECTOR %cst, %cst
    %mul:_(<2 x s16>) = G_MUL %val0, %cst_splat
    %copy_mul:_(<2 x s16>) = COPY %mul
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSelect) {
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %cond:_(s1) = G_CONSTANT i1 false
    %cond_splat:_(<2 x s1>) = G_BUILD_VECTOR %cond, %cond
    %select:_(<2 x s8>) = G_SELECT %cond_splat, %val0, %val1
    %copy_select:_(<2 x s8>) = COPY %select
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ(0x20u, Res.One.getZExtValue());
   EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestVectorSignBitIsZero) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT V2S32 = LLT::vector(2, 32);
   // Vector buildConstant makes splat G_BUILD_VECTOR instruction.
   auto SignBit = B.buildConstant(V2S32, 0x80000000);
   auto Zero = B.buildConstant(V2S32, 0);
 
TEST_F(AArch64GISelMITest, TestVectorNumSignBitsConstant) {
 
    %18:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %15:_(s8)
    %19:_(<2 x s8>) = COPY %18
 
    %20:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %15:_(s8)
    %21:_(<2 x s8>) = COPY %20
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg1 = Copies[Copies.size() - 7];
   Register CopyRegNeg1 = Copies[Copies.size() - 6];
   Register CopyReg127 = Copies[Copies.size() - 5];
   Register CopyReg32 = Copies[Copies.size() - 4];
   Register CopyRegNeg32 = Copies[Copies.size() - 3];
TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSext) {
    %10:_(<2 x s32>) = COPY %9
 
    %11:_(s8) = G_CONSTANT i8 -10
    %12:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %11:_(s8)
    %13:_(<2 x s32>) = G_SEXT %12
    %14:_(<2 x s32>) = COPY %13
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopySextLoad = Copies[Copies.size() - 3];
   Register CopySextNeg1 = Copies[Copies.size() - 2];
   Register CopySextNonSplat = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSextInReg) {
 
    %inreg9_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 9
    %copy_inreg9_sext:_(<2 x s32>) = COPY %inreg9_sext
 
    %inreg31_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 31
    %copy_inreg31_sext:_(<2 x s32>) = COPY %inreg31_sext
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyInReg7 = Copies[Copies.size() - 9];
   Register CopyInReg8 = Copies[Copies.size() - 8];
   Register CopyInReg9 = Copies[Copies.size() - 7];
   Register CopyInReg31 = Copies[Copies.size() - 6];
 
TEST_F(AArch64GISelMITest, TestNumSignBitsVectorAssertSext) {
 
    %assert_sext9_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 9
    %copy_assert_sext9_sext:_(<2 x s32>) = COPY %assert_sext9_sext
 
    %assert_sext31_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 31
    %copy_assert_sext31_sext:_(<2 x s32>) = COPY %assert_sext31_sext
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyInReg1 = Copies[Copies.size() - 10];
   Register CopyInReg7 = Copies[Copies.size() - 9];
   Register CopyInReg8 = Copies[Copies.size() - 8];
   Register CopyInReg9 = Copies[Copies.size() - 7];
   Register CopyInReg31 = Copies[Copies.size() - 6];
TEST_F(AArch64GISelMITest, TestVectorNumSignBitsTrunc) {
    %10:_(<2 x s8>) = COPY %9
 
    %11:_(s32) = G_CONSTANT i32 7
    %12:_(<2 x s32>) = G_BUILD_VECTOR %11:_(s32), %11:_(s32)
    %13:_(<2 x s8>) = G_TRUNC %12
    %14:_(<2 x s8>) = COPY %13
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyTruncLoad = Copies[Copies.size() - 3];
   Register CopyTruncNeg1 = Copies[Copies.size() - 2];
   Register CopyTrunc7 = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
TEST_F(AMDGPUGISelMITest, TestVectorIsKnownToBeAPowerOfTwo) {
 
   %lshr_sign_mask:_(<2 x s32>) = G_LSHR %sign_mask_splat, %shift_amt
   %copy_lshr_sign_mask:_(<2 x s32>) = COPY %lshr_sign_mask
 
   %or_pow2:_(<2 x s32>) = G_OR %zero_splat, %two_splat
   %copy_or_pow2:_(<2 x s32>) = COPY %or_pow2
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   GISelKnownBits KB(*MF);
 
   Register CopyZero = Copies[Copies.size() - 12];
   Register CopyOne = Copies[Copies.size() - 11];
   Register CopyTwo = Copies[Copies.size() - 10];
TEST_F(AArch64GISelMITest, TestVectorMetadata) {
    %load:_(<2 x s8>) = G_LOAD %imp(p0) :: (load 2)
    %ext:_(<2 x s32>) = G_ZEXT %load(<2 x s8>)
    %cst_elt:_(s32) = G_CONSTANT i32 1
    %cst:_(<2 x s32>) = G_BUILD_VECTOR %cst_elt:_(s32), %cst_elt:_(s32)
    %and:_(<2 x s32>) = G_AND %ext, %cst
    %copy:_(<2 x s32>) = COPY %and(<2 x s32>)
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   Register SrcReg = FinalCopy->getOperand(1).getReg();
 
   MachineInstr *And = MRI->getVRegDef(SrcReg);
TEST_F(AArch64GISelMITest, TestVectorKnownBitsExt) {
    %anyext:_(<2 x s32>) = G_ANYEXT %y(<2 x s16>)
    %r1:_(<2 x s32>) = COPY %anyext
    %zext:_(<2 x s32>) = G_ZEXT %y(<2 x s16>)
    %r2:_(<2 x s32>) = COPY %zext
    %sext:_(<2 x s32>) = G_SEXT %y(<2 x s16>)
    %r3:_(<2 x s32>) = COPY %sext
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   Register CopyRegAny = Copies[Copies.size() - 3];
   Register CopyRegZ = Copies[Copies.size() - 2];
   Register CopyRegS = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   MachineInstr *Copy;
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSextInReg) {
    %copy_inreg3:_(<2 x s32>) = COPY %inreg3
 
    ; Extending from a known set bit, overwriting all of the high set bits.
    ; 111...1110
    %inreg4:_(<2 x s32>) = G_SEXT_INREG %ten_splat, 2
    %copy_inreg4:_(<2 x s32>) = COPY %inreg4
 
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   GISelKnownBits Info(*MF);
   KnownBits Res;
   auto GetKB = [&](unsigned Idx) {
     Register CopyReg = Copies[Idx];
     auto *Copy = MRI->getVRegDef(CopyReg);
     return Info.getKnownBits(Copy->getOperand(1).getReg());
TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertSext) {
    %assert_sext3:_(<2 x s32>) = G_ASSERT_SEXT %or, 2
    %copy_assert_sext3:_(<2 x s32>) = COPY %assert_sext3
 
    ; Extending from a known set bit, overwriting all of the high set bits.
    ; 111...1110
    %assert_sext4:_(<2 x s32>) = G_ASSERT_SEXT %ten_splat, 2
    %copy_assert_sext4:_(<2 x s32>) = COPY %assert_sext4
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
   GISelKnownBits Info(*MF);
   KnownBits Res;
   auto GetKB = [&](unsigned Idx) {
     Register CopyReg = Copies[Idx];
     auto *Copy = MRI->getVRegDef(CopyReg);
     return Info.getKnownBits(Copy->getOperand(1).getReg());
TEST_F(AArch64GISelMITest, TestVectorKnownBitsBSwapBitReverse) {
   StringRef MIRString = R"(
    %const:_(s32) = G_CONSTANT i32 287454020
    %const_splat:_(<2 x s32>) = G_BUILD_VECTOR %const:_(s32), %const:_(s32)
    %bswap:_(<2 x s32>) = G_BSWAP %const_splat
    %bitreverse:_(<2 x s32>) = G_BITREVERSE %const_splat
    %copy_bswap:_(<2 x s32>) = COPY %bswap
    %copy_bitreverse:_(<2 x s32>) = COPY %bitreverse
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   const uint32_t TestVal = 0x11223344;
 
   Register CopyBSwap = Copies[Copies.size() - 2];
   Register CopyBitReverse = Copies[Copies.size() - 1];
 
TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMAX) {
    %mask7:_(s8) = G_CONSTANT i8 11
    %mask7_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask7, %mask7
    %tmp4:_(<2 x s8>) = G_AND %unknown, %mask6_splat
    %val4:_(<2 x s8>) = G_OR %tmp4, %mask7_splat
    %umax1:_(<2 x s8>) = G_UMAX %val3, %val4
    %copy_umax1:_(<2 x s8>) = COPY %umax1
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 2];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestVectorKnownBitsUMax) {
    %val:_(<2 x s32>) = COPY $x0
    %zext:_(<2 x s64>) = G_ZEXT %val
    %const:_(s64) = G_CONSTANT i64 -256
    %const_splat:_(<2 x s64>) = G_BUILD_VECTOR %const:_(s64), %const:_(s64)
    %umax:_(<2 x s64>) = G_UMAX %zext, %const_splat
    %copy_umax:_(<2 x s64>) = COPY %umax
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyUMax = Copies[Copies.size() - 1];
   GISelKnownBits Info(*MF);
 
   KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
   EXPECT_EQ(64u, KnownUmax.getBitWidth());
TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMIN) {
    %mask3:_(s8) = G_CONSTANT i8 12
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %umin:_(<2 x s8>) = G_UMIN %val0, %val1
    %copy_umin:_(<2 x s8>) = COPY %umin
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMAX) {
    %mask3:_(s8) = G_CONSTANT i8 128
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %smax:_(<2 x s8>) = G_SMAX %val0, %val1
    %copy_smax:_(<2 x s8>) = COPY %smax
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMIN) {
    %mask3:_(s8) = G_CONSTANT i8 128
    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
    %smin:_(<2 x s8>) = G_SMIN %val0, %val1
    %copy_smin:_(<2 x s8>) = COPY %smin
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyReg0 = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res0 = Info.getKnownBits(SrcReg0);
   EXPECT_EQ(0x80u, Res0.One.getZExtValue());
   EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestVectorInvalidQueries) {
   StringRef MIRString = R"(
    %src:_(<2 x s32>) = COPY $x0
    %thirty2:_(s32) = G_CONSTANT i32 32
    %thirty2_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty2:_(s32), %thirty2:_(s32)
    %equalSized:_(<2 x s32>) = G_SHL %src, %thirty2_splat
    %copy1:_(<2 x s32>) = COPY %equalSized
    %thirty3:_(s32) = G_CONSTANT i32 33
    %thirty3_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty3:_(s32), %thirty3:_(s32)
    %biggerSized:_(<2 x s32>) = G_SHL %src, %thirty3_splat
    %copy2:_(<2 x s32>) = COPY %biggerSized
 )";
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register EqSizedCopyReg = Copies[Copies.size() - 2];
   MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
   Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
 
   Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) {
 
    %assert63:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 63
    %copy_assert63:_(<2 x s64>) = COPY %assert63
 
    %assert3:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 3
    %copy_assert3:_(<2 x s64>) = COPY %assert3
 )";
 
-  setUp(MIRString);
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString);
   if (!TM)
     return;
 
   Register CopyAssert8 = Copies[Copies.size() - 4];
   Register CopyAssert1 = Copies[Copies.size() - 3];
   Register CopyAssert63 = Copies[Copies.size() - 2];
   Register CopyAssert3 = Copies[Copies.size() - 1];
 

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

public:
   void changingInstr(MachineInstr &MI) override {}
   void changedInstr(MachineInstr &MI) override {}
   void createdInstr(MachineInstr &MI) override {}
   void erasingInstr(MachineInstr &MI) override {}
 };
 
 // Test G_ROTL/G_ROTR lowering.
 TEST_F(AArch64GISelMITest, LowerRotates) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
 
   LLT S32 = LLT::scalar(32);
TEST_F(AArch64GISelMITest, LowerRotates) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test G_ROTL/G_ROTR non-pow2 lowering.
 TEST_F(AArch64GISelMITest, LowerRotatesNonPow2) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
 
   LLT S24 = LLT::scalar(24);
TEST_F(AArch64GISelMITest, LowerRotatesNonPow2) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test vector G_ROTR lowering.
 TEST_F(AArch64GISelMITest, LowerRotatesVector) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
 
   LLT S32 = LLT::scalar(32);
TEST_F(AArch64GISelMITest, LowerRotatesVector) {
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test CTTZ expansion when CTTZ_ZERO_UNDEF is legal or custom,
 // in which case it becomes CTTZ_ZERO_UNDEF with select.
 TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).legalFor({{s32, s64}});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ expansion in terms of CTLZ
 TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ1) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ).legalFor({{s64, s64}});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ1) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ scalar narrowing
 TEST_F(AArch64GISelMITest, NarrowScalarCTLZ) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ).legalFor({{s32, s32}});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, NarrowScalarCTLZ) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ scalar narrowing
 TEST_F(AArch64GISelMITest, NarrowScalarCTTZ) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTTZ).legalFor({{s32, s64}});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, NarrowScalarCTTZ) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ expansion in terms of CTPOP
 TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ2) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTPOP).legalFor({{s64, s64}});
   });
   // Build
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ2) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTPOP widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP1) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
       getActionDefinitionsBuilder(G_CTPOP).legalFor({{s16, s16}});
     });
 
TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP1) {
   CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY [[CTPOP]]:_(s16)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test a strange case where the result is wider than the source
 TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP2) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
       getActionDefinitionsBuilder(G_CTPOP).legalFor({{s32, s16}});
     });
 
TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP2) {
   CHECK: [[COPY:%[0-9]+]]:_(s32) = G_ZEXT [[CTPOP]]:_(s16)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ_ZERO_UNDEF expansion in terms of CTTZ
 TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ3) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTTZ).legalFor({{s64, s64}});
   });
   // Build
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ3) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ expansion in terms of CTLZ_ZERO_UNDEF
 TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).legalFor({{s64, s64}});
   });
   // Build
TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ expansion in terms of CTLZ_ZERO_UNDEF if the latter is a libcall
 TEST_F(AArch64GISelMITest, LowerBitCountingCTLZLibcall) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).libcallFor({{s32, s64}});
   });
   // Build
TEST_F(AArch64GISelMITest, LowerBitCountingCTLZLibcall) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ expansion
 TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ1) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTPOP).legalFor({{s8, s8}});
   });
   // Build
TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ1) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTLZ) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenBitCountingCTLZ) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTLZ_ZERO_UNDEF widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroUndef) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroUndef) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTPOP widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTPOP).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ_ZERO_UNDEF widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ_ZERO_UNDEF) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ_ZERO_UNDEF) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // CTTZ widening.
 TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTTZ).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ) {
   CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC [[Cttz]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 // UADDO widening.
 TEST_F(AArch64GISelMITest, WidenUADDO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_ADD).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenUADDO) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // USUBO widening.
 TEST_F(AArch64GISelMITest, WidenUSUBO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_SUB).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenUSUBO) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // SADDO widening.
 TEST_F(AArch64GISelMITest, WidenSADDO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_ADD).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenSADDO) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // SSUBO widening.
 TEST_F(AArch64GISelMITest, WidenSSUBO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_SUB).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenSSUBO) {
   CHECK: G_TRUNC [[SUB]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenUADDE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_UADDE).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenUADDE) {
   CHECK: G_TRUNC [[UADDE]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenUSUBE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_USUBE).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenUSUBE) {
   CHECK: G_TRUNC [[USUBE]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenSADDE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SADDE, G_UADDE}).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenSADDE) {
   CHECK: G_TRUNC [[SADDE]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenSSUBE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SSUBE, G_USUBE}).legalFor({{s16, s16}});
   });
   // Build
TEST_F(AArch64GISelMITest, WidenSSUBE) {
   CHECK: G_TRUNC [[SSUBE]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowUADDO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_UADDO, G_UADDE})
TEST_F(AArch64GISelMITest, NarrowUADDO) {
   CHECK: [[UADDO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[UADDO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDO0]]:_(s32), [[UADDO1]]:_(s32), [[UADDO2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowUSUBO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_USUBO, G_USUBE})
TEST_F(AArch64GISelMITest, NarrowUSUBO) {
   CHECK: [[USUBO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_USUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[USUBO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[USUBO0]]:_(s32), [[USUBO1]]:_(s32), [[USUBO2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSADDO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_SADDE})
TEST_F(AArch64GISelMITest, NarrowSADDO) {
   CHECK: [[SADDO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[SADDO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SADDO0]]:_(s32), [[SADDO1]]:_(s32), [[SADDO2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSSUBO) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_USUBO, G_USUBE, G_SSUBE})
TEST_F(AArch64GISelMITest, NarrowSSUBO) {
   CHECK: [[SSUBO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SSUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[SSUBO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SSUBO0]]:_(s32), [[SSUBO1]]:_(s32), [[SSUBO2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowUADDE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_UADDE).legalFor(
TEST_F(AArch64GISelMITest, NarrowUADDE) {
   CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[UADDE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDE0]]:_(s32), [[UADDE1]]:_(s32), [[UADDE2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowUSUBE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_USUBE).legalFor(
TEST_F(AArch64GISelMITest, NarrowUSUBE) {
   CHECK: [[USUBE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_USUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[USUBE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[USUBE0]]:_(s32), [[USUBE1]]:_(s32), [[USUBE2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSADDE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SADDE, G_UADDE})
TEST_F(AArch64GISelMITest, NarrowSADDE) {
   CHECK: [[SADDE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[SADDE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SADDE0]]:_(s32), [[SADDE1]]:_(s32), [[SADDE2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSSUBE) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT S96 = LLT::scalar(96);
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SSUBE, G_USUBE})
TEST_F(AArch64GISelMITest, NarrowSSUBE) {
   CHECK: [[SSUBE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SSUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
   CHECK: [[SSUBE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SSUBE0]]:_(s32), [[SSUBE1]]:_(s32), [[SSUBE2]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, FewerElementsAnd) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT V2S32 = LLT::vector(2, 32);
   const LLT V5S32 = LLT::vector(5, 32);
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
TEST_F(AArch64GISelMITest, FewerElementsAnd) {
   CHECK: [[VECTOR8:%[0-9]+]]:_(<5 x s32>), [[VECTOR9:%[0-9]+]]:_(<5 x s32>) = G_UNMERGE_VALUES [[VECTOR7]]:_(<10 x s32>)
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, MoreElementsAnd) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s32 = LLT::scalar(32);
   LLT v2s32 = LLT::vector(2, 32);
   LLT v6s32 = LLT::vector(6, 32);
 
   LegalizerInfo LI;
TEST_F(AArch64GISelMITest, MoreElementsAnd) {
   CHECK: [[AND:%[0-9]+]]:_(<6 x s32>) = G_AND [[CONCAT0]]:_, [[CONCAT1]]:_
   CHECK: (<2 x s32>) = G_UNMERGE_VALUES [[AND]]:_(<6 x s32>)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, FewerElementsPhi) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s1 = LLT::scalar(1);
   LLT s32 = LLT::scalar(32);
   LLT s64 = LLT::scalar(64);
   LLT v2s32 = LLT::vector(2, 32);
   LLT v5s32 = LLT::vector(5, 32);
TEST_F(AArch64GISelMITest, FewerElementsPhi) {
   CHECK: [[USE_OP:%[0-9]+]]:_(<5 x s32>) = G_AND [[INSERT2]]:_, [[INSERT2]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // FNEG expansion in terms of XOR
 TEST_F(AArch64GISelMITest, LowerFNEG) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FSUB).legalFor({s64});
   });
 
TEST_F(AArch64GISelMITest, LowerFNEG) {
   CHECK: [[FSUB1:%[0-9]+]]:_(s64) = G_XOR %0:_, [[CONST1]]:_
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LowerMinMax) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   LLT v2s32 = LLT::vector(2, 32);
 
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
TEST_F(AArch64GISelMITest, LowerMinMax) {
   CHECK: [[VCMP3:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ugt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
   CHECK: [[UMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP3]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenScalarBuildVector) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   LLT S16 = LLT::scalar(16);
   LLT V2S16 = LLT::vector(2, S16);
   LLT V2S32 = LLT::vector(2, S32);
 
TEST_F(AArch64GISelMITest, WidenScalarBuildVector) {
 
   CHECK-NEXT: [[BV1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[EXT_K0_1]]:_(s32), [[EXT_K1_1]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LowerMergeValues) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT S32 = LLT::scalar(32);
   const LLT S24 = LLT::scalar(24);
   const LLT S21 = LLT::scalar(21);
   const LLT S16 = LLT::scalar(16);
   const LLT S9 = LLT::scalar(9);
TEST_F(AArch64GISelMITest, LowerMergeValues) {
   [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT_K16]]:_, [[SHL]]:_
   (s16) = G_TRUNC [[OR]]:_(s32)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenScalarMergeValuesPointer) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, Info, Observer, B);
TEST_F(AArch64GISelMITest, WidenScalarMergeValuesPointer) {
    CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT_TRUNC0]]:_, [[SHL]]
    CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]]:_(s64)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, WidenSEXTINREG) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_SEXT_INREG).legalForTypeWithAnyImm({s64});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, WidenSEXTINREG) {
   CHECK: [[T3:%[0-9]+]]:_(s32) = G_TRUNC [[T2]]:_(s64)
   )";
 
   // Check
   ASSERT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSEXTINREG) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info, these aren't actually relevant to the test.
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_SEXT_INREG).legalForTypeWithAnyImm({s64});
   });
   // Build Instr
TEST_F(AArch64GISelMITest, NarrowSEXTINREG) {
   CHECK: [[T3:%[0-9]+]]:_(s16) = G_SEXT [[T2]]:_(s10)
   )";
 
   // Check
   ASSERT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowSEXTINREG2) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info, these aren't actually relevant to the test.
   DefineLegalizerInfo(
       A, { getActionDefinitionsBuilder(G_SEXT_INREG).legalForTypeWithAnyImm({s64}); });
   // Build Instr
   auto MIB = B.buildInstr(
TEST_F(AArch64GISelMITest, NarrowSEXTINREG2) {
   CHECK: [[T7:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[T1]]:_(s8), [[T5]]:_(s8), [[T6]]:_(s8), [[T6]]:_(s8)
   )";
 
   // Check
   ASSERT_TRUE(CheckMachineFunction(*MF, CheckStr));
 }
 
 TEST_F(AArch64GISelMITest, LowerSEXTINREG) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info, these aren't actually relevant to the test.
   DefineLegalizerInfo(
       A, { getActionDefinitionsBuilder(G_SEXT_INREG).legalForTypeWithAnyImm({s64}); });
   // Build Instr
   auto MIB = B.buildInstr(
TEST_F(AArch64GISelMITest, LowerSEXTINREG) {
   CHECK: [[T3:%[0-9]+]]:_(s32) = G_ASHR [[T2]]:_, [[CST]]:_
   )";
 
   // Check
   ASSERT_TRUE(CheckMachineFunction(*MF, CheckStr));
 }
 
 TEST_F(AArch64GISelMITest, LibcallFPExt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s32, s16}, {s128, s64}});
   });
 
TEST_F(AArch64GISelMITest, LibcallFPExt) {
   CHECK: BL &__extenddftf2
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFPTrunc) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s16, s32}, {s64, s128}});
   });
 
TEST_F(AArch64GISelMITest, LibcallFPTrunc) {
   CHECK: BL &__trunctfdf2
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallSimple) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FADD).libcallFor({s16});
   });
 
   LLT S16{LLT::scalar(16)};
   auto MIBTrunc = B.buildTrunc(S16, Copies[0]);
   auto MIBFADD =
       B.buildInstr(TargetOpcode::G_FADD, {S16}, {MIBTrunc, MIBTrunc});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, Info, Observer, B);
   // Make sure we do not crash anymore
   EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
             Helper.libcall(*MIBFADD));
 }
 
 TEST_F(AArch64GISelMITest, LibcallSRem) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_SREM).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallSRem) {
   CHECK: BL &__modti3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallURem) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_UREM).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallURem) {
   CHECK: BL &__umodti3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
         .libcallFor({{s32, s32}, {s64, s64}, {s128, s128}});
   });
TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
   CHECK: BL &__clzti2
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFAdd) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FADD).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFAdd) {
   CHECK: BL &__addtf3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFSub) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FSUB).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFSub) {
   CHECK: BL &__subtf3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFMul) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FMUL).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFMul) {
   CHECK: BL &__multf3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFDiv) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FDIV).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFDiv) {
   CHECK: BL &__divtf3
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFExp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FEXP).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFExp) {
   CHECK: BL &expl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFExp2) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FEXP2).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFExp2) {
   CHECK: BL &exp2l
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFRem) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFRem) {
   CHECK: BL &fmodl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFPow) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FPOW).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFPow) {
   CHECK: BL &powl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFMa) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFMa) {
   CHECK: BL &fmal
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFCeil) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FCEIL).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFCeil) {
   CHECK: BL &ceill
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFFloor) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FFLOOR).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFFloor) {
   CHECK: BL &floorl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFMinNum) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FMINNUM).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFMinNum) {
   CHECK: BL &fminl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFMaxNum) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FMAXNUM).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFMaxNum) {
   CHECK: BL &fmaxl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFSqrt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FSQRT).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFSqrt) {
   CHECK: BL &sqrtl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFRint) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FRINT).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFRint) {
   CHECK: BL &rintl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LibcallFNearbyInt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_FNEARBYINT).libcallFor({s32, s64, s128});
   });
 
TEST_F(AArch64GISelMITest, LibcallFNearbyInt) {
   CHECK: BL &nearbyintl
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, NarrowScalarExtract) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
     getActionDefinitionsBuilder(G_EXTRACT).legalForTypeWithAnyImm({{s16, s32}});
   });
TEST_F(AArch64GISelMITest, NarrowScalarExtract) {
   CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY [[EXTR]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, LowerInsert) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_INSERT).lower(); });
 
   LLT S32{LLT::scalar(32)};
   LLT S64{LLT::scalar(64)};
TEST_F(AArch64GISelMITest, LowerInsert) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test lowering of G_FFLOOR
 TEST_F(AArch64GISelMITest, LowerFFloor) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {});
   // Build Instr
   auto Floor = B.buildFFloor(LLT::scalar(64), Copies[0], MachineInstr::MIFlag::FmNoInfs);
   AInfo Info(MF->getSubtarget());
TEST_F(AArch64GISelMITest, LowerFFloor) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test lowering of G_BSWAP
 TEST_F(AArch64GISelMITest, LowerBSWAP) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure vector lowering doesn't assert.
   auto Cast = B.buildBitcast(LLT::vector(2, 32), Copies[0]);
   auto BSwap = B.buildBSwap(LLT::vector(2, 32), Cast);
TEST_F(AArch64GISelMITest, LowerBSWAP) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test lowering of G_SDIVREM into G_SDIV and G_SREM
 TEST_F(AArch64GISelMITest, LowerSDIVREM) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(
       A, { getActionDefinitionsBuilder(G_SDIVREM).lowerFor({s64}); });
 
   LLT S64{LLT::scalar(64)};
TEST_F(AArch64GISelMITest, LowerSDIVREM) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test lowering of G_UDIVREM into G_UDIV and G_UREM
 TEST_F(AArch64GISelMITest, LowerUDIVREM) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(
       A, { getActionDefinitionsBuilder(G_UDIVREM).lowerFor({s64}); });
 
   LLT S64{LLT::scalar(64)};
TEST_F(AArch64GISelMITest, LowerUDIVREM) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test widening of G_UNMERGE_VALUES
 TEST_F(AArch64GISelMITest, WidenUnmerge) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Check that widening G_UNMERGE_VALUES to a larger type than the source type
   // works as expected
   LLT P0{LLT::pointer(0, 64)};
TEST_F(AArch64GISelMITest, WidenUnmerge) {
   CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BitcastLoad) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT P0 = LLT::pointer(0, 64);
   LLT S32 = LLT::scalar(32);
   LLT V4S8 = LLT::vector(4, 8);
   auto Ptr = B.buildUndef(P0);
 
TEST_F(AArch64GISelMITest, BitcastLoad) {
 
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BitcastStore) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT P0 = LLT::pointer(0, 64);
   LLT S32 = LLT::scalar(32);
   LLT V4S8 = LLT::vector(4, 8);
   auto Ptr = B.buildUndef(P0);
 
TEST_F(AArch64GISelMITest, BitcastStore) {
   CHECK: G_STORE [[CAST]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BitcastSelect) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
   LLT V4S8 = LLT::vector(4, 8);
 
   DefineLegalizerInfo(A, {});
TEST_F(AArch64GISelMITest, BitcastSelect) {
   B.setInsertPt(*EntryMBB, VSelect->getIterator());
   EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
             Helper.bitcast(*VSelect, 0, S32));
   EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
             Helper.bitcast(*VSelect, 1, LLT::scalar(4)));
 }
 
 TEST_F(AArch64GISelMITest, BitcastBitOps) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   LLT V4S8 = LLT::vector(4, 8);
 
   DefineLegalizerInfo(A, {});
 
TEST_F(AArch64GISelMITest, BitcastBitOps) {
   CHECK: [[CAST_XOR:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[XOR]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, CreateLibcall) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
 
TEST_F(AArch64GISelMITest, CreateLibcall) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test narrowing of G_IMPLICIT_DEF
 TEST_F(AArch64GISelMITest, NarrowImplicitDef) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_IMPLICIT_DEF can be narrowed if the original size is not a
   // multiple of narrow size
   LLT S32{LLT::scalar(32)};
TEST_F(AArch64GISelMITest, NarrowImplicitDef) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test widening of G_FREEZE
 TEST_F(AArch64GISelMITest, WidenFreeze) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_FREEZE is widened with anyext
   LLT S64{LLT::scalar(64)};
   LLT S128{LLT::scalar(128)};
TEST_F(AArch64GISelMITest, WidenFreeze) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test narrowing of G_FREEZE
 TEST_F(AArch64GISelMITest, NarrowFreeze) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_FREEZE is narrowed using unmerge/extract
   LLT S16{LLT::scalar(16)};
   LLT S32{LLT::scalar(32)};
TEST_F(AArch64GISelMITest, NarrowFreeze) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test fewer elements of G_FREEZE
 TEST_F(AArch64GISelMITest, FewerElementsFreeze) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT S32{LLT::scalar(32)};
   LLT V2S16{LLT::vector(2, 16)};
   LLT V2S32{LLT::vector(2, 32)};
TEST_F(AArch64GISelMITest, FewerElementsFreeze) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test more elements of G_FREEZE
 TEST_F(AArch64GISelMITest, MoreElementsFreeze) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT V2S32{LLT::vector(2, 32)};
   LLT V4S32{LLT::vector(4, 32)};
 
TEST_F(AArch64GISelMITest, MoreElementsFreeze) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test fewer elements of G_INSERT_VECTOR_ELEMENT
 TEST_F(AArch64GISelMITest, FewerElementsInsertVectorElt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT P0{LLT::pointer(0, 64)};
   LLT S64{LLT::scalar(64)};
   LLT S16{LLT::scalar(16)};
TEST_F(AArch64GISelMITest, FewerElementsInsertVectorElt) {
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 // Test widen scalar of G_UNMERGE_VALUES
 TEST_F(AArch64GISelMITest, widenScalarUnmerge) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT S96{LLT::scalar(96)};
   LLT S64{LLT::scalar(64)};
   LLT S48{LLT::scalar(48)};

llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp

 })
 
 TEST_F(AArch64GISelMITest, BasicLegalizerTest) {
   StringRef MIRString = R"(
     %vptr:_(p0) = COPY $x4
     %v:_(<2 x s8>) = G_LOAD %vptr:_(p0) :: (load 2, align 1)
     $h4 = COPY %v:_(<2 x s8>)
   )";
-  setUp(MIRString.rtrim(' '));
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString.rtrim(' '));
   if (!TM)
     return;
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
 
   Legalizer::MFResult Result = Legalizer::legalizeMachineFunction(
       *MF, LI, {&LocObserver}, LocObserver, B);

 TEST_F(AArch64GISelMITest, UnorderedArtifactCombiningTest) {
   StringRef MIRString = R"(
     %vptr:_(p0) = COPY $x4
     %v:_(<2 x s8>) = G_LOAD %vptr:_(p0) :: (load 2, align 1)
     %v0:_(s8), %v1:_(s8) = G_UNMERGE_VALUES %v:_(<2 x s8>)
     %v0_ext:_(s16) = G_ANYEXT %v0:_(s8)
     $h4 = COPY %v0_ext:_(s16)
   )";
-  setUp(MIRString.rtrim(' '));
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString.rtrim(' '));
   if (!TM)
     return;
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
 
   // The events here unfold as follows:
   // 1. First, the function is scanned pre-forming the worklist of artifacts:
StringRef MIRString = R"(
     %v0:_(s8) = COPY %v0t:_(s8)
     %v1t:_(s8) = COPY %vc11:_(s8)
     %v1:_(s8) = COPY %v1t:_(s8)
     %v0_zext:_(s32) = G_ZEXT %v0:_(s8)
     %v1_sext:_(s32) = G_SEXT %v1:_(s8)
     $w4 = COPY %v0_zext:_(s32)
     $w5 = COPY %v1_sext:_(s32)
   )";
-  setUp(MIRString.rtrim(' '));
+  LLVMTargetMachine *TM = createTargetMachineAndModule(MIRString.rtrim(' '));
   if (!TM)
     return;
 
   ALegalizerInfo LI(MF->getSubtarget());
   LostDebugLocObserver LocObserver(DEBUG_TYPE);
 
   Legalizer::MFResult Result = Legalizer::legalizeMachineFunction(
       *MF, LI, {&LocObserver}, LocObserver, B);

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

 //===- MachineIRBuilderTest.cpp -------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "GISelMITest.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 
 TEST_F(AArch64GISelMITest, TestBuildConstantFConstant) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   B.buildConstant(LLT::scalar(32), 42);
   B.buildFConstant(LLT::scalar(32), 1.0);
 
   B.buildConstant(LLT::vector(2, 32), 99);
   B.buildFConstant(LLT::vector(2, 32), 2.0);
TEST_F(AArch64GISelMITest, TestBuildConstantFConstant) {
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 #ifdef GTEST_HAS_DEATH_TEST
 #ifndef NDEBUG
 
 TEST_F(AArch64GISelMITest, TestBuildConstantFConstantDeath) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLVMContext &Ctx = MF->getFunction().getContext();
   APInt APV32(32, 12345);
 
   // Test APInt version breaks
   EXPECT_DEATH(B.buildConstant(LLT::scalar(16), APV32),
TEST_F(AArch64GISelMITest, TestBuildConstantFConstantDeath) {
   EXPECT_DEATH(B.buildFConstant(LLT::vector(2, 16), *CF),
                "creating fconstant with the wrong size");
 }
 
 #endif
 #endif
 
 TEST_F(AArch64GISelMITest, DstOpSrcOp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   LLT s64 = LLT::scalar(64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
TEST_F(AArch64GISelMITest, DstOpSrcOp) {
   ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY0]]:_, [[COPY1]]:_
   ; CHECK: [[ADD]]:_(s64) = G_ADD [[COPY0]]:_, [[COPY1]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildUnmerge) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
   B.buildUnmerge(LLT::scalar(32), Copies[0]);
   B.buildUnmerge(LLT::scalar(16), Copies[1]);
 
   auto CheckStr = R"(
   ; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
   ; CHECK: [[UNMERGE32_0:%[0-9]+]]:_(s32), [[UNMERGE32_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY0]]
   ; CHECK: [[UNMERGE16_0:%[0-9]+]]:_(s16), [[UNMERGE16_1:%[0-9]+]]:_(s16), [[UNMERGE16_2:%[0-9]+]]:_(s16), [[UNMERGE16_3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]]
 
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, TestBuildFPInsts) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   LLT S64 = LLT::scalar(64);
 
TEST_F(AArch64GISelMITest, TestBuildFPInsts) {
   ; CHECK: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY0]]:_
   ; CHECK: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY0]]:_, [[COPY1]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildIntrinsic) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S64 = LLT::scalar(64);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   // Make sure DstOp version works. sqrt is just a placeholder intrinsic.
TEST_F(AArch64GISelMITest, BuildIntrinsic) {
   ; CHECK: [[SQRT0:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.sqrt), [[COPY0]]:_
   ; CHECK: [[SQRT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.sqrt), [[COPY1]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildXor) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S64 = LLT::scalar(64);
   LLT S128 = LLT::scalar(128);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
   B.buildXor(S64, Copies[0], Copies[1]);
TEST_F(AArch64GISelMITest, BuildXor) {
   ; CHECK: [[NEGONE128:%[0-9]+]]:_(s128) = G_CONSTANT i128 -1
   ; CHECK: [[XOR2:%[0-9]+]]:_(s128) = G_XOR [[MERGE]]:_, [[NEGONE128]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildBitCounts) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   B.buildCTPOP(S32, Copies[0]);
TEST_F(AArch64GISelMITest, BuildBitCounts) {
   ; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY0]]:_
   ; CHECK: [[CTTZ_UNDEF0:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildCasts) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   B.buildUITOFP(S32, Copies[0]);
   B.buildSITOFP(S32, Copies[0]);
   B.buildFPTOUI(S32, Copies[0]);
   B.buildFPTOSI(S32, Copies[0]);
 
   auto CheckStr = R"(
   ; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY0]]:_
   ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY0]]:_
   ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY0]]:_
   ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY0]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildMinMaxAbs) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S64 = LLT::scalar(64);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   B.buildSMin(S64, Copies[0], Copies[1]);
TEST_F(AArch64GISelMITest, BuildMinMaxAbs) {
   ; CHECK: [[UMAX0:%[0-9]+]]:_(s64) = G_UMAX [[COPY0]]:_, [[COPY1]]:_
   ; CHECK: [[UABS0:%[0-9]+]]:_(s64) = G_ABS [[COPY0]]:_
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildAtomicRMW) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S64 = LLT::scalar(64);
   LLT P0 = LLT::pointer(0, 64);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
TEST_F(AArch64GISelMITest, BuildAtomicRMW) {
   ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_FADD [[PTR]]:_(p0), [[COPY0]]:_ :: (load store unordered 8)
   ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_ATOMICRMW_FSUB [[PTR]]:_(p0), [[COPY0]]:_ :: (load store unordered 8)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildMerge) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   Register RegC0 = B.buildConstant(S32, 0).getReg(0);
   Register RegC1 = B.buildConstant(S32, 1).getReg(0);
   Register RegC2 = B.buildConstant(S32, 2).getReg(0);
   Register RegC3 = B.buildConstant(S32, 3).getReg(0);
TEST_F(AArch64GISelMITest, BuildMerge) {
   ; CHECK: [[HIGH2x32:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]]:_(s32), [[C3]]:_(s32)
   ; CHECK: {{%[0-9]+}}:_(<4 x s32>) = G_CONCAT_VECTORS [[LOW2x32]]:_(<2 x s32>), [[HIGH2x32]]:_(<2 x s32>)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildAddoSubo) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S64 = LLT::scalar(64);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
TEST_F(AArch64GISelMITest, BuildAddoSubo) {
   ; CHECK: [[SADDE:%[0-9]+]]:_(s64), [[SADDE_FLAG:%[0-9]+]]:_(s1) = G_SADDE [[COPY0]]:_, [[COPY1]]:_, [[SADDO_FLAG]]
   ; CHECK: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE_FLAG:%[0-9]+]]:_(s1) = G_SSUBE [[COPY0]]:_, [[COPY1]]:_, [[SSUBO_FLAG]]
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, BuildBitfieldExtract) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   LLT S64 = LLT::scalar(64);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
 
   auto Ubfx = B.buildUbfx(S64, Copies[0], Copies[1], Copies[2]);
   B.buildSbfx(S64, Ubfx, Copies[0], Copies[2]);

llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

 #include "gtest/gtest.h"
 
 using namespace llvm;
 using namespace MIPatternMatch;
 
 namespace {
 
 TEST_F(AArch64GISelMITest, MatchIntConstant) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
   int64_t Cst;
   bool match = mi_match(MIBCst.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 42);
 }
 
 TEST_F(AArch64GISelMITest, MatchBinaryOp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   LLT s32 = LLT::scalar(32);
   LLT s64 = LLT::scalar(64);
   LLT p0 = LLT::pointer(0, 64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   // Test case for no bind.
   bool match =
TEST_F(AArch64GISelMITest, MatchBinaryOp) {
   auto PtrAdd = B.buildPtrAdd(p0, {B.buildUndef(p0)}, Copies[0]);
   match = mi_match(PtrAdd.getReg(0), *MRI, m_GPtrAdd(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, PtrAdd->getOperand(1).getReg());
   EXPECT_EQ(Src1, Copies[0]);
 }
 
 TEST_F(AArch64GISelMITest, MatchICmp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT s1 = LLT::scalar(1);
   auto CmpEq = B.buildICmp(CmpInst::ICMP_EQ, s1, Copies[0], Copies[1]);
 
   // Check match any predicate.
   bool match =
       mi_match(CmpEq.getReg(0), *MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
   EXPECT_TRUE(match);
 
   // Check we get the predicate and registers.
   CmpInst::Predicate Pred;
   Register Reg0;
   Register Reg1;
   match = mi_match(CmpEq.getReg(0), *MRI,
                    m_GICmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(CmpInst::ICMP_EQ, Pred);
   EXPECT_EQ(Copies[0], Reg0);
   EXPECT_EQ(Copies[1], Reg1);
 }
 
 TEST_F(AArch64GISelMITest, MatchFCmp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   const LLT s1 = LLT::scalar(1);
   auto CmpEq = B.buildFCmp(CmpInst::FCMP_OEQ, s1, Copies[0], Copies[1]);
 
   // Check match any predicate.
   bool match =
       mi_match(CmpEq.getReg(0), *MRI, m_GFCmp(m_Pred(), m_Reg(), m_Reg()));
   EXPECT_TRUE(match);
 
   // Check we get the predicate and registers.
   CmpInst::Predicate Pred;
   Register Reg0;
   Register Reg1;
   match = mi_match(CmpEq.getReg(0), *MRI,
                    m_GFCmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(CmpInst::FCMP_OEQ, Pred);
   EXPECT_EQ(Copies[0], Reg0);
   EXPECT_EQ(Copies[1], Reg1);
 }
 
 TEST_F(AArch64GISelMITest, MatchFPUnaryOp) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Truncate s64 to s32.
   LLT s32 = LLT::scalar(32);
   auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]);
 
   // Match G_FABS.
TEST_F(AArch64GISelMITest, MatchFPUnaryOp) {
   APFloat APF16(.5);
   APF16.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
   auto CFP16 = ConstantFP::get(Context, APF16);
   EXPECT_EQ(TmpFP16, CFP16);
   EXPECT_NE(TmpFP16, TmpFP);
 }
 
 TEST_F(AArch64GISelMITest, MatchExtendsTrunc) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
 
   auto MIBTrunc = B.buildTrunc(s32, Copies[0]);
   auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
TEST_F(AArch64GISelMITest, MatchExtendsTrunc) {
 
   match = mi_match(MIBZExt.getReg(0), *MRI,
                    m_GZExt(m_GTrunc(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 }
 
 TEST_F(AArch64GISelMITest, MatchSpecificType) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Try to match a 64bit add.
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   EXPECT_FALSE(mi_match(MIBAdd.getReg(0), *MRI,
TEST_F(AArch64GISelMITest, MatchSpecificType) {
   // match the ptrtoint(inttoptr reg)
   bool match = mi_match(MIBPtrToInt.getReg(0), *MRI,
                         m_GPtrToInt(m_GIntToPtr(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 }
 
 TEST_F(AArch64GISelMITest, MatchCombinators) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   Register Src0, Src1;
   bool match =
TEST_F(AArch64GISelMITest, MatchCombinators) {
   // Match a case where none of the predicates hold true.
   match = mi_match(
       MIBAdd.getReg(0), *MRI,
       m_any_of(m_SpecificType(LLT::scalar(16)), m_GSub(m_Reg(), m_Reg())));
   EXPECT_FALSE(match);
 }
 
 TEST_F(AArch64GISelMITest, MatchMiscellaneous) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   Register Reg = MIBAdd.getReg(0);
 
   // Only one use of Reg.
TEST_F(AArch64GISelMITest, MatchMiscellaneous) {
 
   // Multiple non-debug uses of Reg.
   B.buildCast(LLT::pointer(1, 32), MIBAdd);
   EXPECT_FALSE(mi_match(Reg, *MRI, m_OneUse(m_GAdd(m_Reg(), m_Reg()))));
   EXPECT_FALSE(mi_match(Reg, *MRI, m_OneNonDBGUse(m_GAdd(m_Reg(), m_Reg()))));
 }
 
 TEST_F(AArch64GISelMITest, MatchSpecificConstant) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   // Basic case: Can we match a G_CONSTANT with a specific value?
   auto FortyTwo = B.buildConstant(LLT::scalar(64), 42);
   EXPECT_TRUE(mi_match(FortyTwo.getReg(0), *MRI, m_SpecificICst(42)));
   EXPECT_FALSE(mi_match(FortyTwo.getReg(0), *MRI, m_SpecificICst(123)));
 
   // Test that this works inside of a more complex pattern.
   LLT s64 = LLT::scalar(64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], FortyTwo);
   EXPECT_TRUE(mi_match(MIBAdd.getReg(2), *MRI, m_SpecificICst(42)));
 
   // Wrong constant.
   EXPECT_FALSE(mi_match(MIBAdd.getReg(2), *MRI, m_SpecificICst(123)));
 
   // No constant on the LHS.
   EXPECT_FALSE(mi_match(MIBAdd.getReg(1), *MRI, m_SpecificICst(42)));
 }
 
 TEST_F(AArch64GISelMITest, MatchZeroInt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   auto Zero = B.buildConstant(LLT::scalar(64), 0);
   EXPECT_TRUE(mi_match(Zero.getReg(0), *MRI, m_ZeroInt()));
 
   auto FortyTwo = B.buildConstant(LLT::scalar(64), 42);
   EXPECT_FALSE(mi_match(FortyTwo.getReg(0), *MRI, m_ZeroInt()));
 }
 
 TEST_F(AArch64GISelMITest, MatchAllOnesInt) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
   auto AllOnes = B.buildConstant(LLT::scalar(64), -1);
   EXPECT_TRUE(mi_match(AllOnes.getReg(0), *MRI, m_AllOnesInt()));
 
   auto FortyTwo = B.buildConstant(LLT::scalar(64), 42);
   EXPECT_FALSE(mi_match(FortyTwo.getReg(0), *MRI, m_AllOnesInt()));
 }
 
 TEST_F(AArch64GISelMITest, MatchNeg) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   auto Zero = B.buildConstant(LLT::scalar(64), 0);
   auto NegInst = B.buildSub(s64, Zero, Copies[0]);
   Register NegatedReg;
 
TEST_F(AArch64GISelMITest, MatchNeg) {
   // %add = G_ADD = %x, %sub
   auto AddInst = B.buildAdd(s64, Copies[1], NegInst);
   NegatedReg = Register();
   EXPECT_TRUE(mi_match(AddInst.getReg(2), *MRI, m_Neg(m_Reg(NegatedReg))));
   EXPECT_EQ(NegatedReg, Copies[0]);
 }
 
 TEST_F(AArch64GISelMITest, MatchNot) {
-  setUp();
+  LLVMTargetMachine *TM = createTargetMachineAndModule();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   auto AllOnes = B.buildConstant(LLT::scalar(64), -1);
   auto NotInst1 = B.buildXor(s64, Copies[0], AllOnes);
   Register NotReg;