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[AVR] Fix a bug in prologue of ISR
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Authored by benshi001 on Mar 28 2021, 8:00 AM.

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Summary

The r1 register should be cleared in prologue of ISR as it is used
as constant zero.

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Event Timeline

benshi001 created this revision.Mar 28 2021, 8:00 AM
benshi001 requested review of this revision.Mar 28 2021, 8:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2021, 8:00 AM

avr-gcc does

  1. use r0 as tmp_reg to save/restore SREG
  2. clear r1 and then use it as zero_reg

but llvm clears r0 instead of expected r1.

benshi001 updated this revision to Diff 354915.Jun 28 2021, 8:46 AM
benshi001 edited the summary of this revision. (Show Details)Jun 28 2021, 8:49 AM
dylanmckay accepted this revision.Jun 29 2021, 6:38 AM
This revision is now accepted and ready to land.Jun 29 2021, 6:38 AM
This revision was automatically updated to reflect the committed changes.