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Differential D99467

[AVR] Fix a bug in prologue of ISR
ClosedPublic

Authored by benshi001 on Mar 28 2021, 8:00 AM.

Details

Reviewers
aykevl
dylanmckay
Commits
rGc85175c5f6a9: [AVR] Fix a bug in prologue of ISR
Summary

The r1 register should be cleared in prologue of ISR as it is used
as constant zero.

Diff Detail

Event Timeline

benshi001 created this revision.Mar 28 2021, 8:00 AM
Herald added subscribers: Jim, hiraditya. · View Herald TranscriptMar 28 2021, 8:00 AM
benshi001 requested review of this revision.Mar 28 2021, 8:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2021, 8:00 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
benshi001 added a comment.Mar 28 2021, 8:02 AM

avr-gcc does

  1. use r0 as tmp_reg to save/restore SREG
  2. clear r1 and then use it as zero_reg

but llvm clears r0 instead of expected r1.

Harbormaster completed remote builds in B96004: Diff 333724.Mar 28 2021, 8:40 AM
benshi001 updated this revision to Diff 354915.Jun 28 2021, 8:46 AM
benshi001 edited the summary of this revision. (Show Details)Jun 28 2021, 8:49 AM
Harbormaster completed remote builds in B111303: Diff 354915.Jun 28 2021, 9:23 AM
dylanmckay accepted this revision.Jun 29 2021, 6:38 AM
This revision is now accepted and ready to land.Jun 29 2021, 6:38 AM
Closed by commit rGc85175c5f6a9: [AVR] Fix a bug in prologue of ISR (authored by benshi001). · Explain WhyJun 29 2021, 6:44 AM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGc85175c5f6a9: [AVR] Fix a bug in prologue of ISR.
aykevl mentioned this in D116756: [AVR] Do not clear r0 at interrupt entry.Jan 6 2022, 9:29 AM
aykevl mentioned this in rGca27b026f990: [AVR] Do not clear r0 at interrupt entry.Jan 19 2022, 5:23 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AVR/
5 lines
test/
CodeGen/
AVR/
5 lines

Diff 355218

llvm/lib/Target/AVR/AVRFrameLowering.cpp

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines if (AFI->isInterruptOrSignalHandler()) {
BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
.addReg(AVR::R0, RegState::Kill) .addReg(AVR::R0, RegState::Kill)
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
.addReg(AVR::R0, RegState::Define) .addReg(AVR::R0, RegState::Define)
.addReg(AVR::R0, RegState::Kill) .addReg(AVR::R0, RegState::Kill)
.addReg(AVR::R0, RegState::Kill) .addReg(AVR::R0, RegState::Kill)
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
.addReg(AVR::R1, RegState::Define)
.addReg(AVR::R1, RegState::Kill)
.addReg(AVR::R1, RegState::Kill)
.setMIFlag(MachineInstr::FrameSetup);
} }
// Early exit if the frame pointer is not needed in this function. // Early exit if the frame pointer is not needed in this function.
if (!HasFP) { if (!HasFP) {
return; return;
} }
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
▲ Show 20 Lines • Show All 441 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/interrupts.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
define avr_intrcc void @interrupt_handler() { define avr_intrcc void @interrupt_handler() {
; CHECK-LABEL: interrupt_handler: ; CHECK-LABEL: interrupt_handler:
; CHECK: sei ; CHECK: sei
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK: clr r0 ; CHECK: clr r0
; CHECK-NEXT: clr r1
; CHECK: pop r0 ; CHECK: pop r0
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1 ; CHECK-NEXT: pop r1
; CHECK-NEXT: pop r0 ; CHECK-NEXT: pop r0
; CHECK-NEXT: reti ; CHECK-NEXT: reti
ret void ret void
} }
define void @interrupt_handler_via_ir_attribute() #0 { define void @interrupt_handler_via_ir_attribute() #0 {
; CHECK-LABEL: interrupt_handler_via_ir_attribute: ; CHECK-LABEL: interrupt_handler_via_ir_attribute:
; CHECK: sei ; CHECK: sei
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK: clr r0 ; CHECK: clr r0
; CHECK-NEXT: clr r1
; CHECK: pop r0 ; CHECK: pop r0
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1 ; CHECK-NEXT: pop r1
; CHECK-NEXT: pop r0 ; CHECK-NEXT: pop r0
; CHECK-NEXT: reti ; CHECK-NEXT: reti
ret void ret void
} }
define avr_signalcc void @signal_handler() { define avr_signalcc void @signal_handler() {
; CHECK-LABEL: signal_handler: ; CHECK-LABEL: signal_handler:
; CHECK-NOT: sei ; CHECK-NOT: sei
; CHECK: push r0 ; CHECK: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK: clr r0 ; CHECK: clr r0
; CHECK-NEXT: clr r1
; CHECK: pop r0 ; CHECK: pop r0
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1 ; CHECK-NEXT: pop r1
; CHECK-NEXT: pop r0 ; CHECK-NEXT: pop r0
; CHECK-NEXT: reti ; CHECK-NEXT: reti
ret void ret void
} }
define void @signal_handler_via_attribute() #1 { define void @signal_handler_via_attribute() #1 {
; CHECK-LABEL: signal_handler_via_attribute: ; CHECK-LABEL: signal_handler_via_attribute:
; CHECK-NOT: sei ; CHECK-NOT: sei
; CHECK: push r0 ; CHECK: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK: clr r0 ; CHECK: clr r0
; CHECK-NEXT: clr r1
; CHECK: pop r0 ; CHECK: pop r0
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1 ; CHECK-NEXT: pop r1
; CHECK-NEXT: pop r0 ; CHECK-NEXT: pop r0
; CHECK-NEXT: reti ; CHECK-NEXT: reti
ret void ret void
} }
define avr_intrcc void @interrupt_alloca() { define avr_intrcc void @interrupt_alloca() {
; CHECK-LABEL: interrupt_alloca: ; CHECK-LABEL: interrupt_alloca:
; CHECK: sei ; CHECK: sei
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK: clr r0 ; CHECK: clr r0
; CHECK-NEXT: clr r1
; CHECK: push r28 ; CHECK: push r28
; CHECK-NEXT: push r29 ; CHECK-NEXT: push r29
; CHECK-NEXT: in r28, 61 ; CHECK-NEXT: in r28, 61
; CHECK-NEXT: in r29, 62 ; CHECK-NEXT: in r29, 62
; CHECK-NEXT: sbiw r28, 1 ; CHECK-NEXT: sbiw r28, 1
; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: out 62, r29 ; CHECK-NEXT: out 62, r29
Show All 21 Lines