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Differential D98685

[X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention
ClosedPublic

Authored by yubing on Mar 16 2021, 1:12 AM.

Details

Reviewers
LuoYuanke
LiuChen3
pengfei
craig.topper
Commits
rG320b72e9cd77: [X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention
Summary

tile_tdpbf16ps should be renamed with tile_dpbf16ps

Diff Detail

Event Timeline

yubing created this revision.Mar 16 2021, 1:12 AM
Herald added a subscriber: pengfei. · View Herald TranscriptMar 16 2021, 1:12 AM
yubing requested review of this revision.Mar 16 2021, 1:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 16 2021, 1:12 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
yubing retitled this revision from [X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention __tile_tdpbf16ps should be renamed with __tile_dpbf16ps to [X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention.Mar 16 2021, 1:13 AM
yubing edited the summary of this revision. (Show Details)
yubing added reviewers: LuoYuanke, LiuChen3, pengfei, craig.topper.
pengfei accepted this revision.Mar 16 2021, 1:22 AM

LGTM.

This revision is now accepted and ready to land.Mar 16 2021, 1:22 AM
Harbormaster completed remote builds in B93986: Diff 330896.Mar 16 2021, 1:46 AM
This revision was landed with ongoing or failed builds.Mar 16 2021, 8:23 PM
Closed by commit rG320b72e9cd77: [X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention (authored by yubing). · Explain Why
This revision was automatically updated to reflect the committed changes.
yubing added a commit: rG320b72e9cd77: [X86][AMX] Rename amx-bf16 intrinsic according to correct naming convention.

Revision Contents

PathSize
clang/
lib/
Headers/
12 lines
test/
CodeGen/
X86/
6 lines

Diff 331151

clang/lib/Headers/amxintrin.h

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
static __inline__ void __DEFAULT_FN_ATTRS_INT8 static __inline__ void __DEFAULT_FN_ATTRS_INT8
_tile_stored_internal(unsigned short m, unsigned short n, void *base, _tile_stored_internal(unsigned short m, unsigned short n, void *base,
__SIZE_TYPE__ stride, _tile1024i tile) { __SIZE_TYPE__ stride, _tile1024i tile) {
return __builtin_ia32_tilestored64_internal(m, n, base, return __builtin_ia32_tilestored64_internal(m, n, base,
(__SIZE_TYPE__)(stride), tile); (__SIZE_TYPE__)(stride), tile);
} }
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_BF16 static __inline__ _tile1024i __DEFAULT_FN_ATTRS_BF16
_tile_tdpbf16ps_internal(unsigned short m, unsigned short n, unsigned short k, _tile_dpbf16ps_internal(unsigned short m, unsigned short n, unsigned short k,
_tile1024i dst, _tile1024i src1, _tile1024i src2) { _tile1024i dst, _tile1024i src1, _tile1024i src2) {
return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2); return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2);
} }
typedef struct __tile1024i_str { typedef struct __tile1024i_str {
const unsigned short row; const unsigned short row;
const unsigned short col; const unsigned short col;
_tile1024i tile; _tile1024i tile;
} __tile1024i; } __tile1024i;
Show All 38 Lines
} }
__DEFAULT_FN_ATTRS_TILE __DEFAULT_FN_ATTRS_TILE
static void __tile_zero(__tile1024i *dst) { static void __tile_zero(__tile1024i *dst) {
dst->tile = __builtin_ia32_tilezero_internal(dst->row, dst->col); dst->tile = __builtin_ia32_tilezero_internal(dst->row, dst->col);
} }
__DEFAULT_FN_ATTRS_BF16 __DEFAULT_FN_ATTRS_BF16
static void __tile_tdpbf16ps(__tile1024i *dst, __tile1024i src1, static void __tile_dpbf16ps(__tile1024i *dst, __tile1024i src1,
__tile1024i src2) { __tile1024i src2) {
dst->tile = _tile_tdpbf16ps_internal(src1.row, src2.col, src1.col, dst->tile, dst->tile = _tile_dpbf16ps_internal(src1.row, src2.col, src1.col, dst->tile,
src1.tile, src2.tile); src1.tile, src2.tile);
} }
#undef __DEFAULT_FN_ATTRS_TILE #undef __DEFAULT_FN_ATTRS_TILE
#undef __DEFAULT_FN_ATTRS_INT8 #undef __DEFAULT_FN_ATTRS_INT8
#undef __DEFAULT_FN_ATTRS_BF16 #undef __DEFAULT_FN_ATTRS_BF16
#endif /* __x86_64__ */ #endif /* __x86_64__ */
#endif /* __AMXINTRIN_H */ #endif /* __AMXINTRIN_H */

clang/test/CodeGen/X86/amx_api.c

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
void test_tile_zero(__tile1024i c) { void test_tile_zero(__tile1024i c) {
//CHECK-LABEL: @test_tile_zero //CHECK-LABEL: @test_tile_zero
//CHECK: call x86_amx @llvm.x86.tilezero.internal //CHECK: call x86_amx @llvm.x86.tilezero.internal
//CHECK-NEXT bitcast x86_amx {{%.*}} to <256 x i32> //CHECK-NEXT bitcast x86_amx {{%.*}} to <256 x i32>
__tile_zero(&c); __tile_zero(&c);
} }
void test_tile_tdpbf16ps(__tile1024i a, __tile1024i b, __tile1024i c) { void test_tile_dpbf16ps(__tile1024i a, __tile1024i b, __tile1024i c) {
//CHECK-LABEL: @test_tile_tdpbf16ps //CHECK-LABEL: @test_tile_dpbf16ps
//CHECK: call x86_amx @llvm.x86.tdpbf16ps.internal //CHECK: call x86_amx @llvm.x86.tdpbf16ps.internal
//CHECK-NEXT: {{%.*}} = bitcast x86_amx {{%.*}} to <256 x i32> //CHECK-NEXT: {{%.*}} = bitcast x86_amx {{%.*}} to <256 x i32>
__tile_tdpbf16ps(&a, b, c); __tile_dpbf16ps(&a, b, c);
} }