[M68k] Tidy up some bit shifting during code emission

[ricky26]

Summary

This fixes some issues with bit masking when emitting instructions
(including one TODO).

[RKSimon]

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

183–184

1ULL << Size ?

315

Should this be 1ULL << Size? Otherwise some compilers will warn that that you're extending a 32-bit result to 64-bits.

[ricky26]

Fixed implicit 32-bit shifts (they are now explicitly 64-bits)

[RKSimon]

LGTM

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

 //===-- M68kMCCodeEmitter.cpp - Convert M68k code emitter ---*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file contains defintions for M68k code emitter.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/M68kBaseInfo.h"
 #include "MCTargetDesc/M68kFixupKinds.h"
 #include "MCTargetDesc/M68kMCTargetDesc.h"
 
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
   }
 
   unsigned RegNum = MCO.getReg();
   auto RI = Ctx.getRegisterInfo();
 
   unsigned Written = 0;
   if (Reg) {
     uint32_t Val = RI->getEncodingValue(RegNum);
-    Buffer |= Val << Offset;
+    Buffer |= (Val & 7) << Offset;
     Offset += 3;
     Written += 3;
   }
 
   if (DA) {
-    Buffer |= (char)M68kII::isAddressRegister(RegNum) << Offset;
+    Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
     Written++;
   }
 
   return Written;
 }
 
 static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad,
                              uint64_t &Buffer, unsigned Offset) {
   assert(Size + Offset <= 64 && isUIntN(Size, Val) && "Value does not fit");
 
-  // Pad the instruction with zeros if any
-  // FIXME Emit zeros in the padding, since there might be trash in the buffer.
-  Size += Pad;
-
   // Writing Value in host's endianness
-  Buffer |= Val << Offset;
-  return Size;
+  Buffer |= (Val & ((1ULL << Size) - 1)) << Offset;
+  return Size + Pad;
 }
 
 unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
                                       const MCInst &MI, const MCInstrDesc &Desc,
                                       uint64_t &Buffer, unsigned Offset,
                                       SmallVectorImpl<MCFixup> &Fixups,
                                       const MCSubtargetInfo &STI) const {
   unsigned ThisWord = ThisByte / 2;
unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
 
   // 32 bit Imm requires HI16 first then LO16
   if (Size == 32) {
     Offset += EmitConstant((Imm >> 16) & 0xFFFF, 16, Pad, Buffer, Offset);
     EmitConstant(Imm & 0xFFFF, 16, Pad, Buffer, Offset);
     return Size;
   }
 
-  return EmitConstant(Imm & (UINT64_MAX >> (64 - Size)), Size, Pad, Buffer,
-                      Offset);
+  return EmitConstant(Imm & ((1ULL << Size) - 1), Size, Pad, Buffer, Offset);
 }
 
 #include "M68kGenMCCodeBeads.inc"
 
 void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   unsigned Opcode = MI.getOpcode();