[Hexagon] Support inlined use of cs0 and cs1

[sidneym]

Summary

Allow inline assembly to reference cs0 and cs1 registers.

[sidneym]

Same patch, just added full context.

[bcain]

LGTM. @kparzysz ?

clang/lib/Basic/Targets/Hexagon.cpp

else if (F == "-long-calls")
       UseLongCalls = false;
     else if (F == "+audio")
       HasAudio = true;
   }
   return true;
 }
 
 const char *const HexagonTargetInfo::GCCRegNames[] = {
     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",
     "r9",  "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
     "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
     "r27", "r28", "r29", "r30", "r31", "p0",  "p1",  "p2",  "p3",
-    "sa0", "lc0", "sa1", "lc1", "m0",  "m1",  "usr", "ugp",
+    "sa0", "lc0", "sa1", "lc1", "m0",  "m1",  "usr", "ugp", "cs0", "cs1",
     "r1:0", "r3:2", "r5:4", "r7:6", "r9:8", "r11:10", "r13:12", "r15:14",
     "r17:16", "r19:18", "r21:20", "r23:22", "r25:24", "r27:26", "r29:28",
     "r31:30"
 };
 
 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const {
   return llvm::makeArrayRef(GCCRegNames);
 }

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Register Reg = StringSwitch<Register>(RegName)
                      .Case("sa0", Hexagon::SA0)
                      .Case("lc0", Hexagon::LC0)
                      .Case("sa1", Hexagon::SA1)
                      .Case("lc1", Hexagon::LC1)
                      .Case("m0", Hexagon::M0)
                      .Case("m1", Hexagon::M1)
                      .Case("usr", Hexagon::USR)
                      .Case("ugp", Hexagon::UGP)
+                     .Case("cs0", Hexagon::CS0)
+                     .Case("cs1", Hexagon::CS1)
                      .Default(Register());
   if (Reg)
     return Reg;
 
   report_fatal_error("Invalid register name global variable");
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the

llvm/test/CodeGen/Hexagon/namedreg.ll

 ; RUN: llc -mattr=+reserved-r19 -march=hexagon < %s | FileCheck %s
 define dso_local i32 @r19f() #0 {
 entry:
   %0 = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %0
 }
-
 declare i32 @llvm.read_register.i32(metadata) #1
 
+define dso_local i32 @rcs0() #0 {
+entry:
+  %0 = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %0
+}
+
+define dso_local i32 @rcs1() #0 {
+entry:
+  %0 = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %0
+}
+
+
+
 !llvm.named.register.r19 = !{!0}
+!llvm.named.register.cs0 = !{!1}
+!llvm.named.register.cs1 = !{!2}
 
 !0 = !{!"r19"}
+!1 = !{!"cs0"}
+!2 = !{!"cs1"}
 ; CHECK: r0 = r19
+; CHECK: r0 = cs0
+; CHECK: r0 = cs1