[AVR] Refactor 8-bit & 16-bit shifts

[benshi001]

As @aykevl suggested in https://aykevl.nl/2021/02/avr-bitshift,

there could be further optimizations for 8-bit and 16-bit shifts, besides current llvm's optimization.

If we continue current llvm's way, more AVR specific SDNode would be introduced, and introducing new SDNodes for each shift amount seems stupid.

And this patch removes those stupid SDNodes and introducing 6 new ones, which have an extra immediate shift amount operand.

This way make it easy to add optimization for other immediate shift amount.

[benshi001]

Other optimization such as ashr x, 6 and ashr x, 15 can be easily added in future patches along this way.

[benshi001]

As shown in test case https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AVR/shift.ll,

this patch generates optimized code for most cases as avr-gcc does (though there are slight differences in instruction sequence).

TODO:

1. futher optimization for 8-bit ashr x, 6
2. remove the redundant lsl <lower byte> in 16-bit shl when shiftAmount>8;
3. remove the redundant lsr <higher byte> in 16-bit lshr when shiftAmount>8;
4. remove the redundant asr <higher byte> in 16-bit ashr when shiftAmount>8;

[benshi001]

Some key points in my design,

1. The reason for (outs LD8:$rd) but (ins GPR8:$src) in the new pseudo instructions, is that they rely on ANDI which requries R16-R31.

2. The reasons LSLW/LSRW/ASRW are not treated as LSLWN(1)/LSRWN(1)/ASRWN(1), are that
   
   2.1 LSLW/LSRW/ASRW are important fallbacks when shiftAmount = 2, 3
   
   2.2 LSLW/LSRW/ASRW are assisting methods for LSLWN(x)/LSRWN(x)/ASRWN(x) when shiftAmount = 5,6,9,10,13,14.
   
   They are so important that need to keep indpendent.

[dylanmckay]

Very nice design and simplification, looks good to me. Thank you for the link to Ayke's very nice blog post, as well as the detailed summary about your design and the tradeoffs within. It was also helpful that you kept the refactor and the optimizations themselves in separate patches, making this a non-functional change.

[aykevl]

This looks indeed a lot cleaner! I'm glad the blog post was useful :)

Ideally all these instructions would be expanded before register allocation (as described in my blog post), but sadly that doesn't seem to be possible with the current design of the AVR backend. Maybe it becomes possible in the future with GlobalISel.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

private:
 
   bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
 
   bool expandAtomicArithmeticOp(unsigned MemOpcode,
                                 unsigned ArithOpcode,
                                 Block &MBB,
                                 BlockIt MBBI);
 
+  /// Specific shift implementation.
+  bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
+  bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
+  bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
+  bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
+
   /// Scavenges a free GPR8 register for use.
   Register scavengeGPR8(MachineInstr &MI);
 };
 
 char AVRExpandPseudo::ID = 0;
 
 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
 
   // SREG is always implicitly killed
   MIBHI->getOperand(4).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // swap Rh
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg, getKillRegState(DstIsKill));
   buildMI(MBB, MBBI, AVR::SWAPRd)
auto MI3 =
           .addReg(DstLoReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstLoReg);
 
   // clr Rl
   auto MIBLO =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
           .addReg(DstLoReg, getKillRegState(DstIsKill));
   if (ImpIsDead)
     MIBLO->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSLW12Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstLoReg);
 
   // swap Rh
bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
   if (ImpIsDead)
     MI1->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
+bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 4:
+    return expandLSLW4Rd(MBB, MBBI);
+  case 8:
+    return expandLSLW8Rd(MBB, MBBI);
+  case 12:
+    return expandLSLW12Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented lslwn");
+    return false;
+  }
+}
+
+template <>
 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   unsigned OpLo = AVR::RORRd;
bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
 
   // SREG is always implicitly killed
   MIBLO->getOperand(3).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // swap Rh
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg, getKillRegState(DstIsKill));
   buildMI(MBB, MBBI, AVR::SWAPRd)
auto MI3 =
           .addReg(DstHiReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSRW8Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg);
 
   // Clear upper byte.
   auto MIBHI =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addReg(DstHiReg, getKillRegState(DstIsKill));
   if (ImpIsDead)
     MIBHI->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::LSRW12Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg);
 
   // swap Rl
bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
   if (ImpIsDead)
     MIBHI->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
+bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 4:
+    return expandLSRW4Rd(MBB, MBBI);
+  case 8:
+    return expandLSRW8Rd(MBB, MBBI);
+  case 12:
+    return expandLSRW12Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented lsrwn");
+    return false;
+  }
+}
+
+template <>
 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
   llvm_unreachable("RORW unimplemented");
   return false;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
   llvm_unreachable("ROLW unimplemented");
bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
 
   // SREG is always implicitly killed
   MIBLO->getOperand(3).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::ASRW8Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg);
 
   // Move the sign bit to the C flag.
bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
   if (ImpIsDead)
     MIBHI->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
-bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 8:
+    return expandASRW8Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented asrwn");
+    return false;
+  }
+}
+
+bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
 
   // ror r24
   // clr r24
   // ror r24
 
   buildMI(MBB, MBBI, AVR::RORRd)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
   // SREG is always implicitly killed
   MIRRC->getOperand(3).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
-bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 7:
+    return expandLSLB7Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented lslbn");
+    return false;
+  }
+}
+
+bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
 
   // rol r24
   // clr r24
   // rol r24
 
   buildMI(MBB, MBBI, AVR::ADCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
   // SREG is always implicitly killed
   MIRRC->getOperand(4).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
-bool AVRExpandPseudo::expand<AVR::ASRB7Rd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 7:
+    return expandLSRB7Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented lsrbn");
+    return false;
+  }
+}
+
+bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(2).isDead();
+  bool ImpIsDead = MI.getOperand(3).isDead();
 
   // lsl r24
   // sbc r24, r24
 
   buildMI(MBB, MBBI, AVR::ADDRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
       .addReg(DstReg, getKillRegState(DstIsKill));
 
   auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
       .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
     MIRRC->getOperand(3).setIsDead();
 
   // SREG is always implicitly killed
   MIRRC->getOperand(4).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
+template <>
+bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  unsigned Imm = MI.getOperand(2).getImm();
+  switch (Imm) {
+  case 7:
+    return expandASRB7Rd(MBB, MBBI);
+  default:
+    llvm_unreachable("unimplemented asrbn");
+    return false;
+  }
+}
+
 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   // sext R17:R16, R17
   // mov     r16, r17
   // lsl     r17
   // sbc     r17, r17
   // sext R17:R16, R13
case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
     EXPAND(AVR::STDWPtrQRr);
     EXPAND(AVR::INWRdA);
     EXPAND(AVR::OUTWARr);
     EXPAND(AVR::PUSHWRr);
     EXPAND(AVR::POPWRd);
     EXPAND(AVR::ROLBRd);
     EXPAND(AVR::RORBRd);
     EXPAND(AVR::LSLWRd);
-    EXPAND(AVR::LSLW4Rd);
-    EXPAND(AVR::LSLW8Rd);
-    EXPAND(AVR::LSLW12Rd);
     EXPAND(AVR::LSRWRd);
-    EXPAND(AVR::LSRW4Rd);
-    EXPAND(AVR::LSRW8Rd);
-    EXPAND(AVR::LSRW12Rd);
     EXPAND(AVR::RORWRd);
     EXPAND(AVR::ROLWRd);
     EXPAND(AVR::ASRWRd);
-    EXPAND(AVR::ASRW8Rd);
-    EXPAND(AVR::LSLB7Rd);
-    EXPAND(AVR::LSRB7Rd);
-    EXPAND(AVR::ASRB7Rd);
+    EXPAND(AVR::LSLWNRd);
+    EXPAND(AVR::LSRWNRd);
+    EXPAND(AVR::ASRWNRd);
+    EXPAND(AVR::LSLBNRd);
+    EXPAND(AVR::LSRBNRd);
+    EXPAND(AVR::ASRBNRd);
     EXPAND(AVR::SEXT);
     EXPAND(AVR::ZEXT);
     EXPAND(AVR::SPREAD);
     EXPAND(AVR::SPWRITE);
   }
 #undef EXPAND
   return false;
 }

llvm/lib/Target/AVR/AVRISelLowering.h

enum NodeType {
   RETI_FLAG,
   /// Represents an abstract call instruction,
   /// which includes a bunch of information.
   CALL,
   /// A wrapper node for TargetConstantPool,
   /// TargetExternalSymbol, and TargetGlobalAddress.
   WRAPPER,
   LSL,     ///< Logical shift left.
-  LSL4,    ///< Logical shift left 4 bits.
-  LSL8,    ///< Logical shift left 8 bits.
-  LSL12,   ///< Logical shift left 12 bits.
+  LSLBN,   ///< Byte logical shift left N bits.
+  LSLWN,   ///< Word logical shift left N bits.
   LSR,     ///< Logical shift right.
-  LSR4,    ///< Logical shift right 4 bits.
-  LSR8,    ///< Logical shift right 8 bits.
-  LSR12,   ///< Logical shift right 12 bits.
+  LSRBN,   ///< Byte logical shift right N bits.
+  LSRWN,   ///< Word logical shift right N bits.
   ASR,     ///< Arithmetic shift right.
-  ASR8,    ///< Arithmetic shift right 8 bits.
-  LSL7,    ///< Logical shift left 7 bits.
-  LSR7,    ///< Logical shift right 7 bits.
-  ASR7,    ///< Arithmetic shift right 7 bits.
+  ASRBN,   ///< Byte arithmetic shift right N bits.
+  ASRWN,   ///< Word arithmetic shift right N bits.
   ROR,     ///< Bit rotate right.
   ROL,     ///< Bit rotate left.
   LSLLOOP, ///< A loop of single logical shift left instructions.
   LSRLOOP, ///< A loop of single logical shift right instructions.
   ROLLOOP, ///< A loop of single left bit rotate instructions.
   RORLOOP, ///< A loop of single right bit rotate instructions.
   ASRLOOP, ///< A loop of single arithmetic shift right instructions.
   /// AVR conditional branches. Operand 0 is the chain operand, operand 1

llvm/lib/Target/AVR/AVRISelLowering.cpp

if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
                ShiftAmount < 7) {
       // Optimize LSR when 4 <= ShiftAmount <= 6.
       Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
       Victim =
           DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
       ShiftAmount -= 4;
     } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
       // Optimize LSL when ShiftAmount == 7.
-      Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim);
+      Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
+                           DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
     } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
       // Optimize LSR when ShiftAmount == 7.
-      Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim);
+      Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
+                           DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
     } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
       // Optimize ASR when ShiftAmount == 7.
-      Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
+      Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
+                           DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
     }
   } else if (VT.getSizeInBits() == 16) {
     if (4 <= ShiftAmount && ShiftAmount < 8)
       switch (Op.getOpcode()) {
       case ISD::SHL:
-        Victim = DAG.getNode(AVRISD::LSL4, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
+                             DAG.getConstant(4, dl, VT));
         ShiftAmount -= 4;
         break;
       case ISD::SRL:
-        Victim = DAG.getNode(AVRISD::LSR4, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
+                             DAG.getConstant(4, dl, VT));
         ShiftAmount -= 4;
         break;
       default:
         break;
       }
     else if (8 <= ShiftAmount && ShiftAmount < 12)
       switch (Op.getOpcode()) {
       case ISD::SHL:
-        Victim = DAG.getNode(AVRISD::LSL8, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
+                             DAG.getConstant(8, dl, VT));
         ShiftAmount -= 8;
         break;
       case ISD::SRL:
-        Victim = DAG.getNode(AVRISD::LSR8, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
+                             DAG.getConstant(8, dl, VT));
         ShiftAmount -= 8;
         break;
       case ISD::SRA:
-        Victim = DAG.getNode(AVRISD::ASR8, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
+                             DAG.getConstant(8, dl, VT));
         ShiftAmount -= 8;
         break;
       default:
         break;
       }
     else if (12 <= ShiftAmount)
       switch (Op.getOpcode()) {
       case ISD::SHL:
-        Victim = DAG.getNode(AVRISD::LSL12, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
+                             DAG.getConstant(12, dl, VT));
         ShiftAmount -= 12;
         break;
       case ISD::SRL:
-        Victim = DAG.getNode(AVRISD::LSR12, dl, VT, Victim);
+        Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
+                             DAG.getConstant(12, dl, VT));
         ShiftAmount -= 12;
         break;
       default:
         break;
       }
   }
 
   while (ShiftAmount--) {

llvm/lib/Target/AVR/AVRInstrInfo.td

def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond,
                        [SDNPHasChain, SDNPInGlue]>;
 def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
 def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
 def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
 def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
 
 // Shift nodes.
 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
-def AVRlsl4 : SDNode<"AVRISD::LSL4", SDTIntUnaryOp>;
-def AVRlsl8 : SDNode<"AVRISD::LSL8", SDTIntUnaryOp>;
-def AVRlsl12 : SDNode<"AVRISD::LSL12", SDTIntUnaryOp>;
 def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
-def AVRlsr4 : SDNode<"AVRISD::LSR4", SDTIntUnaryOp>;
-def AVRlsr8 : SDNode<"AVRISD::LSR8", SDTIntUnaryOp>;
-def AVRlsr12 : SDNode<"AVRISD::LSR12", SDTIntUnaryOp>;
 def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
 def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
 def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
-def AVRasr8 : SDNode<"AVRISD::ASR8", SDTIntUnaryOp>;
-def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>;
-def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>;
-def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>;
+def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>;
+def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>;
+def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>;
+def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>;
+def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>;
+def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>;
 
 // Pseudo shift nodes for non-constant shift amounts.
 def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
 def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
 def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
 def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
 def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
 

 {
   // 8-bit LSL is an alias of ADD Rd, Rd
 
   def LSLWRd : Pseudo<(outs DREGS:$rd),
                       (ins DREGS:$src),
                       "lslw\t$rd",
                       [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>;
 
-  def LSLB7Rd : Pseudo<(outs GPR8:$rd),
-                       (ins GPR8:$src),
-                       "lslb7\t$rd",
-                       [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
-
-  def LSLW4Rd : Pseudo<(outs DLDREGS:$rd),
-                       (ins DREGS:$src),
-                       "lslw4\t$rd",
-                       [(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>;
-
-  def LSLW8Rd : Pseudo<(outs DREGS:$rd),
-                       (ins DREGS:$src),
-                       "lslw8\t$rd",
-                       [(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>;
+  def LSLWNRd : Pseudo<(outs DLDREGS:$rd),
+                       (ins DREGS:$src, imm16:$bits),
+                       "lslwn\t$rd, $bits",
+                       [(set i16:$rd, (AVRlslwn i16:$src, imm:$bits)),
+                        (implicit SREG)]>;
 
-  def LSLW12Rd : Pseudo<(outs DLDREGS:$rd),
-                       (ins DREGS:$src),
-                       "lslw12\t$rd",
-                       [(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>;
+  def LSLBNRd : Pseudo<(outs LD8:$rd),
+                       (ins GPR8:$src, imm_ldi8:$bits),
+                       "lslbn\t$rd, $bits",
+                       [(set i8:$rd, (AVRlslbn i8:$src, imm:$bits)),
+                        (implicit SREG)]>;
 
   def LSRRd : FRd<0b1001,
                   0b0100110,
                   (outs GPR8:$rd),
                   (ins GPR8:$src),
                   "lsr\t$rd",
                   [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>;
 
-  def LSRB7Rd : Pseudo<(outs GPR8:$rd),
-                       (ins GPR8:$src),
-                       "lsrb7\t$rd",
-                       [(set i8:$rd, (AVRlsr7 i8:$src)), (implicit SREG)]>;
-
   def LSRWRd : Pseudo<(outs DREGS:$rd),
                       (ins DREGS:$src),
                       "lsrw\t$rd",
                       [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
 
-  def LSRW4Rd : Pseudo<(outs DLDREGS:$rd),
-                       (ins DREGS:$src),
-                       "lsrw4\t$rd",
-                       [(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>;
-
-  def LSRW8Rd : Pseudo<(outs DREGS:$rd),
-                       (ins DREGS:$src),
-                       "lsrw8\t$rd",
-                       [(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>;
+  def LSRWNRd : Pseudo<(outs DLDREGS:$rd),
+                       (ins DREGS:$src, imm16:$bits),
+                       "lsrwn\t$rd, $bits",
+                       [(set i16:$rd, (AVRlsrwn i16:$src, imm:$bits)),
+                        (implicit SREG)]>;
 
-  def LSRW12Rd : Pseudo<(outs DLDREGS:$rd),
-                       (ins DREGS:$src),
-                       "lsrw12\t$rd",
-                       [(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>;
+  def LSRBNRd : Pseudo<(outs LD8:$rd),
+                       (ins GPR8:$src, imm_ldi8:$bits),
+                       "lsrbn\t$rd, $bits",
+                       [(set i8:$rd, (AVRlsrbn i8:$src, imm:$bits)),
+                        (implicit SREG)]>;
 
   def ASRRd : FRd<0b1001,
                   0b0100101,
                   (outs GPR8:$rd),
                   (ins GPR8:$src),
                   "asr\t$rd",
                   [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>;
 
-  def ASRB7Rd : Pseudo<(outs GPR8:$rd),
-                       (ins GPR8:$src),
-                       "asrb7\t$rd",
-                       [(set i8:$rd, (AVRasr7 i8:$src)), (implicit SREG)]>;
+  def ASRWNRd : Pseudo<(outs DLDREGS:$rd),
+                       (ins DREGS:$src, imm16:$bits),
+                       "asrwn\t$rd, $bits",
+                       [(set i16:$rd, (AVRasrwn i16:$src, imm:$bits)),
+                        (implicit SREG)]>;
+
+  def ASRBNRd : Pseudo<(outs LD8:$rd),
+                       (ins GPR8:$src, imm_ldi8:$bits),
+                       "asrbn\t$rd, $bits",
+                       [(set i8:$rd, (AVRasrbn i8:$src, imm:$bits)),
+                        (implicit SREG)]>;
 
   def ASRWRd : Pseudo<(outs DREGS:$rd),
                       (ins DREGS:$src),
                       "asrw\t$rd",
                       [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>;
 
-  def ASRW8Rd : Pseudo<(outs DREGS:$rd),
-                       (ins DREGS:$src),
-                       "asrw8\t$rd",
-                       [(set i16:$rd, (AVRasr8 i16:$src)), (implicit SREG)]>;
-
   // Bit rotate operations.
   let Uses = [SREG] in
   {
     // 8-bit ROL is an alias of ADC Rd, Rd
 
     def ROLBRd : Pseudo<(outs GPR8:$rd),
                         (ins GPR8:$src),
                         "rolb\t$rd",
def : Pat<(store i8:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
           (STSKRr tglobaladdr:$dst, i8:$src)>;
 def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
           (STSWKRr tglobaladdr:$dst, i16:$src)>;
 
 // BlockAddress
 def : Pat<(i16 (AVRWrapper tblockaddress:$dst)),
           (LDIWRdK tblockaddress:$dst)>;
 
-def : Pat<(i8 (trunc (AVRlsr8 DREGS:$src))),
+def : Pat<(i8 (trunc (AVRlsrwn DLDREGS:$src, (i16 8)))),
           (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
 
 // :FIXME: DAGCombiner produces an shl node after legalization from these seq:
 // BR_JT -> (mul x, 2) -> (shl x, 1)
 def : Pat<(shl i16:$src1, (i8 1)),
           (LSLWRd i16:$src1)>;
 
 // Lowering of 'tst' node to 'TST' instruction.