Remove redundant RORs when shift amount >= 8.
I should have explained this a while ago, sorry for neglecting this.
Sorry I meant in the MachineIR phase. I think the ideal way to expand bit shift operations is as follows:
- Lower lsl/lshr/ashr operations in SelectionDAG to pseudo instructions that have a constant immediate operand. You will only need six pseudo instructions this way: for lsl/lshr/ashr and for both 8 bit and 16 bit versions. These pseudo instructions should have the usesCustomInserter flag set.
- Expand these instructions in AVRTargetLowering::EmitInstrWithCustomInserter. There are already a few existing expansions in there.
The big advantage is that you can do shifts before register allocation and I think it is also easier to structure the code. Also, this means you don't need as many instructions to expand in the pseudo instruction expansion pass.
Recently I have been thinking a lot about constant shifts on AVR and I've written a blog post here: https://aykevl.nl/2021/02/avr-bitshift
I think you will find it useful.
To be clear: I really appreciate your work on the AVR backend. There are many things that need to be improved, such as these bit shift operations. But I think there is a different and possibly better way to implement these expansions.
Thanks. I have submitted a new patch with a compromised solution against your suggestion. Your suggestion introducing 6 pseudo instructions with an extra shift amount operand is really good. https://reviews.llvm.org/D98335
But I still like to do the pseudo expansion in the old way, which requires the least change.