[AMDGPU] Create AMDGPUModuleInfo

[rampitec]

Summary

Replace AMDGPUMachineModuleInfo to have per-module
information available before MF is created.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.cpp

58

Why does this need to store a module? The context may be used by multiple modules. It shouldn't matter since this just needs the context IDs

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.cpp

58

It could remember context, but since it is named ModuleInfo I am keeping track of a module. Probably it can be renamed as AMDGPUContextInfo and track the context.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.cpp

58

It's not tracking anything about the module either. It's purely a context extension

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.cpp

58

At least not so far. I will rename it tomorrow and will track the context. It will have to stay a module pass though, but I guess it is cheap. I will just have to check context didn't change before I reset it.

[rampitec]

Ugh, that's the problem: I cannot tell if a context is the same as an old one. I can tell it for module as I can create a module pass. Every time module changes I can reset the context. I cannot create a context pass though.

Now I cannot compare context address as well since the same memory can be reused. This is exactly the same problem as with a module, its address can be the same, but the module different. I.e. there is no reliable way to identify a module, but there is a module pass, and there is no reliable way to identify a context, but there are no context passes.

Effectively even though this is a context extension I need to reset it for every new module. Well, unless you tell me there is a way to reliably identify a context.

[rampitec]

Is there any guarantee that a pointer to LLVMContext remains valid through the whole TM life time?

[rampitec]

Updated to use it from lowering.

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp

-//===--- AMDGPUMachineModuleInfo.cpp ----------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file
-/// AMDGPU Machine Module Info.
-///
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPUMachineModuleInfo.h"
-
-namespace llvm {
-
-AMDGPUMachineModuleInfo::AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI)
-    : MachineModuleInfoELF(MMI) {
-  LLVMContext &CTX = MMI.getModule()->getContext();
-  AgentSSID = CTX.getOrInsertSyncScopeID("agent");
-  WorkgroupSSID = CTX.getOrInsertSyncScopeID("workgroup");
-  WavefrontSSID = CTX.getOrInsertSyncScopeID("wavefront");
-  SystemOneAddressSpaceSSID =
-      CTX.getOrInsertSyncScopeID("one-as");
-  AgentOneAddressSpaceSSID =
-      CTX.getOrInsertSyncScopeID("agent-one-as");
-  WorkgroupOneAddressSpaceSSID =
-      CTX.getOrInsertSyncScopeID("workgroup-one-as");
-  WavefrontOneAddressSpaceSSID =
-      CTX.getOrInsertSyncScopeID("wavefront-one-as");
-  SingleThreadOneAddressSpaceSSID =
-      CTX.getOrInsertSyncScopeID("singlethread-one-as");
-}
-
-} // end namespace llvm

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.h

-//===--- AMDGPUMachineModuleInfo.h ------------------------------*- C++ -*-===//
+//===-- AMDGPUModuleInfo.h ------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file
-/// AMDGPU Machine Module Info.
-///
+/// \file This pass holds AMDGPU module specific information.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
-#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMODULEINFO_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMODULEINFO_H
 
-#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/IR/LLVMContext.h"
 
 namespace llvm {
 
-class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF {
-private:
+class ModulePass;
+class PassRegistry;
 
+class AMDGPUModuleInfo {
+  Module *M = nullptr;
   // All supported memory/synchronization scopes can be found here:
   //   http://llvm.org/docs/AMDGPUUsage.html#memory-scopes
 
   /// Agent synchronization scope ID (cross address space).
   SyncScope::ID AgentSSID;
   /// Workgroup synchronization scope ID (cross address space).
   SyncScope::ID WorkgroupSSID;
   /// Wavefront synchronization scope ID (cross address space).
if (SSID == SyncScope::SingleThread ||
         SSID == getSingleThreadOneAddressSpaceSSID())
       return 0;
     else if (SSID == getWavefrontSSID() ||
              SSID == getWavefrontOneAddressSpaceSSID())
       return 1;
     else if (SSID == getWorkgroupSSID() ||
              SSID == getWorkgroupOneAddressSpaceSSID())
       return 2;
     else if (SSID == getAgentSSID() ||
              SSID == getAgentOneAddressSpaceSSID())
       return 3;
     else if (SSID == SyncScope::System ||
              SSID == getSystemOneAddressSpaceSSID())
       return 4;
 
     return None;
   }
 
   /// \returns True if \p SSID is restricted to single address space, false
   /// otherwise
   bool isOneAddressSpace(SyncScope::ID SSID) const {
     return SSID == getSingleThreadOneAddressSpaceSSID() ||
         SSID == getWavefrontOneAddressSpaceSSID() ||
         SSID == getWorkgroupOneAddressSpaceSSID() ||
         SSID == getAgentOneAddressSpaceSSID() ||
         SSID == getSystemOneAddressSpaceSSID();
   }
 
 public:
-  AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI);
+  void initializeModuleInfo(Module *M);
+
+  void resetModule() { M = nullptr; }
 
   /// \returns Agent synchronization scope ID (cross address space).
   SyncScope::ID getAgentSSID() const {
     return AgentSSID;
   }
   /// \returns Workgroup synchronization scope ID (cross address space).
   SyncScope::ID getWorkgroupSSID() const {
     return WorkgroupSSID;
   }
   /// \returns Wavefront synchronization scope ID (cross address space).
   SyncScope::ID getWavefrontSSID() const {
     return WavefrontSSID;
   }
   /// \returns System synchronization scope ID (single address space).
   SyncScope::ID getSystemOneAddressSpaceSSID() const {
     return SystemOneAddressSpaceSSID;
   }
   /// \returns Agent synchronization scope ID (single address space).
   SyncScope::ID getAgentOneAddressSpaceSSID() const {
Optional<bool> isSyncScopeInclusion(SyncScope::ID A, SyncScope::ID B) const {
     const auto &BIO = getSyncScopeInclusionOrdering(B);
     if (!AIO || !BIO)
       return None;
 
     bool IsAOneAddressSpace = isOneAddressSpace(A);
     bool IsBOneAddressSpace = isOneAddressSpace(B);
 
     return AIO.getValue() >= BIO.getValue() &&
         (IsAOneAddressSpace == IsBOneAddressSpace || !IsAOneAddressSpace);
   }
 };
 
-} // end namespace llvm
+void initializeAMDGPUModuleInfoPassPass(PassRegistry &);
+ModulePass *createAMDGPUModuleInfoPass(AMDGPUModuleInfo *Info);
+
+} // End namespace llvm
 
-#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H
+#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMODULEINFO_H

llvm/lib/Target/AMDGPU/AMDGPUModuleInfo.cpp

+//===-- AMDGPUModuleInfo.cpp ----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This pass holds AMDGPU module specific information.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUModuleInfo.h"
+#include "llvm/IR/Module.h"
+#include "llvm/Pass.h"
+
+using namespace llvm;
+
+namespace {
+
+class AMDGPUModuleInfoPass : public ModulePass {
+  AMDGPUModuleInfo *Info;
+
+public:
+  static char ID;
+
+  AMDGPUModuleInfoPass(AMDGPUModuleInfo *Info = nullptr) :
+    ModulePass(ID), Info(Info) { }
+
+  bool runOnModule(Module &M) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+ }
+};
+
+} // End anonymous namespace
+
+INITIALIZE_PASS(AMDGPUModuleInfoPass, "amdgpu-module-info",
+                "AMDGPU Module Information", false, false)
+
+char AMDGPUModuleInfoPass::ID = 0;
+
+ModulePass *llvm::createAMDGPUModuleInfoPass(AMDGPUModuleInfo *Info) {
+  return new AMDGPUModuleInfoPass(Info);
+}
+
+bool AMDGPUModuleInfoPass::runOnModule(Module &M) {
+  Info->resetModule();
+  return false;
+}
+
+void AMDGPUModuleInfo::initializeModuleInfo(Module *M) {
+  if (this->M == M)
+    return;
+
+  this->M = M;
+  LLVMContext &CTX = M->getContext();
+  AgentSSID = CTX.getOrInsertSyncScopeID("agent");
+  WorkgroupSSID = CTX.getOrInsertSyncScopeID("workgroup");
+  WavefrontSSID = CTX.getOrInsertSyncScopeID("wavefront");
+  SystemOneAddressSpaceSSID =
+      CTX.getOrInsertSyncScopeID("one-as");
+  AgentOneAddressSpaceSSID =
+      CTX.getOrInsertSyncScopeID("agent-one-as");
+  WorkgroupOneAddressSpaceSSID =
+      CTX.getOrInsertSyncScopeID("workgroup-one-as");
+  WavefrontOneAddressSpaceSSID =
+      CTX.getOrInsertSyncScopeID("wavefront-one-as");
+  SingleThreadOneAddressSpaceSSID =
+      CTX.getOrInsertSyncScopeID("singlethread-one-as");
+}

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h

 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// The AMDGPU TargetMachine interface definition for hw codgen targets.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
 
+#include "AMDGPUModuleInfo.h"
 #include "GCNSubtarget.h"
 #include "R600Subtarget.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
 //===----------------------------------------------------------------------===//
 // AMDGPU Target Machine (R600+)
 //===----------------------------------------------------------------------===//
 
 class AMDGPUTargetMachine : public LLVMTargetMachine {
 protected:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
 
+  mutable AMDGPUModuleInfo ModuleInfo;
+
   StringRef getGPUName(const Function &F) const;
   StringRef getFeatureString(const Function &F) const;
 
 public:
+
   static bool EnableLateStructurizeCFG;
   static bool EnableFunctionCalls;
   static bool EnableFixedFunctionABI;
 
   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                       StringRef FS, TargetOptions Options,
                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
                       CodeGenOpt::Level OL);
public:
   void registerDefaultAliasAnalyses(AAManager &) override;
 
   /// Get the integer value of a null pointer in the given address space.
   static int64_t getNullPointerValue(unsigned AddrSpace);
 
   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 
   unsigned getAssumedAddrSpace(const Value *V) const override;
+
+  AMDGPUModuleInfo *getModuleInfoPtr() const { return &ModuleInfo; }
+
+  const AMDGPUModuleInfo &getModuleInfo(Module *M) const;
 };
 
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 class R600TargetMachine final : public AMDGPUTargetMachine {
 private:

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUTargetMachine.h"
 #include "AMDGPU.h"
 #include "AMDGPUAliasAnalysis.h"
 #include "AMDGPUExportClustering.h"
 #include "AMDGPUMacroFusion.h"
+#include "AMDGPUModuleInfo.h"
 #include "AMDGPUTargetObjectFile.h"
 #include "AMDGPUTargetTransformInfo.h"
 #include "GCNIterativeScheduler.h"
 #include "GCNSchedStrategy.h"
 #include "R600MachineScheduler.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIMachineScheduler.h"
 #include "TargetInfo/AMDGPUTargetInfo.h"
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPUAlwaysInlinePass(*PR);
   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
   initializeAMDGPUAnnotateUniformValuesPass(*PR);
   initializeAMDGPUArgumentUsageInfoPass(*PR);
   initializeAMDGPUAtomicOptimizerPass(*PR);
   initializeAMDGPULowerKernelArgumentsPass(*PR);
   initializeAMDGPULowerKernelAttributesPass(*PR);
   initializeAMDGPULowerIntrinsicsPass(*PR);
+  initializeAMDGPUModuleInfoPassPass(*PR);
   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
   initializeAMDGPUPostLegalizerCombinerPass(*PR);
   initializeAMDGPUPreLegalizerCombinerPass(*PR);
   initializeAMDGPURegBankCombinerPass(*PR);
   initializeAMDGPUPromoteAllocaPass(*PR);
   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
   initializeAMDGPUCodeGenPreparePass(*PR);
   initializeAMDGPULateCodeGenPreparePass(*PR);

 
 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   return FSAttr.isValid() ? FSAttr.getValueAsString()
                           : getTargetFeatureString();
 }
 
+const AMDGPUModuleInfo &AMDGPUTargetMachine::getModuleInfo(Module *M) const {
+  ModuleInfo.initializeModuleInfo(M);
+  return ModuleInfo;
+};
+
 /// Predicate for Internalize pass.
 static bool mustPreserveGV(const GlobalValue &GV) {
   if (const Function *F = dyn_cast<Function>(&GV))
     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
 
   return !GV.use_empty();
 }
 

 void AMDGPUPassConfig::addIRPasses() {
   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
 
   // There is no reason to run these.
   disablePass(&StackMapLivenessID);
   disablePass(&FuncletLayoutID);
   disablePass(&PatchableFunctionID);
 
+  addPass(createAMDGPUModuleInfoPass(getAMDGPUTargetMachine()
+                                         .getModuleInfoPtr()));
+
   addPass(createAMDGPUPrintfRuntimeBinding());
 
   // This must occur before inlining, as the inliner will not look through
   // bitcast calls.
   addPass(createAMDGPUFixFunctionBitcastsPass());
 
   // A call to propagate attributes pass in the backend in case opt was not run.
   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));

llvm/lib/Target/AMDGPU/CMakeLists.txt

add_llvm_target(AMDGPUCodeGen
   AMDGPULegalizerInfo.cpp
   AMDGPULibCalls.cpp
   AMDGPULibFunc.cpp
   AMDGPULowerIntrinsics.cpp
   AMDGPULowerKernelArguments.cpp
   AMDGPULowerKernelAttributes.cpp
   AMDGPUMachineCFGStructurizer.cpp
   AMDGPUMachineFunction.cpp
-  AMDGPUMachineModuleInfo.cpp
+  AMDGPUModuleInfo.cpp
   AMDGPUMacroFusion.cpp
   AMDGPUMCInstLower.cpp
   AMDGPUMIRFormatter.cpp
   AMDGPUOpenCLEnqueuedBlockLowering.cpp
   AMDGPUPostLegalizerCombiner.cpp
   AMDGPUPreLegalizerCombiner.cpp
   AMDGPUPromoteAlloca.cpp
   AMDGPUPropagateAttributes.cpp

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if ((AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) &&
          Subtarget->hasAtomicFaddInsts()) {
       if (!fpModeMatchesGlobalFPAtomicMode(RMW) ||
           RMW->getFunction()->getFnAttribute("amdgpu-unsafe-fp-atomics")
               .getValueAsString() != "true")
         return AtomicExpansionKind::CmpXChg;
 
       if (Subtarget->hasGFX90AInsts()) {
         auto SSID = RMW->getSyncScopeID();
+        Module *M = RMW->getParent()->getParent()->getParent();
+        const GCNTargetMachine &TM =
+          static_cast<const GCNTargetMachine &>(getTargetMachine());
         if (SSID == SyncScope::System ||
-            SSID == RMW->getContext().getOrInsertSyncScopeID("one-as"))
+            SSID == TM.getModuleInfo(M).getSystemOneAddressSpaceSSID())
           return AtomicExpansionKind::CmpXChg;
 
         return (Ty->isFloatTy() && AS == AMDGPUAS::FLAT_ADDRESS) ?
           AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
       }
 
       if (!Subtarget->hasGFX90AInsts() && AS != AMDGPUAS::GLOBAL_ADDRESS)
         return AtomicExpansionKind::CmpXChg;

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

 //===- SIMemoryLegalizer.cpp ----------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// Memory legalizer - implements memory model. More information can be
 /// found here:
 ///   http://llvm.org/docs/AMDGPUUsage.html#memory-model
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
-#include "AMDGPUMachineModuleInfo.h"
+#include "AMDGPUModuleInfo.h"
+#include "AMDGPUTargetMachine.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/ADT/BitmaskEnum.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/Support/AtomicOrdering.h"
 #include "llvm/Support/TargetParser.h"
 
public:
   bool isAtomic() const {
     return Ordering != AtomicOrdering::NotAtomic;
   }
 
 };
 
 class SIMemOpAccess final {
 private:
-  AMDGPUMachineModuleInfo *MMI = nullptr;
+  const AMDGPUModuleInfo *MMI = nullptr;
 
   /// Reports unsupported message \p Msg for \p MI to LLVM context.
   void reportUnsupported(const MachineBasicBlock::iterator &MI,
                          const char *Msg) const;
 
   /// Inspects the target synchronization scope \p SSID and determines
   /// the SI atomic scope it corresponds to, the address spaces it
   /// covers, and whether the memory ordering applies between address
if (AS == AMDGPUAS::PRIVATE_ADDRESS)
     return SIAtomicAddrSpace::SCRATCH;
   if (AS == AMDGPUAS::REGION_ADDRESS)
     return SIAtomicAddrSpace::GDS;
 
   return SIAtomicAddrSpace::OTHER;
 }
 
 SIMemOpAccess::SIMemOpAccess(MachineFunction &MF) {
-  MMI = &MF.getMMI().getObjFileInfo<AMDGPUMachineModuleInfo>();
+  const AMDGPUTargetMachine& TM = (const AMDGPUTargetMachine&)MF.getTarget();
+  Module *M = MF.getFunction().getParent();
+  MMI = &TM.getModuleInfo(M);
 }
 
 Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
     const MachineBasicBlock::iterator &MI) const {
   assert(MI->getNumMemOperands() > 0);
 
   SyncScope::ID SSID = SyncScope::SingleThread;
   AtomicOrdering Ordering = AtomicOrdering::NotAtomic;