[AMDGPU] Disable SCC bit on fp atomics

[kzhuravl]

llvm/lib/Target/AMDGPU/AMDGPU.td

1222–1224

def hasMAIInsts...? as you are not checking any generation in particular.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.td

1222–1224

There is no FeatureGFX90AInsts, we have FeatureMAIInsts instead.

[kzhuravl]

LGTM, thanks.

llvm/lib/Target/AMDGPU/AMDGPU.td

1222–1224

I think you meant to say that there is no "FeatureGFX908Insts"? FeatureGFX90AInsts exists.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.td

1222–1224

Yes, right.

llvm/lib/Target/AMDGPU/AMDGPU.td

Predicate<"!Subtarget->hasGFX90AInsts() &&"
             "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
             " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
 
 def isGFX90AOnly :
   Predicate<"Subtarget->hasGFX90AInsts()">,
   AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
 
+def isGFX908orGFX90A :
+  Predicate<"Subtarget->hasMAIInsts()">,
+  AssemblerPredicate<(all_of FeatureMAIInsts)>;
+
 def isGFX8GFX9 :
   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
 
 def isGFX10Plus :
   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
   AssemblerPredicate<(all_of FeatureGFX10Insts)>;

llvm/lib/Target/AMDGPU/FLATInstructions.td

 defm FLAT_ATOMIC_FMIN_X2       : FLAT_Real_Atomics_ci <0x5f, FLAT_ATOMIC_FMIN_X2>;
 defm FLAT_ATOMIC_FMAX_X2       : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2>;
 
 
 //===----------------------------------------------------------------------===//
 // VI
 //===----------------------------------------------------------------------===//
 
-class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
+class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
   FLAT_Real <op, ps>,
   SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
   let AssemblerPredicate = isGFX8GFX9;
   let DecoderNamespace = "GFX8";
 
-  let Inst{25} = !if(ps.has_sccb, sccb, ps.sccbValue);
+  let Inst{25} = !if(has_sccb, sccb, ps.sccbValue);
+  let AsmString = ps.Mnemonic #
+                  !subst("$sccb", !if(has_sccb, "$sccb",""), ps.AsmOperands);
 }
 
-multiclass FLAT_Real_AllAddr_vi<bits<7> op> {
-  def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME)>;
-  def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
+multiclass FLAT_Real_AllAddr_vi<bits<7> op,
+  bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
+  def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
+  def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
 }
 
 def FLAT_LOAD_UBYTE_vi         : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
 def FLAT_LOAD_SBYTE_vi         : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
 def FLAT_LOAD_USHORT_vi        : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
 def FLAT_LOAD_SSHORT_vi        : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
 def FLAT_LOAD_DWORD_vi         : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
 def FLAT_LOAD_DWORDX2_vi       : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;

 
 def FLAT_LOAD_UBYTE_D16_vi    : FLAT_Real_vi <0x20, FLAT_LOAD_UBYTE_D16>;
 def FLAT_LOAD_UBYTE_D16_HI_vi : FLAT_Real_vi <0x21, FLAT_LOAD_UBYTE_D16_HI>;
 def FLAT_LOAD_SBYTE_D16_vi    : FLAT_Real_vi <0x22, FLAT_LOAD_SBYTE_D16>;
 def FLAT_LOAD_SBYTE_D16_HI_vi : FLAT_Real_vi <0x23, FLAT_LOAD_SBYTE_D16_HI>;
 def FLAT_LOAD_SHORT_D16_vi    : FLAT_Real_vi <0x24, FLAT_LOAD_SHORT_D16>;
 def FLAT_LOAD_SHORT_D16_HI_vi : FLAT_Real_vi <0x25, FLAT_LOAD_SHORT_D16_HI>;
 
-multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
-  def _vi     : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
-  def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
+multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps,
+  bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
+  def _vi     : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
+  def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
 }
 
-multiclass FLAT_Global_Real_Atomics_vi<bits<7> op> :
-  FLAT_Real_AllAddr_vi<op> {
-  def _RTN_vi  : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
-  def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
+multiclass FLAT_Global_Real_Atomics_vi<bits<7> op,
+  bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> :
+  FLAT_Real_AllAddr_vi<op, has_sccb> {
+  def _RTN_vi  : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
+  def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
 }
 
 
 defm FLAT_ATOMIC_SWAP       : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
 defm FLAT_ATOMIC_CMPSWAP    : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
 defm FLAT_ATOMIC_ADD        : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
 defm FLAT_ATOMIC_SUB        : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
 defm FLAT_ATOMIC_SMIN       : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;

 defm SCRATCH_LOAD_SHORT_D16_HI  : FLAT_Real_AllAddr_vi <0x25>;
 defm SCRATCH_STORE_SHORT        : FLAT_Real_AllAddr_vi <0x1a>;
 defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x1b>;
 defm SCRATCH_STORE_DWORD        : FLAT_Real_AllAddr_vi <0x1c>;
 defm SCRATCH_STORE_DWORDX2      : FLAT_Real_AllAddr_vi <0x1d>;
 defm SCRATCH_STORE_DWORDX3      : FLAT_Real_AllAddr_vi <0x1e>;
 defm SCRATCH_STORE_DWORDX4      : FLAT_Real_AllAddr_vi <0x1f>;
 
-let SubtargetPredicate = isGFX90APlus in {
-  defm FLAT_ATOMIC_ADD_F64   : FLAT_Real_Atomics_vi<0x4f, FLAT_ATOMIC_ADD_F64>;
-  defm FLAT_ATOMIC_MIN_F64   : FLAT_Real_Atomics_vi<0x50, FLAT_ATOMIC_MIN_F64>;
-  defm FLAT_ATOMIC_MAX_F64   : FLAT_Real_Atomics_vi<0x51, FLAT_ATOMIC_MAX_F64>;
-  defm GLOBAL_ATOMIC_ADD_F64 : FLAT_Global_Real_Atomics_vi<0x4f>;
-  defm GLOBAL_ATOMIC_MIN_F64 : FLAT_Global_Real_Atomics_vi<0x50>;
-  defm GLOBAL_ATOMIC_MAX_F64 : FLAT_Global_Real_Atomics_vi<0x51>;
-} // End SubtargetPredicate = isGFX90APlus
+let SubtargetPredicate = isGFX908orGFX90A in {
+defm GLOBAL_ATOMIC_ADD_F32    : FLAT_Global_Real_Atomics_vi <0x04d, 0>;
+defm GLOBAL_ATOMIC_PK_ADD_F16 : FLAT_Global_Real_Atomics_vi <0x04e, 0>;
+}
+
+let SubtargetPredicate = isGFX90AOnly in {
+  defm FLAT_ATOMIC_ADD_F64   : FLAT_Real_Atomics_vi<0x4f, FLAT_ATOMIC_ADD_F64, 0>;
+  defm FLAT_ATOMIC_MIN_F64   : FLAT_Real_Atomics_vi<0x50, FLAT_ATOMIC_MIN_F64, 0>;
+  defm FLAT_ATOMIC_MAX_F64   : FLAT_Real_Atomics_vi<0x51, FLAT_ATOMIC_MAX_F64, 0>;
+  defm GLOBAL_ATOMIC_ADD_F64 : FLAT_Global_Real_Atomics_vi<0x4f, 0>;
+  defm GLOBAL_ATOMIC_MIN_F64 : FLAT_Global_Real_Atomics_vi<0x50, 0>;
+  defm GLOBAL_ATOMIC_MAX_F64 : FLAT_Global_Real_Atomics_vi<0x51, 0>;
+} // End SubtargetPredicate = isGFX90AOnly
 
 //===----------------------------------------------------------------------===//
 // GFX10.
 //===----------------------------------------------------------------------===//
 
 class FLAT_Real_gfx10<bits<7> op, FLAT_Pseudo ps> :
     FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
   let AssemblerPredicate = isGFX10Plus;

 defm SCRATCH_STORE_DWORDX4      : FLAT_Real_ScratchAllAddr_gfx10<0x01e>;
 defm SCRATCH_STORE_DWORDX3      : FLAT_Real_ScratchAllAddr_gfx10<0x01f>;
 defm SCRATCH_LOAD_UBYTE_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x020>;
 defm SCRATCH_LOAD_UBYTE_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x021>;
 defm SCRATCH_LOAD_SBYTE_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x022>;
 defm SCRATCH_LOAD_SBYTE_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x023>;
 defm SCRATCH_LOAD_SHORT_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x024>;
 defm SCRATCH_LOAD_SHORT_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x025>;
-
-let SubtargetPredicate = HasAtomicFaddInsts in {
-
-defm GLOBAL_ATOMIC_ADD_F32    : FLAT_Global_Real_Atomics_vi <0x04d>;
-defm GLOBAL_ATOMIC_PK_ADD_F16 : FLAT_Global_Real_Atomics_vi <0x04e>;
-
-} // End SubtargetPredicate = HasAtomicFaddInsts

llvm/test/MC/AMDGPU/gfx90a_asm_features.s

 // GFX90A: flat_atomic_add_f64 v[0:1], v[2:3] offset:7 ; encoding: [0x07,0x00,0x3c,0xdd,0x00,0x02,0x00,0x00]
 flat_atomic_add_f64 v[0:1], v[2:3] offset:7
 
 // NOT-GFX90A: error: instruction not supported on this GPU
 // GFX90A: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x3d,0xdd,0x00,0x02,0x00,0x00]
 flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc
 
 // NOT-GFX90A: error: instruction not supported on this GPU
-// GFX90A: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc scc ; encoding: [0xff,0x0f,0x3d,0xdf,0x00,0x02,0x00,0x00]
-flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc scc
-
-// NOT-GFX90A: error: instruction not supported on this GPU
 // GFX90A: flat_atomic_add_f64 v[0:1], v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x3e,0xdd,0x00,0x02,0x00,0x00]
 flat_atomic_add_f64 v[0:1], v[2:3] offset:4095 slc
 
 // NOT-GFX90A: error: instruction not supported on this GPU
 // GFX90A: flat_atomic_min_f64 v[0:1], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdd,0x00,0x02,0x00,0x00]
 flat_atomic_min_f64 v[0:1], v[2:3] offset:4095
 
 // NOT-GFX90A: error: instruction not supported on this GPU

 
 // GFX90A: flat_atomic_max_f64 v[0:1], v[0:1], v[2:3] glc ; encoding: [0x00,0x00,0x45,0xdd,0x00,0x02,0x00,0x00]
 // NOT-GFX90A: error: instruction not supported on this GPU
 flat_atomic_max_f64 v[0:1], v[0:1], v[2:3] glc
 
 // GFX90A: flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] glc ; encoding: [0x00,0x00,0x41,0xdd,0x00,0x02,0x00,0x00]
 // NOT-GFX90A: error: instruction not supported on this GPU
 flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] glc
+
+// GFX90A: global_atomic_add  v[2:3], v5, off scc  ; encoding: [0x00,0x80,0x08,0xdf,0x02,0x05,0x7f,0x00]
+// NOT-GFX90A: error: failed parsing operand.
+global_atomic_add v[2:3], v5, off scc
+
+// GFX90A: global_atomic_add_f32  v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x35,0xdd,0x00,0x02,0x7f,0x00]
+// GFX908: error: operands are not valid for this GPU or mode
+// GFX1010: error: instruction not supported on this GPU
+global_atomic_add_f32 v0, v[0:1], v2, off glc
+
+// GFX90A: global_atomic_add_f32  v[0:1], v2, off  ; encoding: [0x00,0x80,0x34,0xdd,0x00,0x02,0x7f,0x00]
+// GFX1010: error: instruction not supported on this GPU
+global_atomic_add_f32 v[0:1], v2, off
+
+// GFX90A: global_atomic_add_f32  v0, v2, s[0:1]   ; encoding: [0x00,0x80,0x34,0xdd,0x00,0x02,0x00,0x00]
+// GFX1010: error: instruction not supported on this GPU
+global_atomic_add_f32 v0, v2, s[0:1]
+
+// GFX90A: global_atomic_add_f32  v1, v0, v2, s[0:1] glc
+// GFX908: error: operands are not valid for this GPU or mode
+// GFX1010: error: instruction not supported on this GPU
+global_atomic_add_f32 v1, v0, v2, s[0:1] glc ; encoding: [0x00,0x80,0x35,0xdd,0x00,0x02,0x00,0x01]
+
+// GFX908: error: operands are not valid for this GPU or mode
+// GFX1010: error: instruction not supported on this GPU
+// GFX90A: global_atomic_pk_add_f16  v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x39,0xdd,0x00,0x02,0x7f,0x00]
+global_atomic_pk_add_f16 v0, v[0:1], v2, off glc

llvm/test/MC/AMDGPU/gfx90a_err.s

 image_sample_cl v[0:3], v[0:1], s[4:11], s[16:19] dmask:0xf
 // GFX90A: error: instruction not supported on this GPU
 
 image_sample_cd v[0:3], v[0:1], s[4:11], s[16:19] dmask:0xf
 // GFX90A: error: instruction not supported on this GPU
 
 image_sample_b v[0:3], v[0:1], s[4:11], s[16:19] dmask:0xf
 // GFX90A: error: instruction not supported on this GPU
+
+global_atomic_add_f32 v0, v[0:1], v2, off glc scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_add_f32 v[0:1], v2, off scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_add_f32 v0, v2, s[0:1] scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_add_f32 v1, v0, v2, s[0:1] glc scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_pk_add_f16 v0, v[0:1], v2, off glc scc
+// GFX90A: error: invalid operand for instruction
+
+flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] glc scc
+// GFX90A: error: invalid operand for instruction
+
+flat_atomic_add_f64 v[0:1], v[2:3] scc
+// GFX90A: error: invalid operand for instruction
+
+flat_atomic_min_f64 v[0:1], v[2:3] scc
+// GFX90A: error: invalid operand for instruction
+
+flat_atomic_max_f64 v[0:1], v[2:3] scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_add_f64 v[0:1], v[2:3], off scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_min_f64 v[0:1], v[2:3], off scc
+// GFX90A: error: invalid operand for instruction
+
+global_atomic_max_f64 v[0:1], v[2:3], off scc
+// GFX90A: error: invalid operand for instruction

llvm/test/MC/Disassembler/AMDGPU/gfx90a_dasm_features.txt

 
 # GFX908: flat_load_dword v0, v[0:1] glc ; encoding: [0x00,0x00,0x51,0xde,0x00,0x00,0x00,0x00]
 # GFX90A: flat_load_dword v0, v[0:1] glc scc ; encoding: [0x00,0x00,0x51,0xde,0x00,0x00,0x00,0x00]
 0x00,0x00,0x51,0xde,0x00,0x00,0x00,0x00
 
 # GFX90A: flat_atomic_add_f64 v[0:1], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x3c,0xdd,0x00,0x02,0x00,0x00]
 0xff,0x0f,0x3c,0xdd,0x00,0x02,0x00,0x00
 
-# GFX90A: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc scc ; encoding: [0xff,0x0f,0x3d,0xdf,0x00,0x02,0x00,0x00]
-0xff,0x0f,0x3d,0xdf,0x00,0x02,0x00,0x00
+# GFX90A: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x3d,0xdd,0x00,0x02,0x00,0x00]
+0xff,0x0f,0x3d,0xdd,0x00,0x02,0x00,0x00
 
 # GFX90A: flat_atomic_add_f64 v[254:255], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x3c,0xdd,0xfe,0x02,0x00,0x00]
 0xff,0x0f,0x3c,0xdd,0xfe,0x02,0x00,0x00
 
 # GFX90A: flat_atomic_add_f64 v[0:1], v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x3c,0xdd,0x00,0xfe,0x00,0x00]
 0xff,0x0f,0x3c,0xdd,0x00,0xfe,0x00,0x00
 
 # GFX90A: flat_atomic_add_f64 v[0:1], v[2:3] ; encoding: [0x00,0x00,0x3c,0xdd,0x00,0x02,0x00,0x00]