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Differential D98078

[AIX][TLS] Generate 64-bit general-dynamic access code sequence
ClosedPublic

Authored by lei on Mar 5 2021, 2:19 PM.

Details

Reviewers
nemanjai
sfertile
daltenty
power-llvm-team
Commits
rG535a4192a9d1: [AIX][TLS] Generate 64-bit general-dynamic access code sequence
Summary

Add support for the TLS general dynamic access model to assembly
files on AIX 64-bit.

Diff Detail

Event Timeline

lei created this revision.Mar 5 2021, 2:19 PM
Herald added a subscriber: hiraditya. · View Herald TranscriptMar 5 2021, 2:19 PM
lei requested review of this revision.Mar 5 2021, 2:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 5 2021, 2:19 PM
Harbormaster completed remote builds in B92397: Diff 328645.Mar 5 2021, 2:20 PM
lei added a parent revision: D97948: [AIX][TLS] Generate 32-bit general-dynamic access code sequence.Mar 5 2021, 2:40 PM
sfertile accepted this revision.Mar 8 2021, 12:42 PM

LGTM.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td
1305

Real minor nit: should we say X3/X4 instead of R3/R4 since that's the 64-bit gprs naming convention internally?

This revision is now accepted and ready to land.Mar 8 2021, 12:42 PM
This revision was landed with ongoing or failed builds.Mar 8 2021, 2:41 PM
Closed by commit rG535a4192a9d1: [AIX][TLS] Generate 64-bit general-dynamic access code sequence (authored by lei). · Explain Why
This revision was automatically updated to reflect the committed changes.
lei added a commit: rG535a4192a9d1: [AIX][TLS] Generate 64-bit general-dynamic access code sequence.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
4 lines
3 lines
23 lines
10 lines
test/
CodeGen/
PowerPC/
315 lines
322 lines
323 lines

Diff 328645

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Show First 20 Lines • Show All 1,149 Lines • ▼ Show 20 Lines EmitToStreamer(*OutStreamer,
.addExpr(SymGotTlsGD)); .addExpr(SymGotTlsGD));
return; return;
} }
case PPC::GETtlsADDR: case PPC::GETtlsADDR:
// Transform: %x3 = GETtlsADDR %x3, @sym // Transform: %x3 = GETtlsADDR %x3, @sym
// Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd) // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
case PPC::GETtlsADDRPCREL: case PPC::GETtlsADDRPCREL:
case PPC::GETtlsADDR32AIX: case PPC::GETtlsADDR32AIX:
// Transform: %r3 = GETtlsADDR32AIX %r3, %r4 case PPC::GETtlsADDR64AIX:
// Transform: %r3 = GETtlsADDRNNAIX %r3, %r4 (for NN == 32/64).
// Into: BLA .__tls_get_addr() // Into: BLA .__tls_get_addr()
// Unlike on Linux, there is no symbol or relocation needed for this call. // Unlike on Linux, there is no symbol or relocation needed for this call.
case PPC::GETtlsADDR32: { case PPC::GETtlsADDR32: {
// Transform: %r3 = GETtlsADDR32 %r3, @sym // Transform: %r3 = GETtlsADDR32 %r3, @sym
// Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD); EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD);
return; return;
} }
▲ Show 20 Lines • Show All 1,140 Lines • ▼ Show 20 Linesbool PPCAIXAsmPrinter::doInitialization(Module &M) {
return Result; return Result;
} }
void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) { void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: default:
break; break;
case PPC::GETtlsADDR64AIX:
case PPC::GETtlsADDR32AIX: { case PPC::GETtlsADDR32AIX: {
// The reference to .__tls_get_addr is unknown to the assembler // The reference to .__tls_get_addr is unknown to the assembler
// so we need to emit an external symbol reference. // so we need to emit an external symbol reference.
MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(".__tls_get_addr"); MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(".__tls_get_addr");
ExtSymSDNodeSymbols.insert(TlsGetAddr); ExtSymSDNodeSymbols.insert(TlsGetAddr);
break; break;
} }
case PPC::BL8: case PPC::BL8:
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,125 Lines • ▼ Show 20 Lines
SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op, SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
if (DAG.getTarget().useEmulatedTLS()) if (DAG.getTarget().useEmulatedTLS())
report_fatal_error("Emulated TLS is not yet supported on AIX"); report_fatal_error("Emulated TLS is not yet supported on AIX");
if (Subtarget.isPPC64())
report_fatal_error("TLS is not yet supported on AIX PPC64");
SDLoc dl(GA); SDLoc dl(GA);
const GlobalValue *GV = GA->getGlobal(); const GlobalValue *GV = GA->getGlobal();
EVT PtrVT = getPointerTy(DAG.getDataLayout()); EVT PtrVT = getPointerTy(DAG.getDataLayout());
// The general-dynamic model is the only access model supported for now, so // The general-dynamic model is the only access model supported for now, so
// all the GlobalTLSAddress nodes are lowered with this model. // all the GlobalTLSAddress nodes are lowered with this model.
// We need to generate two TOC entries, one for the variable offset, one for // We need to generate two TOC entries, one for the variable offset, one for
// the region handle. The global address for the TOC entry of the region // the region handle. The global address for the TOC entry of the region
▲ Show 20 Lines • Show All 13,515 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Show First 20 Lines • Show All 1,295 Lines • ▼ Show 20 Lines
def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">;
// LR8 is a true define, while the rest of the Defs are clobbers. X3 is // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
// explicitly defined when this op is created, so not mentioned here. // explicitly defined when this op is created, so not mentioned here.
let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">;
let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">;
// On AIX, the call to __tls_get_addr needs two inputs in R3/R4 for the
sfertileUnsubmitted
Not Done
ReplyInline Actions

Real minor nit: should we say X3/X4 instead of R3/R4 since that's the 64-bit gprs naming convention internally?

sfertile: Real minor nit: should we say `X3/X4` instead of `R3/R4` since that's the 64-bit gprs naming…
// offset and region handle respectively. The call is not followed by a nop
// so we don't need to mark it with a size of 8 bytes. Finally, the assembly
// manual mentions this exact set of registers as the clobbered set, others
// are guaranteed not to be clobbered.
let Defs = [X0,X4,X5,X11,LR8,CR0] in
def GETtlsADDR64AIX :
PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle),
"GETtlsADDR64AIX",
[(set i64:$rD,
(PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64;
} }
// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8
// are true defines while the rest of the Defs are clobbers. // are true defines while the rest of the Defs are clobbers.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
in in
def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
Show All 9 Linesdef ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
[(set i64:$rD, [(set i64:$rD,
(PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDItlsldL", "#ADDItlsldL",
[(set i64:$rD, [(set i64:$rD,
(PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
// This pseudo is expanded to two copies to put the variable offset in R4 and
// the region handle in R3 and GETtlsADDR64AIX.
def TLSGDAIX8 :
PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle),
"#TLSGDAIX8",
[(set i64:$rD,
(PPCTlsgdAIX i64:$offset, i64:$handle))]>;
// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8
// are true defines, while the rest of the Defs are clobbers. // are true defines, while the rest of the Defs are clobbers.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
in in
def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
(ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
"#ADDItlsldLADDR", "#ADDItlsldLADDR",
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Linesdef : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
(ADDIS8 $in, tglobaladdr:$g)>; (ADDIS8 $in, tglobaladdr:$g)>;
def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
(ADDIS8 $in, tconstpool:$g)>; (ADDIS8 $in, tconstpool:$g)>;
def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
(ADDIS8 $in, tjumptable:$g)>; (ADDIS8 $in, tjumptable:$g)>;
def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
(ADDIS8 $in, tblockaddress:$g)>; (ADDIS8 $in, tblockaddress:$g)>;
// AIX 64-bit small code model TLS access.
def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)),
(i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>;
// Patterns to match r+r indexed loads and stores for // Patterns to match r+r indexed loads and stores for
// addresses without at least 4-byte alignment. // addresses without at least 4-byte alignment.
def : Pat<(i64 (NonDSFormSextLoadi32 xoaddr:$src)), def : Pat<(i64 (NonDSFormSextLoadi32 xoaddr:$src)),
(LWAX xoaddr:$src)>; (LWAX xoaddr:$src)>;
def : Pat<(i64 (NonDSFormLoad xoaddr:$src)), def : Pat<(i64 (NonDSFormLoad xoaddr:$src)),
(LDX xoaddr:$src)>; (LDX xoaddr:$src)>;
def : Pat<(NonDSFormStore i64:$rS, xoaddr:$dst), def : Pat<(NonDSFormStore i64:$rS, xoaddr:$dst),
(STDX $rS, xoaddr:$dst)>; (STDX $rS, xoaddr:$dst)>;
Show All 39 Lines

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bool processBlock(MachineBasicBlock &MBB) {
I != IE;) { I != IE;) {
MachineInstr &MI = *I; MachineInstr &MI = *I;
IsPCREL = isPCREL(MI); IsPCREL = isPCREL(MI);
if (MI.getOpcode() != PPC::ADDItlsgdLADDR && if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
MI.getOpcode() != PPC::ADDItlsldLADDR && MI.getOpcode() != PPC::ADDItlsldLADDR &&
MI.getOpcode() != PPC::ADDItlsgdLADDR32 && MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
MI.getOpcode() != PPC::ADDItlsldLADDR32 && MI.getOpcode() != PPC::ADDItlsldLADDR32 &&
MI.getOpcode() != PPC::TLSGDAIX && !IsPCREL) { MI.getOpcode() != PPC::TLSGDAIX &&
MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) {
// Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
// as scheduling fences, we skip creating fences if we already // as scheduling fences, we skip creating fences if we already
// have existing ADJCALLSTACKDOWN/UP to avoid nesting, // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
// which causes verification error with -verify-machineinstrs. // which causes verification error with -verify-machineinstrs.
if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
NeedFence = false; NeedFence = false;
else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
NeedFence = true; NeedFence = true;
Show All 30 Lines bool processBlock(MachineBasicBlock &MBB) {
case PPC::ADDItlsgdLADDR32: case PPC::ADDItlsgdLADDR32:
Opc1 = PPC::ADDItlsgdL32; Opc1 = PPC::ADDItlsgdL32;
Opc2 = PPC::GETtlsADDR32; Opc2 = PPC::GETtlsADDR32;
break; break;
case PPC::ADDItlsldLADDR32: case PPC::ADDItlsldLADDR32:
Opc1 = PPC::ADDItlsldL32; Opc1 = PPC::ADDItlsldL32;
Opc2 = PPC::GETtlsldADDR32; Opc2 = PPC::GETtlsldADDR32;
break; break;
case PPC::TLSGDAIX8:
// TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only
// set Opc2 here.
Opc2 = PPC::GETtlsADDR64AIX;
break;
case PPC::TLSGDAIX: case PPC::TLSGDAIX:
// TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only // TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only
// set Opc2 here. // set Opc2 here.
Opc2 = PPC::GETtlsADDR32AIX; Opc2 = PPC::GETtlsADDR32AIX;
break; break;
case PPC::PADDI8pc: case PPC::PADDI8pc:
assert(IsPCREL && "Expecting General/Local Dynamic PCRel"); assert(IsPCREL && "Expecting General/Local Dynamic PCRel");
Opc1 = PPC::PADDI8pc; Opc1 = PPC::PADDI8pc;
Show All 15 Lines bool processBlock(MachineBasicBlock &MBB) {
// The ADDItls* instruction is the first instruction in the // The ADDItls* instruction is the first instruction in the
// repair range. // repair range.
MachineBasicBlock::iterator First = I; MachineBasicBlock::iterator First = I;
--First; --First;
if (IsAIX) { if (IsAIX) {
// The variable offset and region handle are copied in r4 and r3. The // The variable offset and region handle are copied in r4 and r3. The
// copies are followed by the GETtlsADDR32AIX instruction. // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
.addReg(MI.getOperand(2).getReg()); .addReg(MI.getOperand(2).getReg());
BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4); BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
} else { } else {
MachineInstr *Addi; MachineInstr *Addi;
if (IsPCREL) { if (IsPCREL) {
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-tls-checks.ll

  • This file was deleted.
; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s - 2>&1 | FileCheck %s
; CHECK: TLS is not yet supported on AIX PPC64
@tls1 = thread_local global i32 0, align 4
define i32* @getTls1Addr() {
entry:
ret i32* @tls1
}

llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL32 ; RUN: --check-prefix=SMALL32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE32 ; RUN: | FileCheck %s --check-prefix=LARGE32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL64
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE64
@TGInit = thread_local global double 1.000000e+00, align 8 @TGInit = thread_local global double 1.000000e+00, align 8
@TWInit = weak thread_local global double 1.000000e+00, align 8 @TWInit = weak thread_local global double 1.000000e+00, align 8
@GInit = global double 1.000000e+00, align 8 @GInit = global double 1.000000e+00, align 8
@TGUninit = thread_local global double 0.000000e+00, align 8 @TGUninit = thread_local global double 0.000000e+00, align 8
@TIInit = internal thread_local global double 1.000000e+00, align 8 @TIInit = internal thread_local global double 1.000000e+00, align 8
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
Show All 22 Lines
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTGUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTGUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store double %Val, double* @TGUninit, align 8 store double %Val, double* @TGUninit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGInit(double %Val) #0 { define void @storesTGInit(double %Val) #0 {
; SMALL32-LABEL: storesTGInit: ; SMALL32-LABEL: storesTGInit:
Show All 20 Lines
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store double %Val, double* @TGInit, align 8 store double %Val, double* @TGInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIInit(double %Val) #0 { define void @storesTIInit(double %Val) #0 {
; SMALL32-LABEL: storesTIInit: ; SMALL32-LABEL: storesTIInit:
Show All 20 Lines
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTIInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTIInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store double %Val, double* @TIInit, align 8 store double %Val, double* @TIInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWInit(double %Val) #0 { define void @storesTWInit(double %Val) #0 {
; SMALL32-LABEL: storesTWInit: ; SMALL32-LABEL: storesTWInit:
Show All 20 Lines
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTWInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTWInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store double %Val, double* @TWInit, align 8 store double %Val, double* @TWInit, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define double @loadsTGUninit() #1 { define double @loadsTGUninit() #1 {
; SMALL32-LABEL: loadsTGUninit: ; SMALL32-LABEL: loadsTGUninit:
Show All 27 Lines
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTGUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTGUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load double, double* @TGUninit, align 8 %0 = load double, double* @TGUninit, align 8
%1 = load double, double* @GInit, align 8 %1 = load double, double* @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load double, double* @TGInit, align 8 %0 = load double, double* @TGInit, align 8
%1 = load double, double* @GInit, align 8 %1 = load double, double* @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTIInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTIInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load double, double* @TIInit, align 8 %0 = load double, double* @TIInit, align 8
%1 = load double, double* @GInit, align 8 %1 = load double, double* @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTWInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTWInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load double, double* @TWInit, align 8 %0 = load double, double* @TWInit, align 8
%1 = load double, double* @GInit, align 8 %1 = load double, double* @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; TOC entry checks ; TOC entry checks
Show All 33 Lines
; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL] ; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]
; LARGE32-LABEL: L..C6: ; LARGE32-LABEL: L..C6:
; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m
; LARGE32-LABEL: L..C7: ; LARGE32-LABEL: L..C7:
; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL] ; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]
; LARGE32-LABEL: L..C8: ; LARGE32-LABEL: L..C8:
; LARGE32-NEXT: .tc GInit[TE],GInit[RW] ; LARGE32-NEXT: .tc GInit[TE],GInit[RW]
; SMALL64-LABEL: .toc
; SMALL64-LABEL: L..C0:
; SMALL64-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
; SMALL64-LABEL: L..C1:
; SMALL64-NEXT: .tc TGUninit[TC],TGUninit[TL]
; SMALL64-LABEL: L..C2:
; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m
; SMALL64-LABEL: L..C3:
; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]
; SMALL64-LABEL: L..C4:
; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m
; SMALL64-LABEL: L..C5:
; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]
; SMALL64-LABEL: L..C6:
; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m
; SMALL64-LABEL: L..C7:
; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]
; SMALL64-LABEL: L..C8:
; SMALL64-NEXT: .tc GInit[TC],GInit[RW]
; LARGE64-LABEL: .toc
; LARGE64-LABEL: L..C0:
; LARGE64-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
; LARGE64-LABEL: L..C1:
; LARGE64-NEXT: .tc TGUninit[TE],TGUninit[TL]
; LARGE64-LABEL: L..C2:
; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m
; LARGE64-LABEL: L..C3:
; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]
; LARGE64-LABEL: L..C4:
; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m
; LARGE64-LABEL: L..C5:
; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]
; LARGE64-LABEL: L..C6:
; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m
; LARGE64-LABEL: L..C7:
; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]
; LARGE64-LABEL: L..C8:
; LARGE64-NEXT: .tc GInit[TE],GInit[RW]
attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL32 ; RUN: --check-prefix=SMALL32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE32 ; RUN: | FileCheck %s --check-prefix=LARGE32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL64
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE64
@TGInit = thread_local global i32 1, align 4 @TGInit = thread_local global i32 1, align 4
@GInit = global i32 1, align 4 @GInit = global i32 1, align 4
@TGUninit = thread_local global i32 0, align 4 @TGUninit = thread_local global i32 0, align 4
@TIUninit = internal thread_local global i32 0, align 4 @TIUninit = internal thread_local global i32 0, align 4
@TWUninit = weak thread_local global i32 0, align 4 @TWUninit = weak thread_local global i32 0, align 4
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
Show All 24 Lines
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTGUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTGUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, i32* @TGUninit, align 4 store i32 %Val, i32* @TGUninit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGInit(i32 %Val) #0 { define void @storesTGInit(i32 %Val) #0 {
; SMALL32-LABEL: storesTGInit: ; SMALL32-LABEL: storesTGInit:
Show All 22 Lines
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, i32* @TGInit, align 4 store i32 %Val, i32* @TGInit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIUninit(i32 %Val) #0 { define void @storesTIUninit(i32 %Val) #0 {
; SMALL32-LABEL: storesTIUninit: ; SMALL32-LABEL: storesTIUninit:
Show All 22 Lines
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTIUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTIUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, i32* @TIUninit, align 4 store i32 %Val, i32* @TIUninit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWUninit(i32 %Val) #0 { define void @storesTWUninit(i32 %Val) #0 {
; SMALL32-LABEL: storesTWUninit: ; SMALL32-LABEL: storesTWUninit:
Show All 22 Lines
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTWUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTWUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, i32* @TWUninit, align 4 store i32 %Val, i32* @TWUninit, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i32 @loadsTGUninit() #1 { define i32 @loadsTGUninit() #1 {
; SMALL32-LABEL: loadsTGUninit: ; SMALL32-LABEL: loadsTGUninit:
Show All 27 Lines
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTGUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTGUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, i32* @TGUninit, align 4 %0 = load i32, i32* @TGUninit, align 4
%1 = load i32, i32* @GInit, align 4 %1 = load i32, i32* @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, i32* @TGInit, align 4 %0 = load i32, i32* @TGInit, align 4
%1 = load i32, i32* @GInit, align 4 %1 = load i32, i32* @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTIUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTIUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, i32* @TIUninit, align 4 %0 = load i32, i32* @TIUninit, align 4
%1 = load i32, i32* @GInit, align 4 %1 = load i32, i32* @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 29 Lines
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTWUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTWUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, i32* @TWUninit, align 4 %0 = load i32, i32* @TWUninit, align 4
%1 = load i32, i32* @GInit, align 4 %1 = load i32, i32* @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; TOC entry checks ; TOC entry checks
Show All 33 Lines
; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL] ; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]
; LARGE32-LABEL: L..C6: ; LARGE32-LABEL: L..C6:
; LARGE32-NEXT: .tc .TWUninit[TE],TWUninit[TL]@m ; LARGE32-NEXT: .tc .TWUninit[TE],TWUninit[TL]@m
; LARGE32-LABEL: L..C7: ; LARGE32-LABEL: L..C7:
; LARGE32-NEXT: .tc TWUninit[TE],TWUninit[TL] ; LARGE32-NEXT: .tc TWUninit[TE],TWUninit[TL]
; LARGE32-LABEL: L..C8: ; LARGE32-LABEL: L..C8:
; LARGE32-NEXT: .tc GInit[TE],GInit[RW] ; LARGE32-NEXT: .tc GInit[TE],GInit[RW]
; SMALL64-LABEL: .toc
; SMALL64-LABEL: L..C0:
; SMALL64-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
; SMALL64-LABEL: L..C1:
; SMALL64-NEXT: .tc TGUninit[TC],TGUninit[TL]
; SMALL64-LABEL: L..C2:
; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m
; SMALL64-LABEL: L..C3:
; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]
; SMALL64-LABEL: L..C4:
; SMALL64-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m
; SMALL64-LABEL: L..C5:
; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]
; SMALL64-LABEL: L..C6:
; SMALL64-NEXT: .tc .TWUninit[TC],TWUninit[TL]@m
; SMALL64-LABEL: L..C7:
; SMALL64-NEXT: .tc TWUninit[TC],TWUninit[TL]
; SMALL64-LABEL: L..C8:
; SMALL64-NEXT: .tc GInit[TC],GInit[RW]
; LARGE64-LABEL: .toc
; LARGE64-LABEL: L..C0:
; LARGE64-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
; LARGE64-LABEL: L..C1:
; LARGE64-NEXT: .tc TGUninit[TE],TGUninit[TL]
; LARGE64-LABEL: L..C2:
; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m
; LARGE64-LABEL: L..C3:
; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]
; LARGE64-LABEL: L..C4:
; LARGE64-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m
; LARGE64-LABEL: L..C5:
; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]
; LARGE64-LABEL: L..C6:
; LARGE64-NEXT: .tc .TWUninit[TE],TWUninit[TL]@m
; LARGE64-LABEL: L..C7:
; LARGE64-NEXT: .tc TWUninit[TE],TWUninit[TL]
; LARGE64-LABEL: L..C8:
; LARGE64-NEXT: .tc GInit[TE],GInit[RW]
attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL32 ; RUN: --check-prefix=SMALL32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE32 ; RUN: | FileCheck %s --check-prefix=LARGE32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL64
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE64
@TGInit = thread_local global i64 1, align 8 @TGInit = thread_local global i64 1, align 8
@TWInit = weak thread_local global i64 1, align 8 @TWInit = weak thread_local global i64 1, align 8
@GInit = global i64 1, align 8 @GInit = global i64 1, align 8
@TIUninit = internal thread_local global i64 0, align 8 @TIUninit = internal thread_local global i64 0, align 8
@TIInit = internal thread_local global i64 1, align 8 @TIInit = internal thread_local global i64 1, align 8
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
Show All 28 Lines
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, i64* @TGInit, align 8 store i64 %Val, i64* @TGInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIUninit(i64 %Val) #0 { define void @storesTIUninit(i64 %Val) #0 {
; SMALL32-LABEL: storesTIUninit: ; SMALL32-LABEL: storesTIUninit:
Show All 26 Lines
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTIUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTIUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, i64* @TIUninit, align 8 store i64 %Val, i64* @TIUninit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIInit(i64 %Val) #0 { define void @storesTIInit(i64 %Val) #0 {
; SMALL32-LABEL: storesTIInit: ; SMALL32-LABEL: storesTIInit:
Show All 26 Lines
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTIInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTIInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, i64* @TIInit, align 8 store i64 %Val, i64* @TIInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWInit(i64 %Val) #0 { define void @storesTWInit(i64 %Val) #0 {
; SMALL32-LABEL: storesTWInit: ; SMALL32-LABEL: storesTWInit:
Show All 26 Lines
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr ; LARGE32-NEXT: bla .__tls_get_addr
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: storesTWInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: storesTWInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, i64* @TWInit, align 8 store i64 %Val, i64* @TWInit, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i64 @loadsTGInit() #1 { define i64 @loadsTGInit() #1 {
; SMALL32-LABEL: loadsTGInit: ; SMALL32-LABEL: loadsTGInit:
Show All 33 Lines
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, i64* @TGInit, align 8 %0 = load i64, i64* @TGInit, align 8
%1 = load i64, i64* @GInit, align 8 %1 = load i64, i64* @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 35 Lines
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTIUninit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTIUninit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, i64* @TIUninit, align 8 %0 = load i64, i64* @TIUninit, align 8
%1 = load i64, i64* @GInit, align 8 %1 = load i64, i64* @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 35 Lines
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTIInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTIInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, i64* @TIInit, align 8 %0 = load i64, i64* @TIInit, align 8
%1 = load i64, i64* @GInit, align 8 %1 = load i64, i64* @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
Show All 35 Lines
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
;
; SMALL64-LABEL: loadsTWInit:
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: bla .__tls_get_addr
; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr
;
; LARGE64-LABEL: loadsTWInit:
; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr
; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, i64* @TWInit, align 8 %0 = load i64, i64* @TWInit, align 8
%1 = load i64, i64* @GInit, align 8 %1 = load i64, i64* @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; TOC entry checks ; TOC entry checks
Show All 32 Lines
; LARGE32-LABEL: L..C5: ; LARGE32-LABEL: L..C5:
; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL] ; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]
; LARGE32-LABEL: L..C6: ; LARGE32-LABEL: L..C6:
; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m
; LARGE32-LABEL: L..C7: ; LARGE32-LABEL: L..C7:
; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL] ; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]
; LARGE32-LABEL: L..C8: ; LARGE32-LABEL: L..C8:
; LARGE32-NEXT: .tc GInit[TE],GInit[RW] ; LARGE32-NEXT: .tc GInit[TE],GInit[RW]
; SMALL64-LABEL: .toc
; SMALL64-LABEL: L..C0:
; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m
; SMALL64-LABEL: L..C1:
; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]
; SMALL64-LABEL: L..C2:
; SMALL64-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m
; SMALL64-LABEL: L..C3:
; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]
; SMALL64-LABEL: L..C4:
; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m
; SMALL64-LABEL: L..C5:
; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]
; SMALL64-LABEL: L..C6:
; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m
; SMALL64-LABEL: L..C7:
; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]
; SMALL64-LABEL: L..C8:
; SMALL64-NEXT: .tc GInit[TC],GInit[RW]
; LARGE64-LABEL: .toc
; LARGE64-LABEL: L..C0:
; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m
; LARGE64-LABEL: L..C1:
; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]
; LARGE64-LABEL: L..C2:
; LARGE64-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m
; LARGE64-LABEL: L..C3:
; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]
; LARGE64-LABEL: L..C4:
; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m
; LARGE64-LABEL: L..C5:
; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]
; LARGE64-LABEL: L..C6:
; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m
; LARGE64-LABEL: L..C7:
; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]
; LARGE64-LABEL: L..C8:
; LARGE64-NEXT: .tc GInit[TE],GInit[RW]
attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" } attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp