[X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and x86_tilezero_internal to X86InstrAMX.td

[pengfei]

llvm/lib/Target/X86/X86InstrAMX.td

51–53

Can we add patterns for the load and restore too?

98

extra space.

[LiuChen3]

llvm/lib/Target/X86/X86InstrAMX.td

51–53

load and store do some custom operation on the memory operand. For now I didn't find a good way to match it.

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

case Intrinsic::x86_tileloadd64_internal: {
                        Index,
                        Disp,
                        Segment,
                        Chain};
       CNode = CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
       ReplaceNode(Node, CNode);
       return;
     }
-
-    case Intrinsic::x86_tdpbssd_internal:
-    case Intrinsic::x86_tdpbsud_internal:
-    case Intrinsic::x86_tdpbusd_internal:
-    case Intrinsic::x86_tdpbuud_internal: {
-      if (!Subtarget->hasAMXINT8())
-        break;
-      SDValue Chain = Node->getOperand(0);
-      unsigned Opc;
-      switch (IntNo) {
-      case Intrinsic::x86_tdpbssd_internal: Opc = X86::PTDPBSSDV; break;
-      case Intrinsic::x86_tdpbsud_internal: Opc = X86::PTDPBSUDV; break;
-      case Intrinsic::x86_tdpbusd_internal: Opc = X86::PTDPBUSDV; break;
-      case Intrinsic::x86_tdpbuud_internal: Opc = X86::PTDPBUUDV; break;
-      default: llvm_unreachable("Impossible intrinsic");
-      }
-      SDValue Ops[] = {Node->getOperand(2),
-                       Node->getOperand(3),
-                       Node->getOperand(4),
-                       Node->getOperand(5),
-                       Node->getOperand(6),
-                       Node->getOperand(7),
-                       Chain};
-      MachineSDNode *CNode =
-          CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
-      ReplaceNode(Node, CNode);
-      return;
-    }
-    case Intrinsic::x86_tilezero_internal: {
-      if (!Subtarget->hasAMXTILE())
-        break;
-      unsigned Opc = X86::PTILEZEROV;
-      SDValue Chain = Node->getOperand(0);
-      SDValue Ops[] = {Node->getOperand(2), Node->getOperand(3), Chain};
-      MachineSDNode *CNode =
-          CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
-      ReplaceNode(Node, CNode);
-      return;
-    }
     }
     break;
   }
   case ISD::INTRINSIC_VOID: {
     unsigned IntNo = Node->getConstantOperandVal(1);
     switch (IntNo) {
     default: break;
     case Intrinsic::x86_sse3_monitor:

llvm/lib/Target/X86/X86InstrAMX.td

def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
                        (ins sibmem:$dst, TILE:$src),
                        "tilestored\t{$src, $dst|$dst, $src}", []>,
                        VEX, T8XS;
     def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
                      "tilezero\t$dst", []>,
                      VEX, T8XD;
 
     // Pseduo instruction for RA.
-    def PTILELOADDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
-                                                      GR16:$src2,
-                                                      opaquemem:$src3), []>;
+    def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
     def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
                                             GR16:$src2, opaquemem:$src3,
                                             TILE:$src4), []>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
-      def PTILEZEROV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
-                                                     GR16:$src2), []>;
+      def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
+                                [(set TILE:$dst, (int_x86_tilezero_internal
+                                  GR16:$src1, GR16:$src2))]>;
 
     let usesCustomInserter = 1 in {
       // Pseudo instructions, using immediates instead of tile registers.
       // To be translated to the actual instructions in X86ISelLowering.cpp
       def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
       def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
                                           sibmem:$src2), []>;
       def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
let Constraints = "$src1 = $dst" in {
       def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
                       "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
                       VEX_4V, T8PS;
     }
 
     // Pseduo instruction for RA.
     let Constraints = "$src4 = $dst" in {
-      def PTDPBSSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
+      def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
                               GR16:$src2, GR16:$src3, TILE:$src4,
-                              TILE:$src5, TILE:$src6), []>;
+                              TILE:$src5, TILE:$src6),
+                              [(set TILE: $dst,
+                              (int_x86_tdpbssd_internal GR16:$src1, GR16:$src2,
+                              GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
       def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
                               GR16:$src2, GR16:$src3, TILE:$src4,
-                              TILE:$src5, TILE:$src6), []>;
+                              TILE:$src5, TILE:$src6),
+                              [(set TILE: $dst,
+                              (int_x86_tdpbsud_internal GR16:$src1, GR16:$src2,
+                               GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
       def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
                               GR16:$src2, GR16:$src3, TILE:$src4,
-                              TILE:$src5, TILE:$src6), []>;
+                              TILE:$src5, TILE:$src6),
+                              [(set TILE: $dst,
+                              (int_x86_tdpbusd_internal GR16:$src1, GR16:$src2,
+                              GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
       def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
                               GR16:$src2, GR16:$src3, TILE:$src4,
-                              TILE:$src5, TILE:$src6), []>;
+                              TILE:$src5, TILE:$src6),
+                              [(set TILE: $dst,
+                              (int_x86_tdpbuud_internal GR16:$src1, GR16:$src2,
+                              GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
     }
 
     let usesCustomInserter = 1 in {
       // Pseudo instructions, using immediates instead of tile registers.
       // To be translated to the actual instructions in X86ISelLowering.cpp
       def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
                              u8imm:$src2, u8imm:$src3),
                              [(int_x86_tdpbssd timm:$src1,