Adds support for ARM hardware watchpoints

[omjavaid]

Summary

This patch adds support for setting hardware watchpoints on arm.

There are still some unfixed issues which results in lldb not hitting hardware watchpoints set/clear functions in NativeLinuxRegisterContextLinus_arm.

I am presenting this code for review meanwhile I ll fix the reminaing issues.

I have added hardware breakpoint set/clear functions for future use.

[omjavaid]

Adding full context diff.

[clayborg]

Looks good.

[tberghammer]

Generally looks good but please fix the broken condition (see inline)

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

775–776

This condition is always true. I am not sure what you try to check but the current condition is definitely broken.

source/Plugins/Process/Linux/ProcessMonitor.cpp

733

Please change it to an enum or at least add a comment for what the values mean.

[omjavaid]

Updated patch with recent changes incorporated.

[tberghammer]

I tried to apply this patch to TOT but it wasn't compiling because NativeProcessLinux::ReadHardwareDebugInfo (and a few similar function) is missing. You should create an operation for it in NativeRegsiterContextLinux_arm and execute it through NativeProcessLinux::DoOperation.

Other note is that you made changes in Linux/ProcessMonitor.{h,cpp}. I have no problem with it, but it isn't used at the moment and hopefully it will be deleted within a few month as that one is only used when debugging an application without lldb-server what is already deprecated on Linux.

[omjavaid]

Made corrections in previous patch.

@tamas
Kindly check build now. Thanks!

[tberghammer]

It is compiling and the concepts are looking good, but when I tried it out I haven't managed to hit any hardware watchpoint.

I tried to verify that PTRACE_SETHBPREGS works as intended but when I did a PTRACE_GETHBPREGS immediately after it I read back a different value for the control register then the one I written there before (tested with Android 5.1 on a Nexus 5)

[omjavaid]

This updated patches correct problems in arm hardware watchpoint support patch posted earlier.

This patch has been tested on samsung chromebook (ARM - Linux) and PandaBoard using basic watchpoint test application.

Also it was tested on Nexus 7 Android device.

On chromebook linux we are able to set and clear all types of watchpoints but on android we end up getting a watchpoint packet error because we are not able to call hardware watchpoint ptrace functions successfully.

I still dont have a android device on me that has hardware watchpoints enable but fact that this functionality now works on linux means that we should get this into our source code.

I am trying to write a test to check hardware watchpoint capabilities of a platform so we are pretty sure what works on which platform.

Is this good to commit?

[tberghammer]

Looks good with a few minor comments inline

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

397

(nit): Please initialize these variables

434

(nit): Indentation

444

Please check for error

484

I think a return true is missing here

484

Please check for error

525

(nit): Please initialize

599

Please check for error

640

Please check for error

673

Please check for error

include/lldb/Host/linux/Ptrace.h

#ifndef ARCH_GET_FS
     #define ARCH_SET_GS 0x1001
     #define ARCH_SET_FS 0x1002
     #define ARCH_GET_FS 0x1003
     #define ARCH_GET_GS 0x1004
 #endif
 
 #define LLDB_PTRACE_NT_ARM_TLS  0x401           // ARM TLS register
 
+#if defined (__arm__) || defined (__thumb__)
+#ifndef PTRACE_GETHBPREGS
+  #define PTRACE_GETHBPREGS 29
+  #define PTRACE_SETHBPREGS 30
+#endif
+#if !defined(PTRACE_TYPE_ARG3)
+  #define PTRACE_TYPE_ARG3 void *
+#endif
+#if !defined(PTRACE_TYPE_ARG4)
+  #define PTRACE_TYPE_ARG4 void *
+#endif
+#endif
+
 #endif // liblldb_Host_linux_Ptrace_h_

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h

protected:
         GetGPRBuffer() override { return &m_gpr_arm; }
 
         void*
         GetFPRBuffer() override { return &m_fpr; }
 
         size_t
         GetFPRSize() override { return sizeof(m_fpr); }
 
+        //------------------------------------------------------------------
+        // Hardware breakpoints/watchpoint mangement functions
+        //------------------------------------------------------------------
+
+        uint32_t
+        SetHardwareBreakpoint (lldb::addr_t addr, size_t size) override;
+
+        bool
+        ClearHardwareBreakpoint (uint32_t hw_idx) override;
+
+        uint32_t
+        NumSupportedHardwareWatchpoints () override;
+
+        uint32_t
+        SetHardwareWatchpoint (lldb::addr_t addr, size_t size, uint32_t watch_flags) override;
+
+        bool
+        ClearHardwareWatchpoint (uint32_t hw_index) override;
+
+        Error
+        ClearAllHardwareWatchpoints () override;
+
+        Error
+        GetWatchpointHitIndex(uint32_t &wp_index, lldb::addr_t trap_addr) override;
+
+        lldb::addr_t
+        GetWatchpointAddress (uint32_t wp_index) override;
+
+        bool
+        HardwareSingleStep (bool enable) override;
+
+        uint32_t
+        GetWatchpointSize(uint32_t wp_index);
+
+        bool
+        WatchpointIsEnabled(uint32_t wp_index);
+
     private:
         struct RegInfo
         {
             uint32_t num_registers;
             uint32_t num_gpr_registers;
             uint32_t num_fpr_registers;
 
             uint32_t last_gpr;
private:
                 QReg     q[16];  // the 128-bit NEON registers
                 } floats;
             uint32_t fpscr;
         };
 
         uint32_t m_gpr_arm[k_num_gpr_registers_arm];
         RegInfo  m_reg_info;
         FPU m_fpr; 
     
+        // Debug register info for hardware breakpoints and watchpoints management.
+        struct DREG
+        {
+            lldb::addr_t address;// Breakpoint/watchpoint address value
+            uint32_t control;    // Breakpoint/watchpoint control value
+            uint32_t refcount;   // Used for enable/disable and refernce count
+        };
+
+        struct DREG m_hbr_regs[16];  // Arm native linux hardware breakpoints
+        struct DREG m_hwp_regs[16];  // Arm native linux hardware watchpoints
+
+        uint32_t m_max_hwp_supported;
+        uint32_t m_max_hbp_supported;
+        bool m_refresh_hwdebug_info;
+
         bool
         IsGPR(unsigned reg) const;
 
         bool
         IsFPR(unsigned reg) const;
     };
 
 } // namespace process_linux
 } // namespace lldb_private
 
 #endif // #ifndef lldb_NativeRegisterContextLinux_arm_h
 
 #endif // defined(__arm__)

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

 #if defined(__arm__)
 
 #include "NativeRegisterContextLinux_arm.h"
 
 #include "lldb/Core/DataBufferHeap.h"
 #include "lldb/Core/Error.h"
 #include "lldb/Core/RegisterValue.h"
 
+#include "lldb/Core/StreamString.h"
+#include "lldb/Core/Log.h"
+
 #include "Plugins/Process/Utility/RegisterContextLinux_arm.h"
 
 #define REG_CONTEXT_SIZE (GetGPRSize() + sizeof (m_fpr))
 
 using namespace lldb;
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
switch (target_arch.GetMachine())
             break;
         default:
             assert(false && "Unhandled target architecture.");
             break;
     }
 
     ::memset(&m_fpr, 0, sizeof (m_fpr));
     ::memset(&m_gpr_arm, 0, sizeof (m_gpr_arm));
+    ::memset(&m_hbr_regs, 0, sizeof (m_hbr_regs));
+    ::memset(&m_hwp_regs, 0, sizeof (m_hwp_regs));
+
+    // 16 is just a maximum value, query hardware for actual watchpoint count
+    m_max_hwp_supported = 16;
+    m_max_hbp_supported = 16;
+    m_refresh_hwdebug_info = true;
 }
 
 uint32_t
 NativeRegisterContextLinux_arm::GetRegisterSetCount () const
 {
     return k_num_register_sets;
 }
 

 }
 
 bool
 NativeRegisterContextLinux_arm::IsFPR(unsigned reg) const
 {
     return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
 }
 
+uint32_t
+NativeRegisterContextLinux_arm::SetHardwareBreakpoint (lldb::addr_t addr, size_t size)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
+    if (!process_sp)
+        return false;
+
+    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
+    // Check if our hardware breakpoint and watchpoint information is updated.
+    if (m_refresh_hwdebug_info)
+    {
+        process_p->ReadHardwareDebugInfo (m_thread.GetID (), m_max_hwp_supported,
+                                          m_max_hbp_supported);
+        m_refresh_hwdebug_info = false;
+    }
+
+    uint32_t control_value, bp_index;
+
+    // Check if size has a valid hardware breakpoint length.
+    // Thumb instructions are 2-bytes but we have no way here to determine
+    // if target address is a thumb or arm instruction.
+    // TODO: Add support for setting thumb mode hardware breakpoints
+    if (size != 4 && size != 2)
+        return LLDB_INVALID_INDEX32;
+
+    // Setup control value
+    // Make the byte_mask into a valid Byte Address Select mask
+    control_value = 0xfu << 5;
+
+    // Enable this breakpoint and make it stop in privileged or user mode;
+    control_value |= 7;
+
+    // Make sure bits 1:0 are clear in our address
+    // This should be different once we support thumb here.
+    addr &= ~((lldb::addr_t)3);
+
+    // Iterate over stored hardware breakpoints
+    // Find a free bp_index or update reference count if duplicate.
+    bp_index = LLDB_INVALID_INDEX32;
+    for (uint32_t i = 0; i < m_max_hbp_supported; i++)
+    {
+        if ((m_hbr_regs[i].control & 1) == 0)
+        {
+            bp_index = i;  // Mark last free slot
+        }
+        else if (m_hbr_regs[i].address == addr && m_hbr_regs[i].control == control_value)
+        {
+            bp_index = i;  // Mark duplicate index
+            break;  // Stop searching here
+        }
+    }
+
+     if (bp_index == LLDB_INVALID_INDEX32)
+        return LLDB_INVALID_INDEX32;
+
+    // Add new or update existing watchpoint
+    if ((m_hbr_regs[bp_index].control & 1) == 0)
+    {
+        m_hbr_regs[bp_index].address = addr;
+        m_hbr_regs[bp_index].control = control_value;
+        m_hbr_regs[bp_index].refcount = 1;
+
+        //TODO: PTRACE CALL HERE for an UPDATE
+    }
+    else
+        m_hbr_regs[bp_index].refcount++;
+
+    return bp_index;
+}
+
+bool
+NativeRegisterContextLinux_arm::ClearHardwareBreakpoint (uint32_t hw_idx)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    if (hw_idx >= m_max_hbp_supported)
+        return false;
+
+    // Update reference count if multiple references.
+    if (m_hbr_regs[hw_idx].refcount > 1)
+    {
+        m_hbr_regs[hw_idx].refcount--;
+        return true;
+    }
+    else if (m_hbr_regs[hw_idx].refcount == 1)
+    {
+        m_hbr_regs[hw_idx].control &= ~1;
+        m_hbr_regs[hw_idx].address = 0;
+        m_hbr_regs[hw_idx].refcount = 0;
+
+        //TODO: PTRACE CALL HERE for an UPDATE
+        return true;
+    }
+
+    return false;
+}
+
+uint32_t
+NativeRegisterContextLinux_arm::NumSupportedHardwareWatchpoints ()
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    return m_max_hwp_supported;
+}
+
+uint32_t
+NativeRegisterContextLinux_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t size, uint32_t watch_flags)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
+    if (!process_sp)
+        return false;
+
+    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
+    // Check if our hardware breakpoint and watchpoint information is updated.
+    if (m_refresh_hwdebug_info)
+    {
+        process_p->ReadHardwareDebugInfo (m_thread.GetID (), m_max_hwp_supported,
+                                          m_max_hbp_supported);
+        m_refresh_hwdebug_info = false;
+    }
+
+    uint32_t control_value, wp_index, addr_word_offset, byte_mask;
+    // Can't watch zero bytes
+    // Can't watch more than 4 bytes per WVR/WCR pair
+    lldb_private::StreamString output_stream;
+    output_stream.Printf("Watchpoint created: ");
+
+    if (size == 0 || size > 4)
+        return LLDB_INVALID_INDEX32;
+
+    // We can only watch up to four bytes that follow a 4 byte aligned address
+    // per watchpoint register pair, so make sure we can properly encode this.
+    addr_word_offset = addr % 4;
+    byte_mask = ((1u << size) - 1u) << addr_word_offset;
+
+    // Check if we need multiple watchpoint register
+    if (byte_mask > 0xfu)
+        return LLDB_INVALID_INDEX32;
+
+    // Setup control value
+    // Make the byte_mask into a valid Byte Address Select mask
+    control_value = byte_mask << 5;
+
+    //Turn on appropriate watchpoint flags read or write
+    control_value |= (watch_flags << 3);
+
+    // Enable this watchpoint and make it stop in privileged or user mode;
+    control_value |= 7;
+
+    // Make sure bits 1:0 are clear in our address
+    addr &= ~((lldb::addr_t)3);
+
+    // Iterate over stored watchpoints
+    // Find a free wp_index or update reference count if duplicate.
+    wp_index = LLDB_INVALID_INDEX32;
+    for (uint32_t i = 0; i < m_max_hwp_supported; i++)
+    {
+        if ((m_hwp_regs[i].control & 1) == 0)
+        {
+            wp_index = i; // Mark last free slot
+        }
+        else if (m_hwp_regs[i].address == addr && m_hwp_regs[i].control == control_value)
+        {
+            wp_index = i; // Mark duplicate index
+            break; // Stop searching here
+        }
+    }
+
+     if (wp_index == LLDB_INVALID_INDEX32)
+        return LLDB_INVALID_INDEX32;
+
+    // Add new or update existing watchpoint
+    if ((m_hwp_regs[wp_index].control & 1) == 0)
+    {
+        m_hwp_regs[wp_index].address = addr;
+        m_hwp_regs[wp_index].control = control_value;
+        m_hwp_regs[wp_index].refcount = 1;
+
+        // PTRACE call to set corresponding watchpoint register.
+        process_p->WriteHardwareDebugRegs(m_thread.GetID (), &addr,
+                                          &control_value, 0, wp_index);
+    }
+    else
+        m_hwp_regs[wp_index].refcount++;
+
+    return wp_index;
+}
+
+bool
+NativeRegisterContextLinux_arm::ClearHardwareWatchpoint (uint32_t wp_index)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
+    if (!process_sp)
+        return false;
+
+    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
+
+    if (wp_index >= m_max_hwp_supported)
+        return false;
+
+    // Update reference count if multiple references.
+    if (m_hwp_regs[wp_index].refcount > 1)
+    {
+        m_hwp_regs[wp_index].refcount--;
+        return true;
+    }
+    else if (m_hwp_regs[wp_index].refcount == 1)
+    {
+        m_hwp_regs[wp_index].control &= ~1;
+        m_hwp_regs[wp_index].address = 0;
+        m_hwp_regs[wp_index].refcount = 0;
+
+        //TODO: PTRACE CALL HERE for an UPDATE
+        process_p->WriteHardwareDebugRegs(m_thread.GetID (),
+                                          &m_hwp_regs[wp_index].address,
+                                          &m_hwp_regs[wp_index].control,
+                                          0, wp_index);
+
+        return true;
+    }
+
+    return false;
+}
+
+Error
+NativeRegisterContextLinux_arm::ClearAllHardwareWatchpoints ()
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
+
+    Error ml_error;
+    ml_error.SetErrorToErrno();
+    if (!process_sp)
+        return ml_error;
+
+    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
+
+    for (uint32_t i = 0; i < m_max_hwp_supported; i++)
+    {
+        if (m_hwp_regs[i].control & 0x01)
+        {
+            m_hwp_regs[i].control &= ~1;
+            m_hwp_regs[i].address = 0;
+            m_hwp_regs[i].refcount = 0;
+
+            process_p->WriteHardwareDebugRegs(m_thread.GetID (),
+                                          &m_hwp_regs[i].address,
+                                          &m_hwp_regs[i].control,
+                                          0, i);
+        }
+    }
+
+    return Error();
+}
+
+uint32_t
+NativeRegisterContextLinux_arm::GetWatchpointSize(uint32_t wp_index)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    switch ((m_hwp_regs[wp_index].control >> 5) & 0x0f)
+    {
+        case 0x01:
+            return 1;
+        case 0x03:
+            return 2;
+        case 0x07:
+            return 3;
+        case 0x0f:
+            return 4;
+        default:
+            return 0;
+    }
+}
+bool
+NativeRegisterContextLinux_arm::WatchpointIsEnabled(uint32_t wp_index)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    if ((m_hwp_regs[wp_index].control & 0x1) == 0x1)
+        return true;
+    else
+        return false;
+}
+
+Error
+NativeRegisterContextLinux_arm::GetWatchpointHitIndex(uint32_t &wp_index, lldb::addr_t trap_addr)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    uint32_t watch_size;
+    lldb::addr_t watch_addr;
+
+    for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index)
+    {
+        watch_size = GetWatchpointSize (wp_index);
+        watch_addr = m_hwp_regs[wp_index].address;
+
+        if (m_hwp_regs[wp_index].refcount >= 1 && WatchpointIsEnabled(wp_index)
+            && trap_addr >= watch_addr && trap_addr < watch_addr + watch_size)
+        {
+            return Error();
+        }
+    }
+
+    wp_index = LLDB_INVALID_INDEX32;
+    return Error();
+}
+
+lldb::addr_t
+NativeRegisterContextLinux_arm::GetWatchpointAddress (uint32_t wp_index)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    if (wp_index >= m_max_hwp_supported)
+        return LLDB_INVALID_ADDRESS;
+
+    if (WatchpointIsEnabled(wp_index))
+        return m_hwp_regs[wp_index].address;
+    else
+        return LLDB_INVALID_ADDRESS;
+}
+
+bool
+NativeRegisterContextLinux_arm::HardwareSingleStep (bool enable)
+{
+    Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
+
+    if (log)
+        log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
+
+    return false;
+}
+
 #endif // defined(__arm__)

source/Plugins/Process/Linux/ProcessMonitor.h

public:
     /// Reads all general purpose registers into the specified buffer.
     bool
     ReadGPR(lldb::tid_t tid, void *buf, size_t buf_size);
 
     /// Reads generic floating point registers into the specified buffer.
     bool
     ReadFPR(lldb::tid_t tid, void *buf, size_t buf_size);
 
-#if defined (__arm64__) || defined (__aarch64__)
     /// Reads hardware breakpoints and watchpoints capability information.
     bool
     ReadHardwareDebugInfo (lldb::tid_t tid, unsigned int &watch_count ,
                            unsigned int &break_count);
 
     /// Write hardware breakpoint/watchpoint control and address registers.
     bool
     WriteHardwareDebugRegs (lldb::tid_t tid, lldb::addr_t *addr_buf,
                             uint32_t *cntrl_buf, int type, int count);
-#endif
 
     /// Reads the specified register set into the specified buffer.
     /// For instance, the extended floating-point register set.
     bool
     ReadRegisterSet(lldb::tid_t tid, void *buf, size_t buf_size, unsigned int regset);
 
     /// Writes all general purpose registers into the specified buffer.
     bool

source/Plugins/Process/Linux/ProcessMonitor.cpp

 void
 WriteOperation::Execute(ProcessMonitor *monitor)
 {
     lldb::pid_t pid = monitor->GetPID();
 
     m_result = DoWriteMemory(pid, m_addr, m_buff, m_size, m_error);
 }
 
+//------------------------------------------------------------------------------
+/// @class ReadDBGROperation
+/// @brief Implements NativeProcessLinux::ReadDBGR.
+class ReadDBGROperation : public Operation
+{
+public:
+    ReadDBGROperation(lldb::tid_t tid, unsigned int &count_wp,
+                      unsigned int &count_bp)
+        : m_tid(tid),
+          m_count_wp(count_wp),
+          m_count_bp(count_bp)
+        { }
+
+    void Execute(ProcessMonitor *monitor) override;
+
+private:
+    lldb::tid_t m_tid;
+    unsigned int &m_count_wp;
+    unsigned int &m_count_bp;
+};
+
+void
+ReadDBGROperation::Execute(ProcessMonitor *monitor)
+{
+#if defined (__arm64__) || defined (__aarch64__)
+
+    int regset = NT_ARM_HW_WATCH;
+    struct iovec ioVec;
+    struct user_hwdebug_state dreg_state;
+
+    ioVec.iov_base = &dreg_state;
+    ioVec.iov_len = sizeof (dreg_state);
+
+    PTRACE(PTRACE_GETREGSET, m_tid, &regset, &ioVec, ioVec.iov_len);
+
+    m_count_wp = dreg_state.dbg_info & 0xff;
+    regset = NT_ARM_HW_BREAK;
+
+    PTRACE(PTRACE_GETREGSET, m_tid, &regset, &ioVec, ioVec.iov_len);
+    m_count_bp = dreg_state.dbg_info & 0xff;
+
+#elif defined (__arm__) || defined (__thumb__)
+
+    unsigned int cap_val;
+
+    PTRACE(PTRACE_GETHBPREGS, m_tid, nullptr, &cap_val, sizeof(unsigned int));
+
+    m_count_wp = (cap_val >> 8) & 0xff;
+    m_count_bp = cap_val & 0xff;
+
+#endif
+}
 
 //------------------------------------------------------------------------------
+/// @class WriteDBGROperation
+/// @brief Implements NativeProcessLinux::WriteFPR.
+class WriteDBGROperation : public Operation
+{
+public:
+    WriteDBGROperation(lldb::tid_t tid, lldb::addr_t *addr_buf,
+                       uint32_t *cntrl_buf, int type, int count)
+        : m_tid(tid),
+          m_address(addr_buf),
+          m_control(cntrl_buf),
+          m_type(type),
+          m_count(count)
+        { }
+
+    void Execute(ProcessMonitor *monitor) override;
+private:
+    lldb::tid_t m_tid;
+    lldb::addr_t * m_address;
+    uint32_t * m_control;
+    int m_type;
+    int m_count;
+};
+
+void
+WriteDBGROperation::Execute(ProcessMonitor *monitor)
+{
+#if defined (__arm64__) || defined (__aarch64__)
+    struct iovec ioVec;
+    struct user_hwdebug_state dreg_state;
+
+    memset (&dreg_state, 0, sizeof (dreg_state));
+    ioVec.iov_base = &dreg_state;
+    ioVec.iov_len = sizeof(dreg_state);
+
+    if (m_type == 0)
+        m_type = NT_ARM_HW_WATCH;
+    else
+        m_type = NT_ARM_HW_BREAK;
+
+    for (int i = 0; i < m_count; i++)
+    {
+        dreg_state.dbg_regs[i].addr = m_addr_buf[i];
+        dreg_state.dbg_regs[i].ctrl = m_cntrl_buf[i];
+    }
+
+    PTRACE(PTRACE_SETREGSET, m_tid, &m_type, &ioVec, ioVec.iov_len);
+
+#elif defined (__arm__) || defined (__thumb__)
+
+    if (m_type)
+    {
+        PTRACE(PTRACE_SETHBPREGS, m_tid,
+               (PTRACE_TYPE_ARG3) ((m_count << 1) + 1),
+               m_address, sizeof(unsigned int));
+
+        PTRACE(PTRACE_SETHBPREGS, m_tid,
+               (PTRACE_TYPE_ARG3) ((m_count << 1) + 2),
+               m_control, sizeof(unsigned int));
+
+    }
+    else
+    {
+        PTRACE(PTRACE_SETHBPREGS, m_tid,
+               (PTRACE_TYPE_ARG3) -((m_count << 1) + 1),
+               m_address, sizeof(unsigned int));
+
+        PTRACE(PTRACE_SETHBPREGS, m_tid,
+               (PTRACE_TYPE_ARG3) -((m_count << 1) + 2),
+               m_control, sizeof(unsigned int));
+    }
+#endif
+}
+
 /// @class ReadRegOperation
 /// @brief Implements ProcessMonitor::ReadRegisterValue.
 class ReadRegOperation : public Operation
 {
 public:
     ReadRegOperation(lldb::tid_t tid, unsigned offset, const char *reg_name,
                      RegisterValue &value, bool &result)
         : m_tid(tid), m_offset(offset), m_reg_name(reg_name),
else
         m_result = true;
     }
     if (log)
         log->Printf ("ProcessMonitor::%s() reg %s: 0x%" PRIx64, __FUNCTION__,
                      m_reg_name, data);
 #endif
 }
 
-#if defined (__arm64__) || defined (__aarch64__)
-    //------------------------------------------------------------------------------
-    /// @class ReadDBGROperation
-    /// @brief Implements NativeProcessLinux::ReadDBGR.
-    class ReadDBGROperation : public Operation
-    {
-    public:
-        ReadDBGROperation(lldb::tid_t tid, unsigned int &count_wp, unsigned int &count_bp)
-            : m_tid(tid),
-              m_count_wp(count_wp),
-              m_count_bp(count_bp)
-            { }
-
-        void Execute(ProcessMonitor *monitor) override;
-
-    private:
-        lldb::tid_t m_tid;
-        unsigned int &m_count_wp;
-        unsigned int &m_count_bp;
-    };
-
-    void
-    ReadDBGROperation::Execute(ProcessMonitor *monitor)
-    {
-       int regset = NT_ARM_HW_WATCH;
-       struct iovec ioVec;
-       struct user_hwdebug_state dreg_state;
-
-       ioVec.iov_base = &dreg_state;
-       ioVec.iov_len = sizeof (dreg_state);
-
-       PTRACE(PTRACE_GETREGSET, m_tid, &regset, &ioVec, ioVec.iov_len);
-
-       m_count_wp = dreg_state.dbg_info & 0xff;
-       regset = NT_ARM_HW_BREAK;
-
-       PTRACE(PTRACE_GETREGSET, m_tid, &regset, &ioVec, ioVec.iov_len);
-       m_count_bp = dreg_state.dbg_info & 0xff;
-    }
-#endif
-
-#if defined (__arm64__) || defined (__aarch64__)
-    //------------------------------------------------------------------------------
-    /// @class WriteDBGROperation
-    /// @brief Implements NativeProcessLinux::WriteFPR.
-    class WriteDBGROperation : public Operation
-    {
-    public:
-        WriteDBGROperation(lldb::tid_t tid, lldb::addr_t *addr_buf, uint32_t *cntrl_buf, int type, int count)
-            : m_tid(tid),
-              m_addr_buf(addr_buf),
-              m_cntrl_buf(cntrl_buf),
-              m_type(type),
-              m_count(count)
-            { }
-
-        void Execute(ProcessMonitor *monitor) override;
-
-    private:
-        lldb::tid_t m_tid;
-        lldb::addr_t *m_addr_buf;
-        uint32_t *m_cntrl_buf;
-        int m_type;
-        int m_count;
-    };
-
-    void
-    WriteDBGROperation::Execute(ProcessMonitor *monitor)
-    {
-        struct iovec ioVec;
-        struct user_hwdebug_state dreg_state;
-
-        memset (&dreg_state, 0, sizeof (dreg_state));
-        ioVec.iov_base = &dreg_state;
-        ioVec.iov_len = sizeof(dreg_state);
-
-        if (m_type == 0)
-            m_type = NT_ARM_HW_WATCH;
-        else
-            m_type = NT_ARM_HW_BREAK;
-
-        for (int i = 0; i < m_count; i++)
-        {
-            dreg_state.dbg_regs[i].addr = m_addr_buf[i];
-            dreg_state.dbg_regs[i].ctrl = m_cntrl_buf[i];
-        }
-
-        PTRACE(PTRACE_SETREGSET, m_tid, &m_type, &ioVec, ioVec.iov_len);
-    }
-#endif//------------------------------------------------------------------------------
 /// @class WriteRegOperation
 /// @brief Implements ProcessMonitor::WriteRegisterValue.
 class WriteRegOperation : public Operation
 {
 public:
     WriteRegOperation(lldb::tid_t tid, unsigned offset, const char *reg_name,
                       const RegisterValue &value, bool &result)
         : m_tid(tid), m_offset(offset), m_reg_name(reg_name),
if (m_offset > sizeof(struct user_pt_regs))
                     m_result = true;
             }
         }
     }
     else
     {
         elf_gregset_t regs;
         int regset = NT_PRSTATUS;
         struct iovec ioVec;
 
         ioVec.iov_base = &regs;
         ioVec.iov_len = sizeof regs;
         if (PTRACE(PTRACE_GETREGSET, m_tid, &regset, &ioVec, sizeof regs) < 0)
             m_result = false;
         else
         {
             ::memcpy((void *)(((unsigned char *)(&regs)) + m_offset), m_value.GetBytes(), 8);
ProcessMonitor::ReadRegisterValue(lldb::tid_t tid, unsigned offset, const char* reg_name,
                                   unsigned size, RegisterValue &value)
 {
     bool result;
     ReadRegOperation op(tid, offset, reg_name, value, result);
     DoOperation(&op);
     return result;
 }
 
-#if defined (__arm64__) || defined (__aarch64__)
-
 bool
 ProcessMonitor::ReadHardwareDebugInfo (lldb::tid_t tid, unsigned int &watch_count , unsigned int &break_count)
 {
     bool result = true;
     ReadDBGROperation op(tid, watch_count, break_count);
     DoOperation(&op);
     return result;
 }
 
 bool
 ProcessMonitor::WriteHardwareDebugRegs (lldb::tid_t tid, lldb::addr_t *addr_buf, uint32_t *cntrl_buf, int type, int count)
 {
     bool result = true;
     WriteDBGROperation op(tid, addr_buf, cntrl_buf, type, count);
     DoOperation(&op);
     return result;
 }
 
-#endif
 bool
 ProcessMonitor::WriteRegisterValue(lldb::tid_t tid, unsigned offset,
                                    const char* reg_name, const RegisterValue &value)
 {
     bool result;
     WriteRegOperation op(tid, offset, reg_name, value, result);
     DoOperation(&op);
     return result;