[GlobalISel] Add G_ASSERT_SEXT

[paquette]

Summary

This adds a G_ASSERT_SEXT opcode, similar to G_ASSERT_ZEXT. This instruction signifies that an operation was already sign extended from a smaller type.

This is useful for functions with sign-extended parameters.

E.g.

define void @foo(i16 signext %x) {
    ...
}

This adds verifier, regbankselect, and instruction selection support for G_ASSERT_SEXT equivalent to G_ASSERT_ZEXT.

llvm/docs/GlobalISel/GenericOpcode.rst

.. code-block:: none
   %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32
 
 Optimization Hints
 ------------------
 
 These instructions do not correspond to any target instructions. They act as
 hints for various combines.
 
-G_ASSERT_ZEXT
+G_ASSERT_SEXT, G_ASSERT_ZEXT
 ^^^^^^^^^^^^^
 
-Signifies that the contents of a register were previously zero-extended from a
+Signifies that the contents of a register were previously extended from a
 smaller type.
 
 The smaller type is denoted using an immediate operand. For scalars, this is the
 width of the entire smaller type. For vectors, this is the width of the smaller
 element type.
 
 .. code-block:: none
 
-  %x_assert:_(s32) = G_ASSERT_ZEXT %x(s32), 16
-  %y_assert:_(<2 x s32>) = G_ASSERT_ZEXT %y(<2 x s32>), 16
+  %x_was_zexted:_(s32) = G_ASSERT_ZEXT %x(s32), 16
+  %y_was_zexted:_(<2 x s32>) = G_ASSERT_ZEXT %y(<2 x s32>), 16
 
-G_ASSERT_ZEXT acts like a restricted form of copy.
+  %z_was_sexted:_(s32) = G_ASSERT_SEXT %z(s32), 8
+
+G_ASSERT_SEXT and G_ASSERT_ZEXT act like copies, albeit with some restrictions.
 
 The source and destination registers must
 
 - Be virtual
 - Belong to the same register class
 - Belong to the same register bank
 
 It should always be safe to
 
 - Look through the source register
 - Replace the destination register with the source register

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
 
   /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
                                       unsigned Size);
 
+  /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
+                                      unsigned Size);
+
   /// Build and insert `Res = G_LOAD Addr, MMO`.
   ///
   /// Loads the value stored at \p Addr. Puts the result in \p Res.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res must be a generic virtual register.
   /// \pre \p Addr must be a generic virtual register with pointer type.
   ///

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
 
 /// The following generic opcodes are not supposed to appear after ISel.
 /// This is something we might want to relax, but for now, this is convenient
 /// to produce diagnostics.
 
 /// Instructions which should not exist past instruction selection, but do not
 /// generate code. These instructions only act as optimization hints.
+HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
 HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START,
-                            G_ASSERT_ZEXT)
+                            G_ASSERT_SEXT)
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END,
                             G_ASSERT_ZEXT)
 
 /// Generic ADD instruction. This is an integer add.
 HANDLE_TARGET_OPCODE(G_ADD)
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
 
 /// Generic SUB instruction. This is an integer sub.

llvm/include/llvm/Target/GenericOpcodes.td

 
 // Asserts that an operation has already been zero-extended from a specific
 // type.
 def G_ASSERT_ZEXT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
   let hasSideEffects = false;
 }
+
+// Asserts that an operation has already been sign-extended from a specific
+// type.
+def G_ASSERT_SEXT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
+  let hasSideEffects = false;
+}

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

return buildInstr(TargetOpcode::G_BRJT)
       .addUse(IndexReg);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
                                                 const SrcOp &Op) {
   return buildInstr(TargetOpcode::COPY, Res, Op);
 }
 
+MachineInstrBuilder MachineIRBuilder::buildAssertSExt(const DstOp &Res,
+                                                      const SrcOp &Op,
+                                                      unsigned Size) {
+  return buildInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op).addImm(Size);
+}
+
 MachineInstrBuilder MachineIRBuilder::buildAssertZExt(const DstOp &Res,
                                                       const SrcOp &Op,
                                                       unsigned Size) {
   return buildInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op).addImm(Size);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
                                                     const ConstantInt &Val) {

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

bool RegBankSelect::applyMapping(
   RBI->applyMapping(OpdMapper);
 
   return true;
 }
 
 bool RegBankSelect::assignInstr(MachineInstr &MI) {
   LLVM_DEBUG(dbgs() << "Assign: " << MI);
 
-  if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
-    // We'll probably have a G_ASSERT_SEXT or something similar in the future.
-    assert(MI.getOpcode() == TargetOpcode::G_ASSERT_ZEXT &&
-           "G_ASSERT_ZEXT is the only hint right now!");
+  unsigned Opc = MI.getOpcode();
+  if (isPreISelGenericOptimizationHint(Opc)) {
+    assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
+            Opc == TargetOpcode::G_ASSERT_SEXT) &&
+           "Unexpected hint opcode!");
     // The only correct mapping for these is to always use the source register
     // bank.
     const RegisterBank *RB = MRI->getRegBankOrNull(MI.getOperand(1).getReg());
     // We can assume every instruction above this one has a selected register
     // bank.
     assert(RB && "Expected source register to have a register bank?");
-    LLVM_DEBUG(
-        dbgs() << "... G_ASSERT_ZEXT always uses source's register bank.\n");
+    LLVM_DEBUG(dbgs() << "... Hint always uses source's register bank.\n");
     MRI->setRegBank(MI.getOperand(0).getReg(), *RB);
     return true;
   }
 
   // Remember the repairing placement for all the operands.
   SmallVector<RepairingPlacement, 4> RepairPts;
 
   const RegisterBankInfo::InstructionMapping *BestMapping;

llvm/lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
     void visitMachineFunctionAfter();
 
     void report(const char *msg, const MachineFunction *MF);
     void report(const char *msg, const MachineBasicBlock *MBB);
     void report(const char *msg, const MachineInstr *MI);
     void report(const char *msg, const MachineOperand *MO, unsigned MONum,
                 LLT MOVRegType = LLT{});
+    void report(const Twine &Msg, const MachineInstr *MI);
 
     void report_context(const LiveInterval &LI) const;
     void report_context(const LiveRange &LR, Register VRegUnit,
                         LaneBitmask LaneMask) const;
     void report_context(const LiveRange::Segment &S) const;
     void report_context(const VNInfo &VNI) const;
     void report_context(SlotIndex Pos) const;
     void report_context(MCPhysReg PhysReg) const;
void MachineVerifier::report(const char *msg, const MachineOperand *MO,
                              unsigned MONum, LLT MOVRegType) {
   assert(MO);
   report(msg, MO->getParent());
   errs() << "- operand " << MONum << ":   ";
   MO->print(errs(), MOVRegType, TRI);
   errs() << "\n";
 }
 
+void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
+  report(Msg.str().c_str(), MI);
+}
+
 void MachineVerifier::report_context(SlotIndex Pos) const {
   errs() << "- at:          " << Pos << '\n';
 }
 
 void MachineVerifier::report_context(const LiveInterval &LI) const {
   errs() << "- interval:    " << LI << '\n';
 }
 
void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
   if (MI->getNumOperands() < MCID.getNumOperands())
     return;
 
   StringRef ErrorInfo;
   if (!TII->verifyInstruction(*MI, ErrorInfo))
     report(ErrorInfo.data(), MI);
 
   // Verify properties of various specific instruction types
-  switch (MI->getOpcode()) {
+  unsigned Opc = MI->getOpcode();
+  switch (Opc) {
+  case TargetOpcode::G_ASSERT_SEXT:
   case TargetOpcode::G_ASSERT_ZEXT: {
+    std::string OpcName =
+        Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
     if (!MI->getOperand(2).isImm()) {
-      report("G_ASSERT_ZEXT expects an immediate operand #2", MI);
+      report(Twine(OpcName, " expects an immediate operand #2"), MI);
       break;
     }
 
     Register Dst = MI->getOperand(0).getReg();
     Register Src = MI->getOperand(1).getReg();
     LLT SrcTy = MRI->getType(Src);
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0) {
-      report("G_ASSERT_ZEXT size must be >= 1", MI);
+      report(Twine(OpcName, " size must be >= 1"), MI);
       break;
     }
 
     if (Imm >= SrcTy.getScalarSizeInBits()) {
-      report("G_ASSERT_ZEXT size must be less than source bit width", MI);
+      report(Twine(OpcName, " size must be less than source bit width"), MI);
       break;
     }
 
     if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
-      report("G_ASSERT_ZEXT source and destination register banks must match",
-             MI);
+      report(
+          Twine(OpcName, " source and destination register banks must match"),
       break;
     }
 
     if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
-      report("G_ASSERT_ZEXT source and destination register classes must match",
-             MI);
+      report(
+          Twine(OpcName, " source and destination register classes must match"),
 
     break;
   }
 
   case TargetOpcode::G_CONSTANT:
   case TargetOpcode::G_FCONSTANT: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     if (DstTy.isVector())

llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Verify register banks for G_ASSERT_SEXT.
+#
+
+...
+---
+name:            gpr
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; G_ASSERT_SEXT should end up on a GPR.
+
+    ; CHECK-LABEL: name: gpr
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:gpr(s32) = COPY $w0
+    ; CHECK: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: $w1 = COPY %copy_assert_sext(s32)
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:_(s32) = COPY $w0
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    $w1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            gpr_vector
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $x1
+
+    ; G_ASSERT_SEXT should end up on a GPR.
+
+    ; CHECK-LABEL: name: gpr_vector
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK: %copy:gpr(<2 x s32>) = COPY $x0
+    ; CHECK: %copy_assert_sext:gpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: $x1 = COPY %copy_assert_sext(<2 x s32>)
+    ; CHECK: RET_ReallyLR implicit $x1
+    %copy:_(<2 x s32>) = COPY $x0
+    %copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
+    $x1 = COPY %copy_assert_sext(<2 x s32>)
+    RET_ReallyLR implicit $x1
+
+...
+---
+name:            fpr
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+
+    ; G_ASSERT_SEXT should end up on a FPR.
+
+    ; CHECK-LABEL: name: fpr
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK: %copy:fpr(s32) = COPY $s0
+    ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: $s1 = COPY %copy_assert_sext(s32)
+    ; CHECK: RET_ReallyLR implicit $s1
+    %copy:_(s32) = COPY $s0
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    $s1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            fpr_vector
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0, $d1
+
+    ; G_ASSERT_SEXT should end up on a FPR.
+
+    ; CHECK-LABEL: name: fpr_vector
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK: %copy:fpr(<2 x s32>) = COPY $d0
+    ; CHECK: %copy_assert_sext:fpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: $d1 = COPY %copy_assert_sext(<2 x s32>)
+    ; CHECK: RET_ReallyLR implicit $d1
+    %copy:_(<2 x s32>) = COPY $d0
+    %copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
+    $d1 = COPY %copy_assert_sext(<2 x s32>)
+    RET_ReallyLR implicit $d1
+
+...
+---
+name:            in_between_cross_bank_copy
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $w1
+
+    ; CHECK-LABEL: name: in_between_cross_bank_copy
+    ; CHECK: liveins: $s0, $w1
+    ; CHECK: %copy:fpr(s32) = COPY $s0
+    ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: $w1 = COPY %copy_assert_sext(s32)
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:_(s32) = COPY $s0
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    $w1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            fpr_feeding_store
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $s0, $s1
+
+    ; The G_ASSERT_SEXT should end up on a FPR, and there should be no copy
+    ; between it and the G_STORE.
+
+    ; CHECK-LABEL: name: fpr_feeding_store
+    ; CHECK: liveins: $x0, $s0, $s1
+    ; CHECK: %ptr:gpr(p0) = COPY $x0
+    ; CHECK: %copy:fpr(s32) = COPY $s0
+    ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+    ; CHECK: G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store 4)
+    ; CHECK: RET_ReallyLR
+    %ptr:_(p0) = COPY $x0
+    %copy:_(s32) = COPY $s0
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store 4)
+    RET_ReallyLR
+
+...
+---
+name:            fpr_feeding_select
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0, $x1, $w0
+
+    ; G_ASSERT_SEXT and G_SELECT should both end up on FPRs.
+
+    ; CHECK-LABEL: name: fpr_feeding_select
+    ; CHECK: liveins: $d0, $x1, $w0
+    ; CHECK: %w0:gpr(s32) = COPY $w0
+    ; CHECK: %cond:gpr(s1) = G_TRUNC %w0(s32)
+    ; CHECK: %fpr:fpr(s64) = COPY $d0
+    ; CHECK: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
+    ; CHECK: %gpr:gpr(s64) = COPY $x1
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+    ; CHECK: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_sext, [[COPY]]
+    ; CHECK: $d0 = COPY %select(s64)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %w0:_(s32) = COPY $w0
+    %cond:_(s1) = G_TRUNC %w0(s32)
+    %fpr:_(s64) = COPY $d0
+    %fpr_assert_sext:_(s64) = G_ASSERT_SEXT %fpr, 32
+    %gpr:_(s64) = COPY $x1
+    %select:_(s64) = G_SELECT %cond(s1), %fpr_assert_sext, %gpr
+    $d0 = COPY %select(s64)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            fpr_feeding_phi
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: fpr_feeding_phi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: $s0, $w1
+  ; CHECK:   %copy1:fpr(s32) = COPY $s0
+  ; CHECK:   %copy2:gpr(s32) = COPY $w1
+  ; CHECK:   %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+  ; CHECK:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
+  ; CHECK:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+  ; CHECK:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   %bb1_val:gpr(s32) = COPY %copy2(s32)
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.0(0x80000000)
+  ; CHECK:   %phi:fpr(s32) = G_PHI %copy_assert_sext(s32), %bb.0, %bb1_val(s32), %bb.1
+  ; CHECK:   G_BR %bb.0
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $s0, $w1
+    %copy1:_(s32) = COPY $s0
+    %copy2:_(s32) = COPY $w1
+
+    ; This should produce a FPR.
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy1(s32), 16
+
+    %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
+    %cmp_trunc:_(s1) = G_TRUNC %cmp
+    G_BRCOND %cmp_trunc, %bb.1
+    G_BR %bb.1
+  bb.1:
+    successors: %bb.2
+    %bb1_val:_(s32) = COPY %copy2
+    G_BR %bb.2
+  bb.2:
+    successors: %bb.0
+    ; This should produce a FPR.
+    %phi:_(s32) = G_PHI %copy_assert_sext, %bb.0, %bb1_val, %bb.1
+    G_BR %bb.0
+
+...
+---
+name:            fed_by_fpr_phi
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: fed_by_fpr_phi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: $s0, $s1
+  ; CHECK:   %copy1:fpr(s32) = COPY $s0
+  ; CHECK:   %copy2:fpr(s32) = COPY $s1
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
+  ; CHECK:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+  ; CHECK:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+  ; CHECK:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   %bb1_val:gpr(s32) = COPY %copy2(s32)
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.0(0x80000000)
+  ; CHECK:   %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
+  ; CHECK:   %assert_sext:fpr(s32) = G_ASSERT_SEXT %phi, 16
+  ; CHECK:   G_BR %bb.0
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $s0, $s1
+    %copy1:_(s32) = COPY $s0
+    %copy2:_(s32) = COPY $s1
+    %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
+    %cmp_trunc:_(s1) = G_TRUNC %cmp
+    G_BRCOND %cmp_trunc, %bb.1
+    G_BR %bb.1
+  bb.1:
+    successors: %bb.2
+    %bb1_val:_(s32) = COPY %copy2
+    G_BR %bb.2
+  bb.2:
+    successors: %bb.0
+    ; The G_PHI and G_ASSERT_SEXT should both end up on FPRs.
+    %phi:_(s32) = G_PHI %copy1, %bb.0, %bb1_val, %bb.1
+    %assert_sext:_(s32) = G_ASSERT_SEXT %phi(s32), 16
+    G_BR %bb.0
+
+...
+---
+name:            different_blocks_gpr
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: different_blocks_gpr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $w0, $w1
+  ; CHECK:   %copy:gpr(s32) = COPY $w0
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+  ; CHECK:   $w1 = COPY %copy_assert_sext(s32)
+  ; CHECK:   RET_ReallyLR implicit $w1
+  bb.0:
+    successors: %bb.1
+    liveins: $w0, $w1
+    %copy:_(s32) = COPY $w0
+    G_BR %bb.1
+  bb.1:
+    ; The G_ASSERT_SEXT should end up on a GPR.
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    $w1 = COPY %copy_assert_sext
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            different_blocks_fpr
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: different_blocks_fpr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $s0, $s1
+  ; CHECK:   %copy:fpr(s32) = COPY $s0
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+  ; CHECK:   $s1 = COPY %copy_assert_sext(s32)
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1
+    liveins: $s0, $s1
+    %copy:_(s32) = COPY $s0
+    G_BR %bb.1
+  bb.1:
+    ; The G_ASSERT_SEXT should end up on a FPR.
+    %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    $s1 = COPY %copy_assert_sext
+    RET_ReallyLR implicit $s1
+
+
+...
+---
+name:            different_blocks_fpr_backedge
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: different_blocks_fpr_backedge
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $s0, $s1
+  ; CHECK:   %copy:fpr(s32) = COPY $s0
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   %copy_assert_sext1:fpr(s32) = G_ASSERT_SEXT %copy, 16
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.0(0x80000000)
+  ; CHECK:   %copy_assert_sext2:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext1, 16
+  ; CHECK:   %copy_assert_sext3:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext2, 16
+  ; CHECK:   G_BR %bb.0
+  bb.0:
+    successors: %bb.1
+    liveins: $s0, $s1
+    %copy:_(s32) = COPY $s0
+    G_BR %bb.1
+  bb.1:
+    successors: %bb.2
+    ; All of the G_ASSERT_SEXTs should end up on FPRs.
+    %copy_assert_sext1:_(s32) = G_ASSERT_SEXT %copy(s32), 16
+    G_BR %bb.2
+  bb.2:
+    successors: %bb.0
+    %copy_assert_sext2:_(s32) = G_ASSERT_SEXT %copy_assert_sext1(s32), 16
+    %copy_assert_sext3:_(s32) = G_ASSERT_SEXT %copy_assert_sext2(s32), 16
+    G_BR %bb.0

llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
-# Check that we remove G_ASSERT_ZEXT during selection.
+# Check that we remove hints during selection.
 
 ...
 ---
 name:            assert_zext_gpr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
bb.0:
     ; CHECK: %copy_with_rc:gpr32sp = COPY $w2
     ; CHECK: $w1 = COPY %copy_with_rc
     ; CHECK: RET_ReallyLR implicit $w1
     %copy:gpr(s32) = COPY $w0
     %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
     %copy_with_rc:gpr32sp(s32) = COPY $w2
     $w1 = COPY %copy_with_rc(s32)
     RET_ReallyLR implicit $w1
+
+...
+---
+name:            assert_sext_gpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: assert_sext_gpr
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:gpr32all = COPY $w0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:gpr(s32) = COPY $w0
+    %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+    $w1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            assert_sext_fpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+
+    ; CHECK-LABEL: name: assert_sext_fpr
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $s1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $s1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+    $s1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            assert_sext_in_between_cross_bank
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $w1
+
+    ; CHECK-LABEL: name: assert_sext_in_between_cross_bank
+    ; CHECK: liveins: $s0, $w1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+    $w1 = COPY %copy_assert_sext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            assert_sext_decided_dst_class
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1, $w2
+
+    ; Users of G_ASSERT_SEXT may end up deciding the destination register class.
+    ; Make sure that the source register class is constrained.
+
+    ; CHECK-LABEL: name: assert_sext_decided_dst_class
+    ; CHECK: liveins: $w0, $w1, $w2
+    ; CHECK: %copy_with_rc:gpr32sp = COPY $w2
+    ; CHECK: $w1 = COPY %copy_with_rc
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:gpr(s32) = COPY $w0
+    %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+    %copy_with_rc:gpr32sp(s32) = COPY $w2
+    $w1 = COPY %copy_with_rc(s32)
+    RET_ReallyLR implicit $w1

llvm/test/MachineVerifier/test_g_assert_sext.mir

+# REQUIRES: aarch64-registered-target
+# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+name:            test
+body: |
+  bb.0:
+   liveins: $x0, $w0
+   %0:_(s64) = COPY $x0
+   %1:_(<4 x s16>) = COPY $x0
+   %2:_(s32) = COPY $w0
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
+   ; CHECK: instruction: %assert_sext_1:_(s64) = G_ASSERT_SEXT
+   %assert_sext_1:_(s64) = G_ASSERT_SEXT %0, %0
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
+   ; CHECK: instruction: %assert_sext_2:_(s64) = G_ASSERT_SEXT
+   %assert_sext_2:_(s64) = G_ASSERT_SEXT %0, i8 8
+
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+   ; CHECK: instruction: %assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT
+   %assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT %0, 8
+
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+   ; CHECK: instruction: %assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT
+   %assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT %1, 8
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be >= 1 ***
+   ; CHECK: instruction: %assert_sext_5:_(s64) = G_ASSERT_SEXT
+   %assert_sext_5:_(s64) = G_ASSERT_SEXT %0, 0
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be less than source bit width ***
+   ; CHECK: instruction: %assert_sext_6:_(s64) = G_ASSERT_SEXT
+   %assert_sext_6:_(s64) = G_ASSERT_SEXT %0, 128
+
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+   ; CHECK: instruction: %assert_sext_7:_(s64) = G_ASSERT_SEXT %2:_, 8
+   %assert_sext_7:_(s64) = G_ASSERT_SEXT %2, 8
+
+   ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+   ; CHECK: instruction: %assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
+   %assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8

llvm/test/MachineVerifier/test_g_assert_sext_register_bank_class.mir

+# REQUIRES: aarch64-registered-target
+# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+name:            test
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+   liveins: $w0, $w1
+   %bank:gpr(s32) = COPY $w0
+   %class:gpr32(s32) = COPY $w1
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
+   ; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank:gpr, 16
+   %bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank, 16
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
+   ; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class:gpr32, 16
+   %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class, 16
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
+   ; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class:gpr32, 16
+   %class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class, 16
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
+   ; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank:gpr, 16
+   %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank, 16
+
+   ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
+   ; CHECK: instruction: %dst_has_bank_src_has_class:gpr(s32) = G_ASSERT_SEXT %class:gpr32, 16
+   %dst_has_bank_src_has_class:gpr(s32) = G_ASSERT_SEXT %class, 16
+
+   ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+   ; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class:gpr32, 16, implicit-def $w0
+   %implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class, 16, implicit-def $w0