[AVR] Fix a bug in 16-bit shifts

[benshi001]

Summary

Fix a bug in my prevous commit 50f1aa1db5c59499b40abda1f565a3db1ebd7ee4.

The generated ANDIs in the expansion of pseudo LSLW4/LSLW12/LSR4/LSR12
should only use R16~R31.

[aykevl]

Thank you for the quick patch! I have verified locally that this does indeed fix the bug (my AVR tests pass again), so this looks good to me.

[aykevl]

@benshi001 can you commit it or should I do it for you?

[benshi001]

In D96590#2561818, @aykevl wrote:

@benshi001 can you commit it or should I do it for you?

Thanks. I have committed it. And you are appreciated to take a look at my patch https://reviews.llvm.org/D96506，

it is also about shift optimization.

[aykevl]

Thank you!
I have created a bug report to include this fix in the LLVM 12 release: https://bugs.llvm.org/show_bug.cgi?id=49176

llvm/lib/Target/AVR/AVRInstrInfo.td

def LSLWRd : Pseudo<(outs DREGS:$rd),
                       "lslw\t$rd",
                       [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>;
 
   def LSLB7Rd : Pseudo<(outs GPR8:$rd),
                        (ins GPR8:$src),
                        "lslb7\t$rd",
                        [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
 
-  def LSLW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw4\t$rd",
                        [(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>;
 
   def LSLW8Rd : Pseudo<(outs DREGS:$rd),
                        (ins DREGS:$src),
                        "lslw8\t$rd",
                        [(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>;
 
-  def LSLW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw12\t$rd",
                        [(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>;
 
   def LSRRd : FRd<0b1001,
                   0b0100110,
                   (outs GPR8:$rd),
                   (ins GPR8:$src),
                   "lsr\t$rd",
                   [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>;
 
   def LSRB7Rd : Pseudo<(outs GPR8:$rd),
                        (ins GPR8:$src),
                        "lsrb7\t$rd",
                        [(set i8:$rd, (AVRlsr7 i8:$src)), (implicit SREG)]>;
 
   def LSRWRd : Pseudo<(outs DREGS:$rd),
                       (ins DREGS:$src),
                       "lsrw\t$rd",
                       [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
 
-  def LSRW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw4\t$rd",
                        [(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>;
 
   def LSRW8Rd : Pseudo<(outs DREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw8\t$rd",
                        [(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>;
 
-  def LSRW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw12\t$rd",
                        [(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>;
 
   def ASRRd : FRd<0b1001,
                   0b0100101,
                   (outs GPR8:$rd),
                   (ins GPR8:$src),

llvm/test/CodeGen/AVR/shift.ll

 ; CHECK-NEXT:  eor r25, r24
 ; CHECK-NEXT:  lsl r24
 ; CHECK-NEXT:  rol r25
 ; CHECK-NEXT:  ret
   %result = shl i16 %a, 5
   ret i16 %result
 }
 
+define i16 @lsl_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsl_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r25, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  andi r24, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  ret
+  %result = shl i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsl_i16_9(i16 %a) {
 ; CHECK-LABEL: lsl_i16_9
 ; CHECK:       mov r25, r24
 ; CHECK-NEXT:  clr r24
 ; CHECK-NEXT:  lsl r24
 ; CHECK-NEXT:  rol r25
 ; CHECK-NEXT:  ret
   %result = shl i16 %a, 9

 ; CHECK-NEXT:  eor r24, r25
 ; CHECK-NEXT:  lsr r25
 ; CHECK-NEXT:  ror r24
 ; CHECK-NEXT:  ret
   %result = lshr i16 %a, 5
   ret i16 %result
 }
 
+define i16 @lsr_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsr_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r24, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  andi r25, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT: ret
+  %result = lshr i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsr_i16_9(i16 %a) {
 ; CHECK-LABEL: lsr_i16_9
 ; CHECK:       mov r24, r25
 ; CHECK-NEXT:  clr r25
 ; CHECK-NEXT:  lsr r25
 ; CHECK-NEXT:  ror r24
 ; CHECK-NEXT:  ret
   %result = lshr i16 %a, 9