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[AVR] Fix a bug in 16-bit shifts
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Authored by benshi001 on Feb 12 2021, 3:33 AM.

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Summary

Fix a bug in my prevous commit 50f1aa1db5c59499b40abda1f565a3db1ebd7ee4.

The generated ANDIs in the expansion of pseudo LSLW4/LSLW12/LSR4/LSR12
should only use R16~R31.

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Event Timeline

benshi001 created this revision.Feb 12 2021, 3:33 AM
benshi001 requested review of this revision.Feb 12 2021, 3:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 12 2021, 3:33 AM
aykevl added a comment.EditedFeb 13 2021, 3:13 AM

Thank you for the quick patch! I have verified locally that this does indeed fix the bug (my AVR tests pass again), so this looks good to me.

aykevl accepted this revision.Feb 13 2021, 9:53 AM

@benshi001 can you commit it or should I do it for you?

This revision is now accepted and ready to land.Feb 13 2021, 9:53 AM
This revision was automatically updated to reflect the committed changes.

@benshi001 can you commit it or should I do it for you?

Thanks. I have committed it. And you are appreciated to take a look at my patch https://reviews.llvm.org/D96506,

it is also about shift optimization.

Thank you!
I have created a bug report to include this fix in the LLVM 12 release: https://bugs.llvm.org/show_bug.cgi?id=49176