[AArch64][GlobalISel] Perform load/store extended reg folding with optsize

[paquette]

Summary

GlobalISel was only doing this with minsize. SDAG does this with optsize.

(See: SelectionDAG::shouldOptForSize())

This is a 0.3% code size improvement for CTMark at -Os.

(Best: 1.1% improvements on lencod + pairlocalalign)

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

 /// Return true if it is worth folding MI into an extended register. That is,
 /// if it's safe to pull it into the addressing mode of a load or store as a
 /// shift.
 bool AArch64InstructionSelector::isWorthFoldingIntoExtendedReg(
     MachineInstr &MI, const MachineRegisterInfo &MRI) const {
   // Always fold if there is one use, or if we're optimizing for size.
   Register DefReg = MI.getOperand(0).getReg();
   if (MRI.hasOneNonDBGUse(DefReg) ||
-      MI.getParent()->getParent()->getFunction().hasMinSize())
+      MI.getParent()->getParent()->getFunction().hasOptSize())
     return true;
 
   // It's better to avoid folding and recomputing shifts when we don't have a
   // fastpath.
   if (!STI.hasLSLFast())
     return false;
 
   // We have a fastpath, so folding a shift in and potentially computing it

llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

--- |
   define void @more_than_one_use_shl_lsl_fast(i64* %addr) #1 { ret void }
   define void @more_than_one_use_shl_lsl_slow(i64* %addr) { ret void }
   define void @more_than_one_use_shl_minsize(i64* %addr) #0 { ret void }
   define void @ldrwrox(i64* %addr) { ret void }
   define void @ldrsrox(i64* %addr) { ret void }
   define void @ldrhrox(i64* %addr) { ret void }
   define void @ldbbrox(i64* %addr) { ret void }
   define void @ldrqrox(i64* %addr) { ret void }
-  attributes #0 = { optsize minsize }
+  attributes #0 = { optsize }
   attributes #1 = { "target-features"="+lsl-fast" }
 ...
 
 ---
 name:            ldrxrox_breg_oreg
 alignment:       4
 legalized:       true
 regBankSelected: true