[SPARC] recognize the "rd %pc, reg" special form

[LemonBoy]

LGTM

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
         Op = SparcOperand::CreateToken("%cq", S);
         break;
       case Sparc::WIM:
         Op = SparcOperand::CreateToken("%wim", S);
         break;
       case Sparc::TBR:
         Op = SparcOperand::CreateToken("%tbr", S);
         break;
+      case Sparc::PC:
+        Op = SparcOperand::CreateToken("%pc", S);
+        break;
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
       }
       break;
if (name.equals("otherwin")) {
       RegKind = SparcOperand::rk_Special;
       return true;
     }
     if (name.equals("wstate")) {
       RegNo = Sparc::WSTATE;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
+    if (name.equals("pc")) {
+      RegNo = Sparc::PC;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
   }
   return false;
 }
 
 // Determine if an expression contains a reference to the symbol
 // "_GLOBAL_OFFSET_TABLE_".
 static bool hasGOTReference(const MCExpr *Expr) {
   switch (Expr->getKind()) {

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

static const unsigned ASRRegDecoderTable[] = {
   SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
   SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
   SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
   SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
 
 static const unsigned PRRegDecoderTable[] = {
   SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
   SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
-  SP::OTHERWIN, SP::WSTATE
+  SP::OTHERWIN, SP::WSTATE, SP::PC
 };
 
 static const uint16_t IntPairDecoderTable[] = {
   SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
   SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
   SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
   SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
 };

llvm/lib/Target/Sparc/SparcInstrAliases.td

 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
 
 // mov specialreg, rd -> rd specialreg, rd
 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
+def : InstAlias<"mov %pc, $rd", (RDPC IntRegs:$rd), 0>;
 
 // mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;

llvm/lib/Target/Sparc/SparcInstrInfo.td

def RDWIM : F3_1<2, 0b101010,
          "rd %wim, $rd", []>;
 
   let rs2 = 0, rs1 = 0, Uses=[TBR] in
     def RDTBR : F3_1<2, 0b101011,
          (outs IntRegs:$rd), (ins),
          "rd %tbr, $rd", []>;
 }
 
+// PC don't exist on the SparcV8, only the V9.
+let Predicates = [HasV9] in {
+  let rs2 = 0, rs1 = 5 in
+    def RDPC : F3_1<2, 0b101000,
+         (outs IntRegs:$rd), (ins),
+         "rd %pc, $rd", []>;
+}
+
 // Section B.29 - Write State Register Instructions
 def WRASRrr : F3_1<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                  "wr $rs1, $rs2, $rd", []>;
 def WRASRri : F3_2<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                  "wr $rs1, $simm13, $rd", []>;
 

llvm/lib/Target/Sparc/SparcRegisterInfo.td

 def ASR29 : SparcCtrlReg<29, "ASR29">;
 def ASR30 : SparcCtrlReg<30, "ASR30">;
 def ASR31 : SparcCtrlReg<31, "ASR31">;
 
 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
 def PSR : SparcCtrlReg<0, "PSR">;
 def WIM : SparcCtrlReg<0, "WIM">;
 def TBR : SparcCtrlReg<0, "TBR">;
+// PC on the other hand is only available for SparcV9.
+def PC : SparcCtrlReg<5, "PC">;
 
 def TPC : SparcCtrlReg<0, "TPC">;
 def TNPC : SparcCtrlReg<1, "TNPC">;
 def TSTATE : SparcCtrlReg<2, "TSTATE">;
 def TT : SparcCtrlReg<3, "TT">;
 def TICK : SparcCtrlReg<4, "TICK">;
 def TBA : SparcCtrlReg<5, "TBA">;
 def PSTATE : SparcCtrlReg<6, "PSTATE">;

llvm/test/MC/Sparc/sparcv9-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %otherwin,%i5
         ! V9: rdpr %otherwin, %i5       ! encoding: [0xbb,0x53,0x40,0x00]
         rdpr %otherwin,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %wstate,%i5
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rd %pc, %o7
+        ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
+        rd %pc, %o7