[AMDGPU][MC] Corrected error position for invalid dim modifiers

[dp]

Summary

Error position for an invalid dim modifier may be reported incorrectly.
See bug 49054.

[foad]

Looks OK, but it's a shame to have to repeat the same error message three times in the source.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

7194

All the other errors start with a lower case letter.

[dp]

Fixed issues found by Jay:

• Corrected error message;
• Refactored to avoid duplication of code.

[foad]

Looks good, thanks! Aa an alternative, parseDimId could return Optional<unsigned>.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
 
   void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
 
   void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
                bool IsAtomic = false);
   void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
   void cvtIntersectRay(MCInst &Inst, const OperandVector &Operands);
 
+  bool parseDimId(unsigned &Encoding);
   OperandMatchResultTy parseDim(OperandVector &Operands);
   OperandMatchResultTy parseDPP8(OperandVector &Operands);
   OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
   bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
   int64_t parseDPPCtrlSel(StringRef Ctrl);
   int64_t parseDPPCtrlPerm();
   AMDGPUOperand::Ptr defaultRowMask() const;
   AMDGPUOperand::Ptr defaultBankMask() const;

 bool AMDGPUOperand::isS16Imm() const {
   return isImm() && (isInt<16>(getImm()) || isUInt<16>(getImm()));
 }
 
 bool AMDGPUOperand::isU16Imm() const {
   return isImm() && isUInt<16>(getImm());
 }
 
-OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {
-  if (!isGFX10Plus())
-    return MatchOperand_NoMatch;
-
-  SMLoc S = getLoc();
-
-  if (!trySkipId("dim", AsmToken::Colon))
-    return MatchOperand_NoMatch;
+//===----------------------------------------------------------------------===//
+// dim
+//===----------------------------------------------------------------------===//
 
-  // We want to allow "dim:1D" etc., but the initial 1 is tokenized as an
-  // integer.
+bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {
+  // We want to allow "dim:1D" etc.,
+  // but the initial 1 is tokenized as an integer.
   std::string Token;
   if (isToken(AsmToken::Integer)) {
     SMLoc Loc = getToken().getEndLoc();
     Token = std::string(getTokenStr());
     lex();
     if (getLoc() != Loc)
-      return MatchOperand_ParseFail;
+      return false;
   }
-  if (!isToken(AsmToken::Identifier))
-    return MatchOperand_ParseFail;
-  Token += getTokenStr();
+
+  StringRef Suffix;
+  if (!parseId(Suffix))
+    return false;
+  Token += Suffix;
 
   StringRef DimId = Token;
   if (DimId.startswith("SQ_RSRC_IMG_"))
-    DimId = DimId.substr(12);
+    DimId = DimId.drop_front(12);
 
   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);
   if (!DimInfo)
-    return MatchOperand_ParseFail;
+    return false;
 
-  lex();
+  Encoding = DimInfo->Encoding;
+  return true;
+}
+
+OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {
+  if (!isGFX10Plus())
+    return MatchOperand_NoMatch;
+
+  SMLoc S = getLoc();
+
+  if (!trySkipId("dim", AsmToken::Colon))
+    return MatchOperand_NoMatch;
+
+  unsigned Encoding;
+  SMLoc Loc = getLoc();
+  if (!parseDimId(Encoding)) {
+    Error(Loc, "invalid dim value");
+    return MatchOperand_ParseFail;
+  }
 
-  Operands.push_back(AMDGPUOperand::CreateImm(this, DimInfo->Encoding, S,
+  Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,
                                               AMDGPUOperand::ImmTyDim));
   return MatchOperand_Success;
 }
 
+//===----------------------------------------------------------------------===//
+// dpp
+//===----------------------------------------------------------------------===//
+
 OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
   SMLoc S = getLoc();
 
   if (!isGFX10Plus() || !trySkipId("dpp8", AsmToken::Colon))
     return MatchOperand_NoMatch;
 
   // dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]
 

llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s

 
 image_sample_c_d_cl v[0:3], [v0, v1, v2, v3, v4, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
 // NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: image address size does not match dim and a16
 
 image_sample_c_d_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
 // NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: image address size does not match dim and a16
 
 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 // CHECK: error: expected an operation name or an absolute expression
 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 // CHECK-NEXT:{{^}}                          ^
 
 //==============================================================================
 // failed parsing operand.
 
-image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
-// CHECK-NEXT:{{^}}                                              ^
-
 v_ceil_f16 v0, abs(neg(1))
 // CHECK: error: failed parsing operand.
 // CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
 // CHECK-NEXT:{{^}}                   ^
 
-image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
-// CHECK-NEXT:{{^}}                                                  ^
-
 //==============================================================================
 // first register index should not exceed second index
 
 s_mov_b64 s[10:11], s[1:0]
 // CHECK: error: first register index should not exceed second index
 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0]
 // CHECK-NEXT:{{^}}                      ^
 

 // invalid counter name x
 
 s_waitcnt vmcnt(0) & expcnt(0) x(0)
 // CHECK: error: invalid counter name x
 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)
 // CHECK-NEXT:{{^}}                               ^
 
 //==============================================================================
+// invalid dim value
+
+image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
+// CHECK: error: invalid dim value
+// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
+// CHECK-NEXT:{{^}}                                            ^
+
+image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
+// CHECK: error: invalid dim value
+// CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
+// CHECK-NEXT:{{^}}                                                  ^
+
+image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
+// CHECK: error: invalid dim value
+// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
+// CHECK-NEXT:{{^}}                                            ^
+
+//==============================================================================
 // invalid dst_sel value
 
 v_mov_b32_sdwa v5, v1 dst_sel:WORD
 // CHECK: error: invalid dst_sel value
 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD
 // CHECK-NEXT:{{^}}                              ^
 
 //==============================================================================