[update_llc_test_checks] Support AVR

[benshi001]

Summary

Add AVR to update_llc_test_checks.py along with several tests.

[arichardson]

It might be worth adding a test in llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ but I'd say that's not essential to land this patch.

llvm/test/CodeGen/AVR/neg.ll

14–15

These incorrect CHECK lines should be removed.

[MaskRay]

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_function_name.ll

5

Some existing files have such ; lines but they just editing the file harder. So they should be deleted.

[MaskRay]

You missed a main test file in llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ (and add a REQUIRES:)

[benshi001]

In D95240#2517790, @MaskRay wrote:

You missed a main test file in llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ (and add a REQUIRES:)

Sorry. I forget to do "git add -A" for some files. Now they are all added. You are appreciated to help me review again. :)

[arichardson]

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_generated_funcs.ll.generated.expected

1

I'd say the avr_function_name.ll test is sufficient to show that the script works for AVR.

This test is not actually testing for any generated functions (I guess -enable-machine-outliner does nothing?)

[benshi001]

Done. The unnecessary tests are removed. Only the avr_function_name.ll is kept.

llvm/test/CodeGen/AVR/com.ll

-; RUN: llc < %s -march=avr | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=avr | FileCheck %s
 
 define i8 @com8(i8 %x) {
 ; CHECK-LABEL: com8:
-; CHECK: com r24
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    com r24
+; CHECK-NEXT:    ret
   %neg = xor i8 %x, -1
   ret i8 %neg
 }
 
 define i16 @com16(i16 %x) {
 ; CHECK-LABEL: com16:
-; CHECK: com r24
-; CHECK: com r25
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    com r24
+; CHECK-NEXT:    com r25
+; CHECK-NEXT:    ret
   %neg = xor i16 %x, -1
   ret i16 %neg
 }
 
 define i32 @com32(i32 %x) {
 ; CHECK-LABEL: com32:
-; CHECK: com r22
-; CHECK: com r23
-; CHECK: com r24
-; CHECK: com r25
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    com r22
+; CHECK-NEXT:    com r23
+; CHECK-NEXT:    com r24
+; CHECK-NEXT:    com r25
+; CHECK-NEXT:    ret
   %neg = xor i32 %x, -1
   ret i32 %neg
 }
 
 define i64 @com64(i64 %x) {
 ; CHECK-LABEL: com64:
-; CHECK: com r18
-; CHECK: com r19
-; CHECK: com r20
-; CHECK: com r21
-; CHECK: com r22
-; CHECK: com r23
-; CHECK: com r24
-; CHECK: com r25
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    com r18
+; CHECK-NEXT:    com r19
+; CHECK-NEXT:    com r20
+; CHECK-NEXT:    com r21
+; CHECK-NEXT:    com r22
+; CHECK-NEXT:    com r23
+; CHECK-NEXT:    com r24
+; CHECK-NEXT:    com r25
+; CHECK-NEXT:    ret
   %neg = xor i64 %x, -1
   ret i64 %neg
 }

llvm/test/CodeGen/AVR/neg.ll

-; RUN: llc < %s -march=avr | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=avr | FileCheck %s
 
 define i8 @neg8(i8 %x) {
 ; CHECK-LABEL: neg8:
-; CHECK: neg r24
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    neg r24
+; CHECK-NEXT:    ret
   %sub = sub i8 0, %x
   ret i8 %sub
 }
 
 define i16 @neg16(i16 %x) {
 ; CHECK-LABEL: neg16:
-; CHECK:       neg r25
-; CHECK-next:  neg r24
-; CHECK-next:  sbci r25, 0
-; CHECK-next:  ret
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    neg r25
+; CHECK-NEXT:    neg r24
+; CHECK-NEXT:    sbci r25, 0
+; CHECK-NEXT:    ret
   %sub = sub i16 0, %x
   ret i16 %sub
 }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_function_name.ll

+; Check that we accept functions with '$' in the name.
+
+; RUN: llc -mtriple=avr < %s | FileCheck %s
+
+define hidden i8 @"_Z54bar$ompvariant$bar"() {
+entry:
+  ret i8 2
+}

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_function_name.ll.expected

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; Check that we accept functions with '$' in the name.
+
+; RUN: llc -mtriple=avr < %s | FileCheck %s
+
+define hidden i8 @"_Z54bar$ompvariant$bar"() {
+; CHECK-LABEL: _Z54bar$ompvariant$bar:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    ldi r24, 2
+; CHECK-NEXT:    ret
+entry:
+  ret i8 2
+}

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_generated_funcs.ll

+; RUN: llc -enable-machine-outliner -mtriple=avr < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_generated_funcs.ll.generated.expected

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
+; RUN: llc -enable-machine-outliner -mtriple=avr < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
+; CHECK-LABEL: check_boundaries:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    sbiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    ldi r24, 0
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+19, r24
+; CHECK-NEXT:    std Y+20, r25
+; CHECK-NEXT:    std Y+17, r24
+; CHECK-NEXT:    std Y+18, r25
+; CHECK-NEXT:    ldi r18, 0
+; CHECK-NEXT:    cpi r18, 0
+; CHECK-NEXT:    ldi r18, 1
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    breq .LBB0_2
+; CHECK-NEXT:  ; %bb.1:
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    rjmp .LBB0_3
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    std Y+11, r24
+; CHECK-NEXT:    std Y+12, r25
+; CHECK-NEXT:    ldi r20, 2
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+9, r20
+; CHECK-NEXT:    std Y+10, r21
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r18
+; CHECK-NEXT:    std Y+14, r19
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    ldi r20, 3
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r24
+; CHECK-NEXT:    std Y+4, r25
+; CHECK-NEXT:    ldi r20, 4
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+1, r20
+; CHECK-NEXT:    std Y+2, r21
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    ldd r22, Y+13
+; CHECK-NEXT:    ldd r23, Y+14
+; CHECK-NEXT:    ldd r26, Y+15
+; CHECK-NEXT:    ldd r27, Y+16
+; CHECK-NEXT:    ldi r20, 1
+; CHECK-NEXT:    cp r22, r24
+; CHECK-NEXT:    cpc r23, r25
+; CHECK-NEXT:    cpc r26, r24
+; CHECK-NEXT:    cpc r27, r25
+; CHECK-NEXT:    brne .LBB0_5
+; CHECK-NEXT:  ; %bb.4:
+; CHECK-NEXT:    ldi r20, 0
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    andi r20, 1
+; CHECK-NEXT:    cpi r20, 0
+; CHECK-NEXT:    breq .LBB0_7
+; CHECK-NEXT:  ; %bb.6:
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    rjmp .LBB0_8
+; CHECK-NEXT:  .LBB0_7:
+; CHECK-NEXT:    std Y+11, r24
+; CHECK-NEXT:    std Y+12, r25
+; CHECK-NEXT:    ldi r20, 2
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+9, r20
+; CHECK-NEXT:    std Y+10, r21
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r18
+; CHECK-NEXT:    std Y+14, r19
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    ldi r18, 3
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    std Y+3, r24
+; CHECK-NEXT:    std Y+4, r25
+; CHECK-NEXT:    ldi r24, 4
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    std Y+1, r24
+; CHECK-NEXT:    std Y+2, r25
+; CHECK-NEXT:  .LBB0_8:
+; CHECK-NEXT:    ldi r22, 0
+; CHECK-NEXT:    ldi r23, 0
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    adiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+;
+; CHECK-LABEL: main:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    sbiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    ldi r22, 0
+; CHECK-NEXT:    ldi r23, 0
+; CHECK-NEXT:    sts x+3, r23
+; CHECK-NEXT:    sts x+2, r22
+; CHECK-NEXT:    ldi r24, 1
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    sts x+1, r25
+; CHECK-NEXT:    sts x, r24
+; CHECK-NEXT:    std Y+19, r22
+; CHECK-NEXT:    std Y+20, r23
+; CHECK-NEXT:    std Y+17, r22
+; CHECK-NEXT:    std Y+18, r23
+; CHECK-NEXT:    std Y+15, r22
+; CHECK-NEXT:    std Y+16, r23
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+11, r22
+; CHECK-NEXT:    std Y+12, r23
+; CHECK-NEXT:    ldi r18, 2
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    std Y+9, r18
+; CHECK-NEXT:    std Y+10, r19
+; CHECK-NEXT:    std Y+7, r22
+; CHECK-NEXT:    std Y+8, r23
+; CHECK-NEXT:    ldi r20, 3
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r22
+; CHECK-NEXT:    std Y+4, r23
+; CHECK-NEXT:    ldi r30, 4
+; CHECK-NEXT:    ldi r31, 0
+; CHECK-NEXT:    std Y+1, r30
+; CHECK-NEXT:    std Y+2, r31
+; CHECK-NEXT:    ;APP
+; CHECK-NEXT:    ;NO_APP
+; CHECK-NEXT:    std Y+11, r22
+; CHECK-NEXT:    std Y+12, r23
+; CHECK-NEXT:    std Y+9, r18
+; CHECK-NEXT:    std Y+10, r19
+; CHECK-NEXT:    std Y+15, r22
+; CHECK-NEXT:    std Y+16, r23
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+7, r22
+; CHECK-NEXT:    std Y+8, r23
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r22
+; CHECK-NEXT:    std Y+4, r23
+; CHECK-NEXT:    std Y+1, r30
+; CHECK-NEXT:    std Y+2, r31
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    adiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/avr_generated_funcs.ll.nogenerated.expected

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -enable-machine-outliner -mtriple=avr < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+; CHECK-LABEL: check_boundaries:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    sbiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    ldi r24, 0
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+19, r24
+; CHECK-NEXT:    std Y+20, r25
+; CHECK-NEXT:    std Y+17, r24
+; CHECK-NEXT:    std Y+18, r25
+; CHECK-NEXT:    ldi r18, 0
+; CHECK-NEXT:    cpi r18, 0
+; CHECK-NEXT:    ldi r18, 1
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    breq .LBB0_2
+; CHECK-NEXT:  ; %bb.1:
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    rjmp .LBB0_3
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    std Y+11, r24
+; CHECK-NEXT:    std Y+12, r25
+; CHECK-NEXT:    ldi r20, 2
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+9, r20
+; CHECK-NEXT:    std Y+10, r21
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r18
+; CHECK-NEXT:    std Y+14, r19
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    ldi r20, 3
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r24
+; CHECK-NEXT:    std Y+4, r25
+; CHECK-NEXT:    ldi r20, 4
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+1, r20
+; CHECK-NEXT:    std Y+2, r21
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    ldd r22, Y+13
+; CHECK-NEXT:    ldd r23, Y+14
+; CHECK-NEXT:    ldd r26, Y+15
+; CHECK-NEXT:    ldd r27, Y+16
+; CHECK-NEXT:    ldi r20, 1
+; CHECK-NEXT:    cp r22, r24
+; CHECK-NEXT:    cpc r23, r25
+; CHECK-NEXT:    cpc r26, r24
+; CHECK-NEXT:    cpc r27, r25
+; CHECK-NEXT:    brne .LBB0_5
+; CHECK-NEXT:  ; %bb.4:
+; CHECK-NEXT:    ldi r20, 0
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    andi r20, 1
+; CHECK-NEXT:    cpi r20, 0
+; CHECK-NEXT:    breq .LBB0_7
+; CHECK-NEXT:  ; %bb.6:
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    rjmp .LBB0_8
+; CHECK-NEXT:  .LBB0_7:
+; CHECK-NEXT:    std Y+11, r24
+; CHECK-NEXT:    std Y+12, r25
+; CHECK-NEXT:    ldi r20, 2
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+9, r20
+; CHECK-NEXT:    std Y+10, r21
+; CHECK-NEXT:    std Y+15, r24
+; CHECK-NEXT:    std Y+16, r25
+; CHECK-NEXT:    std Y+13, r18
+; CHECK-NEXT:    std Y+14, r19
+; CHECK-NEXT:    std Y+7, r24
+; CHECK-NEXT:    std Y+8, r25
+; CHECK-NEXT:    ldi r18, 3
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    std Y+5, r18
+; CHECK-NEXT:    std Y+6, r19
+; CHECK-NEXT:    std Y+3, r24
+; CHECK-NEXT:    std Y+4, r25
+; CHECK-NEXT:    ldi r24, 4
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    std Y+1, r24
+; CHECK-NEXT:    std Y+2, r25
+; CHECK-NEXT:  .LBB0_8:
+; CHECK-NEXT:    ldi r22, 0
+; CHECK-NEXT:    ldi r23, 0
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    adiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    sbiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    ldi r22, 0
+; CHECK-NEXT:    ldi r23, 0
+; CHECK-NEXT:    sts x+3, r23
+; CHECK-NEXT:    sts x+2, r22
+; CHECK-NEXT:    ldi r24, 1
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:    sts x+1, r25
+; CHECK-NEXT:    sts x, r24
+; CHECK-NEXT:    std Y+19, r22
+; CHECK-NEXT:    std Y+20, r23
+; CHECK-NEXT:    std Y+17, r22
+; CHECK-NEXT:    std Y+18, r23
+; CHECK-NEXT:    std Y+15, r22
+; CHECK-NEXT:    std Y+16, r23
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+11, r22
+; CHECK-NEXT:    std Y+12, r23
+; CHECK-NEXT:    ldi r18, 2
+; CHECK-NEXT:    ldi r19, 0
+; CHECK-NEXT:    std Y+9, r18
+; CHECK-NEXT:    std Y+10, r19
+; CHECK-NEXT:    std Y+7, r22
+; CHECK-NEXT:    std Y+8, r23
+; CHECK-NEXT:    ldi r20, 3
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r22
+; CHECK-NEXT:    std Y+4, r23
+; CHECK-NEXT:    ldi r30, 4
+; CHECK-NEXT:    ldi r31, 0
+; CHECK-NEXT:    std Y+1, r30
+; CHECK-NEXT:    std Y+2, r31
+; CHECK-NEXT:    ;APP
+; CHECK-NEXT:    ;NO_APP
+; CHECK-NEXT:    std Y+11, r22
+; CHECK-NEXT:    std Y+12, r23
+; CHECK-NEXT:    std Y+9, r18
+; CHECK-NEXT:    std Y+10, r19
+; CHECK-NEXT:    std Y+15, r22
+; CHECK-NEXT:    std Y+16, r23
+; CHECK-NEXT:    std Y+13, r24
+; CHECK-NEXT:    std Y+14, r25
+; CHECK-NEXT:    std Y+7, r22
+; CHECK-NEXT:    std Y+8, r23
+; CHECK-NEXT:    std Y+5, r20
+; CHECK-NEXT:    std Y+6, r21
+; CHECK-NEXT:    std Y+3, r22
+; CHECK-NEXT:    std Y+4, r23
+; CHECK-NEXT:    std Y+1, r30
+; CHECK-NEXT:    std Y+2, r31
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    adiw r28, 20
+; CHECK-NEXT:    in r0, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    out 62, r29
+; CHECK-NEXT:    out 63, r0
+; CHECK-NEXT:    out 61, r28
+; CHECK-NEXT:    pop r29
+; CHECK-NEXT:    pop r28
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/avr-function-name.test

+# REQUIRES: avr-registered-target
+## Check that functions names with '$' are processed correctly
+
+# RUN: cp -f %S/Inputs/avr_function_name.ll %t.ll && %update_llc_test_checks %t.ll
+# RUN: diff -u %S/Inputs/avr_function_name.ll.expected %t.ll

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/avr_generated_funcs.test

+# REQUIRES: avr-registered-target
+
+## Check that generated functions are included.
+# RUN: cp -f %S/Inputs/avr_generated_funcs.ll %t.ll && %update_llc_test_checks --include-generated-funcs %t.ll
+# RUN: diff -u %t.ll %S/Inputs/avr_generated_funcs.ll.generated.expected
+
+## Check that running the script again does not change the result:
+# RUN: %update_llc_test_checks --include-generated-funcs %t.ll
+# RUN: diff -u %t.ll %S/Inputs/avr_generated_funcs.ll.generated.expected
+
+## Check that generated functions are not included.
+# RUN: cp -f %S/Inputs/avr_generated_funcs.ll %t.ll && %update_llc_test_checks %t.ll
+# RUN: diff -u %t.ll %S/Inputs/avr_generated_funcs.ll.nogenerated.expected
+
+## Check that running the script again does not change the result:
+# RUN: %update_llc_test_checks %t.ll
+# RUN: diff -u %t.ll %S/Inputs/avr_generated_funcs.ll.nogenerated.expected

llvm/utils/UpdateTestChecks/asm.py

ASM_FUNCTION_MIPS_RE = re.compile(
     flags=(re.M | re.S))
 
 ASM_FUNCTION_MSP430_RE = re.compile(
     r'^_?(?P<func>[^:]+):[ \t]*;+[ \t]*@"?(?P=func)"?\n[^:]*?'
     r'(?P<body>.*?)\n'
     r'(\$|\.L)func_end[0-9]+:\n',             # $func_end0:
     flags=(re.M | re.S))
 
+ASM_FUNCTION_AVR_RE = re.compile(
+    r'^_?(?P<func>[^:]+):[ \t]*;+[ \t]*@"?(?P=func)"?\n[^:]*?'
+    r'(?P<body>.*?)\n'
+    r'.Lfunc_end[0-9]+:\n',
+    flags=(re.M | re.S))
+
 ASM_FUNCTION_PPC_RE = re.compile(
     r'#[ \-\t]*Begin function (?P<func>[^.:]+)\n'
     r'.*?'
     r'^[_.]?(?P=func):(?:[ \t]*#+[ \t]*@"?(?P=func)"?)?\n'
     r'(?:^[^#]*\n)*'
     r'(?P<body>.*?)\n'
     # This list is incomplete
     r'(?:^[ \t]*(?:\.(?:long|quad|v?byte)[ \t]+[^\n]+)\n)*'
def scrub_asm_msp430(asm, args):
   # whitespace in place.
   asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
   # Expand the tabs used for indentation.
   asm = string.expandtabs(asm, 2)
   # Strip trailing whitespace.
   asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
   return asm
 
+def scrub_asm_avr(asm, args):
+  # Scrub runs of whitespace out of the assembly, but leave the leading
+  # whitespace in place.
+  asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
+  # Expand the tabs used for indentation.
+  asm = string.expandtabs(asm, 2)
+  # Strip trailing whitespace.
+  asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
+  return asm
+
 def scrub_asm_riscv(asm, args):
   # Scrub runs of whitespace out of the assembly, but leave the leading
   # whitespace in place.
   asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
   # Expand the tabs used for indentation.
   asm = string.expandtabs(asm, 2)
   # Strip trailing whitespace.
   asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
target_handlers = {
       'armv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
       'armv7-apple-darwin': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_DARWIN_RE),
       'thumb': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
       'thumb-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
       'thumbv5-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
       'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
       'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE),
       'msp430': (scrub_asm_msp430, ASM_FUNCTION_MSP430_RE),
+      'avr': (scrub_asm_avr, ASM_FUNCTION_AVR_RE),
       'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
       'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
       'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
       'riscv64': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
       'lanai': (scrub_asm_lanai, ASM_FUNCTION_LANAI_RE),
       'sparc': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
       's390x': (scrub_asm_systemz, ASM_FUNCTION_SYSTEMZ_RE),
       'wasm32': (scrub_asm_wasm32, ASM_FUNCTION_WASM32_RE),