[mlir]][SPIRV] Define OrderedOp and UnorderedOp and add lowerings from Standard.

[mravishankar]

Summary

Define OrderedOp and UnorderedOp instructions in SPIR-V and convert
cmpf operations with ord and uno tag to these instructions
respectively.

Depends On D95097

[antiagainst]

Thanks for fixing this!

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

 def SPV_OC_OpFDiv                      : I32EnumAttrCase<"OpFDiv", 136>;
 def SPV_OC_OpUMod                      : I32EnumAttrCase<"OpUMod", 137>;
 def SPV_OC_OpSRem                      : I32EnumAttrCase<"OpSRem", 138>;
 def SPV_OC_OpSMod                      : I32EnumAttrCase<"OpSMod", 139>;
 def SPV_OC_OpFRem                      : I32EnumAttrCase<"OpFRem", 140>;
 def SPV_OC_OpFMod                      : I32EnumAttrCase<"OpFMod", 141>;
 def SPV_OC_OpMatrixTimesScalar         : I32EnumAttrCase<"OpMatrixTimesScalar", 143>;
 def SPV_OC_OpMatrixTimesMatrix         : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>;
+def SPV_OC_OpOrdered                   : I32EnumAttrCase<"OpOrdered", 162>;
+def SPV_OC_OpUnordered                 : I32EnumAttrCase<"OpUnordered", 163>;
 def SPV_OC_OpLogicalEqual              : I32EnumAttrCase<"OpLogicalEqual", 164>;
 def SPV_OC_OpLogicalNotEqual           : I32EnumAttrCase<"OpLogicalNotEqual", 165>;
 def SPV_OC_OpLogicalOr                 : I32EnumAttrCase<"OpLogicalOr", 166>;
 def SPV_OC_OpLogicalAnd                : I32EnumAttrCase<"OpLogicalAnd", 167>;
 def SPV_OC_OpLogicalNot                : I32EnumAttrCase<"OpLogicalNot", 168>;
 def SPV_OC_OpSelect                    : I32EnumAttrCase<"OpSelect", 169>;
 def SPV_OC_OpIEqual                    : I32EnumAttrCase<"OpIEqual", 170>;
 def SPV_OC_OpINotEqual                 : I32EnumAttrCase<"OpINotEqual", 171>;
SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", [
       SPV_OC_OpCompositeConstruct, SPV_OC_OpCompositeExtract,
       SPV_OC_OpCompositeInsert, SPV_OC_OpTranspose, SPV_OC_OpConvertFToU,
       SPV_OC_OpConvertFToS, SPV_OC_OpConvertSToF, SPV_OC_OpConvertUToF,
       SPV_OC_OpUConvert, SPV_OC_OpSConvert, SPV_OC_OpFConvert, SPV_OC_OpBitcast,
       SPV_OC_OpSNegate, SPV_OC_OpFNegate, SPV_OC_OpIAdd, SPV_OC_OpFAdd,
       SPV_OC_OpISub, SPV_OC_OpFSub, SPV_OC_OpIMul, SPV_OC_OpFMul, SPV_OC_OpUDiv,
       SPV_OC_OpSDiv, SPV_OC_OpFDiv, SPV_OC_OpUMod, SPV_OC_OpSRem, SPV_OC_OpSMod,
       SPV_OC_OpFRem, SPV_OC_OpFMod, SPV_OC_OpMatrixTimesScalar,
-      SPV_OC_OpMatrixTimesMatrix, SPV_OC_OpLogicalEqual, SPV_OC_OpLogicalNotEqual,
-      SPV_OC_OpLogicalOr, SPV_OC_OpLogicalAnd, SPV_OC_OpLogicalNot, SPV_OC_OpSelect,
-      SPV_OC_OpIEqual, SPV_OC_OpINotEqual, SPV_OC_OpUGreaterThan,
-      SPV_OC_OpSGreaterThan, SPV_OC_OpUGreaterThanEqual, SPV_OC_OpSGreaterThanEqual,
-      SPV_OC_OpULessThan, SPV_OC_OpSLessThan, SPV_OC_OpULessThanEqual,
-      SPV_OC_OpSLessThanEqual, SPV_OC_OpFOrdEqual, SPV_OC_OpFUnordEqual,
-      SPV_OC_OpFOrdNotEqual, SPV_OC_OpFUnordNotEqual, SPV_OC_OpFOrdLessThan,
-      SPV_OC_OpFUnordLessThan, SPV_OC_OpFOrdGreaterThan, SPV_OC_OpFUnordGreaterThan,
+      SPV_OC_OpMatrixTimesMatrix, SPV_OC_OpOrdered, SPV_OC_OpUnordered,
+      SPV_OC_OpLogicalEqual, SPV_OC_OpLogicalNotEqual, SPV_OC_OpLogicalOr,
+      SPV_OC_OpLogicalAnd, SPV_OC_OpLogicalNot, SPV_OC_OpSelect, SPV_OC_OpIEqual,
+      SPV_OC_OpINotEqual, SPV_OC_OpUGreaterThan, SPV_OC_OpSGreaterThan,
+      SPV_OC_OpUGreaterThanEqual, SPV_OC_OpSGreaterThanEqual, SPV_OC_OpULessThan,
+      SPV_OC_OpSLessThan, SPV_OC_OpULessThanEqual, SPV_OC_OpSLessThanEqual,
+      SPV_OC_OpFOrdEqual, SPV_OC_OpFUnordEqual, SPV_OC_OpFOrdNotEqual,
+      SPV_OC_OpFUnordNotEqual, SPV_OC_OpFOrdLessThan, SPV_OC_OpFUnordLessThan,
+      SPV_OC_OpFOrdGreaterThan, SPV_OC_OpFUnordGreaterThan,
       SPV_OC_OpFOrdLessThanEqual, SPV_OC_OpFUnordLessThanEqual,
       SPV_OC_OpFOrdGreaterThanEqual, SPV_OC_OpFUnordGreaterThanEqual,
       SPV_OC_OpShiftRightLogical, SPV_OC_OpShiftRightArithmetic,
       SPV_OC_OpShiftLeftLogical, SPV_OC_OpBitwiseOr, SPV_OC_OpBitwiseXor,
       SPV_OC_OpBitwiseAnd, SPV_OC_OpNot, SPV_OC_OpBitFieldInsert,
       SPV_OC_OpBitFieldSExtract, SPV_OC_OpBitFieldUExtract, SPV_OC_OpBitReverse,
       SPV_OC_OpBitCount, SPV_OC_OpControlBarrier, SPV_OC_OpMemoryBarrier,
       SPV_OC_OpAtomicCompareExchangeWeak, SPV_OC_OpAtomicIIncrement,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td

let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
+def SPV_OrderedOp : SPV_LogicalBinaryOp<"Ordered", SPV_Float, [Commutative]> {
+  let summary = [{
+    Result is true if both x == x and y == y are true, where IEEE comparison
+    is used, otherwise result is false.
+  }];
+
+  let description = [{
+    Result Type must be a scalar or vector of Boolean type.
+
+    x must be a scalar or vector of floating-point type.  It must have the
+    same number of components as Result Type.
+
+    y must have the same type as x.
+
+     Results are computed per component.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    float-scalar-vector-type ::= float-type |
+                                 `vector<` integer-literal `x` float-type `>`
+    ordered-op ::= ssa-id `=` `spv.Ordered` ssa-use, ssa-use
+    ```mlir
+
+    #### Example:
+
+    ```
+    %4 = spv.Ordered %0, %1 : f32
+    %5 = spv.Ordered %2, %3 : vector<4xf32>
+    ```
+  }];
+}
+
+// -----
+
 def SPV_SGreaterThanOp : SPV_LogicalBinaryOp<"SGreaterThan",
                                              SPV_Integer,
                                              [UsableInSpecConstantOp, SignedOp]> {
   let summary = [{
     Signed-integer comparison if Operand 1 is greater than  Operand 2.
   }];
 
   let description = [{
let description = [{
     %5 = spv.ULessThan %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
+def SPV_UnorderedOp : SPV_LogicalBinaryOp<"Unordered", SPV_Float, [Commutative]> {
+  let summary = [{
+    Result is true if either x or y is an IEEE NaN, otherwise result is
+    false.
+  }];
+
+  let description = [{
+    Result Type must be a scalar or vector of Boolean type.
+
+    x must be a scalar or vector of floating-point type.  It must have the
+    same number of components as Result Type.
+
+    y must have the same type as x.
+
+     Results are computed per component.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    float-scalar-vector-type ::= float-type |
+                                 `vector<` integer-literal `x` float-type `>`
+    unordered-op ::= ssa-id `=` `spv.Unordered` ssa-use, ssa-use
+    ```mlir
+
+    #### Example:
+
+    ```
+    %4 = spv.Unordered %0, %1 : f32
+    %5 = spv.Unordered %2, %3 : vector<4xf32>
+    ```
+  }];
+}
+
+// -----
+
 def SPV_ULessThanEqualOp : SPV_LogicalBinaryOp<"ULessThanEqual",
                                                SPV_Integer,
                                                [UnsignedOp,
                                                 UsableInSpecConstantOp]> {
   let summary = [{
     Unsigned-integer comparison if Operand 1 is less than or equal to
     Operand 2.
   }];

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp

case cmpPredicate:                                                           \
 
     // Ordered.
     DISPATCH(CmpFPredicate::OEQ, spirv::FOrdEqualOp);
     DISPATCH(CmpFPredicate::OGT, spirv::FOrdGreaterThanOp);
     DISPATCH(CmpFPredicate::OGE, spirv::FOrdGreaterThanEqualOp);
     DISPATCH(CmpFPredicate::OLT, spirv::FOrdLessThanOp);
     DISPATCH(CmpFPredicate::OLE, spirv::FOrdLessThanEqualOp);
     DISPATCH(CmpFPredicate::ONE, spirv::FOrdNotEqualOp);
+    DISPATCH(CmpFPredicate::ORD, spirv::OrderedOp);
     // Unordered.
     DISPATCH(CmpFPredicate::UEQ, spirv::FUnordEqualOp);
     DISPATCH(CmpFPredicate::UGT, spirv::FUnordGreaterThanOp);
     DISPATCH(CmpFPredicate::UGE, spirv::FUnordGreaterThanEqualOp);
     DISPATCH(CmpFPredicate::ULT, spirv::FUnordLessThanOp);
     DISPATCH(CmpFPredicate::ULE, spirv::FUnordLessThanEqualOp);
     DISPATCH(CmpFPredicate::UNE, spirv::FUnordNotEqualOp);
+    DISPATCH(CmpFPredicate::UNO, spirv::UnorderedOp);
 
 #undef DISPATCH
 
   default:
     break;
   }
   return failure();
 }

mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir

func @cmpf(%arg0 : f32, %arg1 : f32) {
   // CHECK: spv.FUnordGreaterThanEqual
   %9 = cmpf uge, %arg0, %arg1 : f32
   // CHECK: spv.FUnordLessThan
   %10 = cmpf ult, %arg0, %arg1 : f32
   // CHECK: FUnordLessThanEqual
   %11 = cmpf ule, %arg0, %arg1 : f32
   // CHECK: spv.FUnordNotEqual
   %12 = cmpf une, %arg0, %arg1 : f32
+  // CHECK: spv.Ordered
+  %13 = cmpf ord, %arg0, %arg1 : f32
+  // CHECK: spv.Unordered
+  %14 = cmpf uno, %arg0, %arg1 : f32
   return
 }
 
 //===----------------------------------------------------------------------===//
 // std.cmpi
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @cmpi

mlir/test/Target/SPIRV/logical-ops.mlir

spv.func @cmpf(%arg0 : f32, %arg1 : f32) "None" {
     // CHECK: spv.FUnordGreaterThanEqual
     %9 = spv.FUnordGreaterThanEqual %arg0, %arg1 : f32
     // CHECK: spv.FUnordLessThan
     %10 = spv.FUnordLessThan %arg0, %arg1 : f32
     // CHECK: spv.FUnordLessThanEqual
     %11 = spv.FUnordLessThanEqual %arg0, %arg1 : f32
     // CHECK: spv.FUnordNotEqual
     %12 = spv.FUnordNotEqual %arg0, %arg1 : f32
+    // CHECK: spv.Ordered
+    %13 = spv.Ordered %arg0, %arg1 : f32
+    // CHECK: spv.Unordered
+    %14 = spv.Unordered %arg0, %arg1 : f32
     spv.Return
   }
 }
 
 // -----
 
 spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   spv.specConstant @condition_scalar = true

mlir/utils/spirv/define_inst.sh

 shift
 shift
 
 current_file="$(readlink -f "$0")"
 current_dir="$(dirname "$current_file")"
 
 python3 ${current_dir}/gen_spirv_dialect.py \
   --op-td-path \
-  ${current_dir}/../../include/mlir/Dialect/SPIRV/${file_name} \
+  ${current_dir}/../../include/mlir/Dialect/SPIRV/IR/${file_name} \
   --inst-category $baseclass --new-inst "$@"
 
 ${current_dir}/define_opcodes.sh "$@"