[AMDGPU][MC][GFX10] Improved dpp8 errors handling

[rampitec]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

7274

Just use getLoc() here? Loc does not seem to be used otherwise.

[dp]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

7274

The intention was to save the location before calling parseAbsoluteExpression. If the expression value is out of bounds, and we call getLoc() later, we will refer an incorrect error position (the next token after the expression).

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
 
   if (!isGFX10Plus() || !trySkipId("dpp8", AsmToken::Colon))
     return MatchOperand_NoMatch;
 
   // dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]
 
   int64_t Sels[8];
 
-  if (!trySkipToken(AsmToken::LBrac))
+  if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
     return MatchOperand_ParseFail;
 
-  if (getParser().parseAbsoluteExpression(Sels[0]))
-    return MatchOperand_ParseFail;
-  if (0 > Sels[0] || 7 < Sels[0])
-    return MatchOperand_ParseFail;
-
-  for (size_t i = 1; i < 8; ++i) {
-    if (!trySkipToken(AsmToken::Comma))
+  for (size_t i = 0; i < 8; ++i) {
+    if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
       return MatchOperand_ParseFail;
 
+    SMLoc Loc = getLoc();
     if (getParser().parseAbsoluteExpression(Sels[i]))
       return MatchOperand_ParseFail;
-    if (0 > Sels[i] || 7 < Sels[i])
+    if (0 > Sels[i] || 7 < Sels[i]) {
+      Error(Loc, "expected a 3-bit value");
       return MatchOperand_ParseFail;
     }
+  }
 
-  if (!trySkipToken(AsmToken::RBrac))
+  if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
     return MatchOperand_ParseFail;
 
   unsigned DPP8 = 0;
   for (size_t i = 0; i < 8; ++i)
     DPP8 |= (Sels[i] << (i * 3));
 
   Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));
   return MatchOperand_Success;

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // CHECK-NEXT:{{^}}                         ^
 
 s_atomic_swap s5, s[2:3], 0x1FFFFF
 // CHECK: error: expected a 21-bit signed offset
 // CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
 // CHECK-NEXT:{{^}}                          ^
 
 //==============================================================================
+// expected a 3-bit value
+
+v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK-NEXT:{{^}}                           ^
+
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK-NEXT:{{^}}                                 ^
+
+//==============================================================================
 // expected a 5-character mask
 
 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 // CHECK: error: expected a 5-character mask
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 // CHECK-NEXT:{{^}}                                                   ^
 
 //==============================================================================

 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 // CHECK-NEXT:{{^}}                                         ^
 
 v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 // CHECK: error: expected a closing square bracket
 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 // CHECK-NEXT:{{^}}                                       ^
 
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK: error: expected a closing square bracket
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK-NEXT:{{^}}                                          ^
+
 //==============================================================================
 // expected a colon
 
 ds_swizzle_b32 v8, v2 offset
 // CHECK: error: expected a colon
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset
 // CHECK-NEXT:{{^}}                            ^
 

 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1,2 3), s2
 // CHECK-NEXT:{{^}}                        ^
 
 v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 // CHECK: error: expected a comma
 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 // CHECK-NEXT:{{^}}                                  ^
 
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK: error: expected a comma
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK-NEXT:{{^}}                                        ^
+
 //==============================================================================
 // expected a comma or a closing parenthesis
 
 s_setreg_b32  hwreg(1 2,3), s2
 // CHECK: error: expected a comma or a closing parenthesis
 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1 2,3), s2
 // CHECK-NEXT:{{^}}                      ^
 

 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 // CHECK-NEXT:{{^}}                                                             ^
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 // CHECK: error: expected absolute expression
 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 // CHECK-NEXT:{{^}}                                                            ^
 
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK: error: expected absolute expression
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK-NEXT:{{^}}                                 ^
+
 //==============================================================================
 // expected a message name or an absolute expression
 
 s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 // CHECK: error: expected a message name or an absolute expression
 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 // CHECK-NEXT:{{^}}                  ^
 

 // expected a swizzle macro or an absolute expression
 
 ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 // CHECK: error: expected a swizzle macro or an absolute expression
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 // CHECK-NEXT:{{^}}                             ^
 
 //==============================================================================
+// expected a hwreg macro or an absolute expression
+
+s_setreg_b32 undef, s2
+// CHECK: error: expected a hwreg macro or an absolute expression
+// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
+// CHECK-NEXT:{{^}}             ^
+
+//==============================================================================
 // expected an 11-bit unsigned offset
 
 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 // CHECK: error: expected a 11-bit unsigned offset
 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 // CHECK-NEXT:{{^}}                                       ^
 
 //==============================================================================

 // CHECK-NEXT:{{^}}                ^
 
 v_mov_b32_sdwa v1, sext(u)
 // CHECK: error: expected an absolute expression
 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)
 // CHECK-NEXT:{{^}}                        ^
 
 //==============================================================================
-// expected a hwreg macro or an absolute expression
+// expected an opening square bracket
 
-s_setreg_b32 undef, s2
-// CHECK: error: expected a hwreg macro or an absolute expression
-// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
-// CHECK-NEXT:{{^}}             ^
+v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
+// CHECK: error: expected an opening square bracket
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
+// CHECK-NEXT:{{^}}                          ^
 
 //==============================================================================
 // expected an operation name or an absolute expression
 
 s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 // CHECK: error: expected an operation name or an absolute expression
 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 // CHECK-NEXT:{{^}}                          ^