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Differential D94156

AMDGPU/GlobalISel: Enable sret demotion
ClosedPublic

Authored by cdevadas on Jan 5 2021, 10:56 PM.

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Reviewers
arsenm

Diff Detail

Event Timeline

cdevadas created this revision.Jan 5 2021, 10:56 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptJan 5 2021, 10:56 PM
cdevadas requested review of this revision.Jan 5 2021, 10:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 5 2021, 10:56 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B84163: Diff 314802.Jan 5 2021, 11:31 PM
arsenm added a comment.Jan 6 2021, 8:49 AM

I think we're missing a test that needs sret inserted and also has additional arguments

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
45

You can get the context through the MachineFunction, so you can avoid this argument

cdevadas updated this revision to Diff 315107.Jan 7 2021, 5:08 AM

Added two more tests to address the review comment.

Harbormaster completed remote builds in B84319: Diff 315107.Jan 7 2021, 5:48 AM
arsenm accepted this revision.Jan 7 2021, 6:04 AM
This revision is now accepted and ready to land.Jan 7 2021, 6:04 AM
cdevadas closed this revision.Jan 7 2021, 9:30 PM

ae25a397e9de833ffbd5d8e3b480086404625cb7

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
4 lines
lib/
CodeGen/
GlobalISel/
6 lines
Target/
AMDGPU/
4 lines
34 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
69 lines
256 lines

Diff 315107

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Linespublic:
/// convention. \return True if the return value of \p MF can be returned /// convention. \return True if the return value of \p MF can be returned
/// without performing sret demotion. /// without performing sret demotion.
bool checkReturnTypeForCallConv(MachineFunction &MF) const; bool checkReturnTypeForCallConv(MachineFunction &MF) const;
/// This hook must be implemented to check whether the return values /// This hook must be implemented to check whether the return values
/// described by \p Outs can fit into the return registers. If false /// described by \p Outs can fit into the return registers. If false
/// is returned, an sret-demotion is performed. /// is returned, an sret-demotion is performed.
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs, bool IsVarArg, SmallVectorImpl<BaseArgInfo> &Outs,
LLVMContext &Context) const { bool IsVarArg) const {
return true; return true;
} }
/// This hook must be implemented to lower outgoing return values, described /// This hook must be implemented to lower outgoing return values, described
/// by \p Val, into the specified virtual registers \p VRegs. /// by \p Val, into the specified virtual registers \p VRegs.
/// This hook is used by GlobalISel. /// This hook is used by GlobalISel.
/// ///
/// \p FLI is required for sret demotion. /// \p FLI is required for sret demotion.
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines bool CanBeTailCalled = CB.isTailCall() &&
.getValueAsString() != "true"); .getValueAsString() != "true");
CallingConv::ID CallConv = CB.getCallingConv(); CallingConv::ID CallConv = CB.getCallingConv();
Type *RetTy = CB.getType(); Type *RetTy = CB.getType();
bool IsVarArg = CB.getFunctionType()->isVarArg(); bool IsVarArg = CB.getFunctionType()->isVarArg();
SmallVector<BaseArgInfo, 4> SplitArgs; SmallVector<BaseArgInfo, 4> SplitArgs;
getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL); getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
Info.CanLowerReturn = Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
canLowerReturn(MF, CallConv, SplitArgs, IsVarArg, RetTy->getContext());
if (!Info.CanLowerReturn) { if (!Info.CanLowerReturn) {
// Callee requires sret demotion. // Callee requires sret demotion.
insertSRetOutgoingArgument(MIRBuilder, CB, Info); insertSRetOutgoingArgument(MIRBuilder, CB, Info);
// The sret demotion isn't compatible with tail-calls, since the sret // The sret demotion isn't compatible with tail-calls, since the sret
// argument points into the caller's stack frame. // argument points into the caller's stack frame.
CanBeTailCalled = false; CanBeTailCalled = false;
▲ Show 20 Lines • Show All 479 Lines • ▼ Show 20 Lines
bool CallLowering::checkReturnTypeForCallConv(MachineFunction &MF) const { bool CallLowering::checkReturnTypeForCallConv(MachineFunction &MF) const {
const auto &F = MF.getFunction(); const auto &F = MF.getFunction();
Type *ReturnType = F.getReturnType(); Type *ReturnType = F.getReturnType();
CallingConv::ID CallConv = F.getCallingConv(); CallingConv::ID CallConv = F.getCallingConv();
SmallVector<BaseArgInfo, 4> SplitArgs; SmallVector<BaseArgInfo, 4> SplitArgs;
getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs, getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
MF.getDataLayout()); MF.getDataLayout());
return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg(), return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
ReturnType->getContext());
} }
bool CallLowering::analyzeArgInfo(CCState &CCState, bool CallLowering::analyzeArgInfo(CCState &CCState,
SmallVectorImpl<ArgInfo> &Args, SmallVectorImpl<ArgInfo> &Args,
CCAssignFn &AssignFnFixed, CCAssignFn &AssignFnFixed,
CCAssignFn &AssignFnVarArg) const { CCAssignFn &AssignFnVarArg) const {
for (unsigned i = 0, e = Args.size(); i < e; ++i) { for (unsigned i = 0, e = Args.size(); i < e; ++i) {
MVT VT = MVT::getVT(Args[i].Ty); MVT VT = MVT::getVT(Args[i].Ty);
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

Show All 34 Linesclass AMDGPUCallLowering final : public CallLowering {
void splitToValueTypes(MachineIRBuilder &B, void splitToValueTypes(MachineIRBuilder &B,
const ArgInfo &OrigArgInfo, const ArgInfo &OrigArgInfo,
SmallVectorImpl<ArgInfo> &SplitArgs, SmallVectorImpl<ArgInfo> &SplitArgs,
const DataLayout &DL, const DataLayout &DL,
CallingConv::ID CallConv, CallingConv::ID CallConv,
bool IsOutgoing, bool IsOutgoing,
SplitArgTy SplitArg) const; SplitArgTy SplitArg) const;
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,
bool IsVarArg) const override;
arsenmUnsubmitted
Not Done
ReplyInline Actions

You can get the context through the MachineFunction, so you can avoid this argument

arsenm: You can get the context through the MachineFunction, so you can avoid this argument
bool lowerReturnVal(MachineIRBuilder &B, const Value *Val, bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const; ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
public: public:
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI); AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
bool lowerReturn(MachineIRBuilder &B, const Value *Val, bool lowerReturn(MachineIRBuilder &B, const Value *Val,
ArrayRef<Register> VRegs, ArrayRef<Register> VRegs,
Show All 22 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show All 18 Lines
#include "AMDGPUSubtarget.h" #include "AMDGPUSubtarget.h"
#include "AMDGPUTargetMachine.h" #include "AMDGPUTargetMachine.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIISelLowering.h" #include "SIISelLowering.h"
#include "SIMachineFunctionInfo.h" #include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h" #include "SIRegisterInfo.h"
#include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/LowLevelTypeImpl.h" #include "llvm/Support/LowLevelTypeImpl.h"
#define DEBUG_TYPE "amdgpu-call-lowering" #define DEBUG_TYPE "amdgpu-call-lowering"
using namespace llvm; using namespace llvm;
▲ Show 20 Lines • Show All 373 Lines • ▼ Show 20 Linesstatic void unpackRegsToOrigType(MachineIRBuilder &B,
for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize; for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize;
Size += DstSize) { Size += DstSize) {
UnmergeResults.push_back(MRI.createGenericVirtualRegister(DstTy)); UnmergeResults.push_back(MRI.createGenericVirtualRegister(DstTy));
} }
B.buildUnmerge(UnmergeResults, UnmergeSrc); B.buildUnmerge(UnmergeResults, UnmergeSrc);
} }
bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,
bool IsVarArg) const {
// For shaders. Vector types should be explicitly handled by CC.
if (AMDGPU::isEntryFunctionCC(CallConv))
return true;
SmallVector<CCValAssign, 16> ArgLocs;
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
MF.getFunction().getContext());
return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg));
}
/// Lower the return value for the already existing \p Ret. This assumes that /// Lower the return value for the already existing \p Ret. This assumes that
/// \p B's insertion point is correct. /// \p B's insertion point is correct.
bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B, bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
const Value *Val, ArrayRef<Register> VRegs, const Value *Val, ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const { MachineInstrBuilder &Ret) const {
if (!Val) if (!Val)
return true; return true;
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesbool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,
auto Ret = B.buildInstrNoInsert(ReturnOpc); auto Ret = B.buildInstrNoInsert(ReturnOpc);
Register ReturnAddrVReg; Register ReturnAddrVReg;
if (ReturnOpc == AMDGPU::S_SETPC_B64_return) { if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass); ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
Ret.addUse(ReturnAddrVReg); Ret.addUse(ReturnAddrVReg);
} }
if (!lowerReturnVal(B, Val, VRegs, Ret)) if (!FLI.CanLowerReturn)
insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister);
else if (!lowerReturnVal(B, Val, VRegs, Ret))
return false; return false;
if (ReturnOpc == AMDGPU::S_SETPC_B64_return) { if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
const SIRegisterInfo *TRI = ST.getRegisterInfo(); const SIRegisterInfo *TRI = ST.getRegisterInfo();
Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF), Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
&AMDGPU::SGPR_64RegClass); &AMDGPU::SGPR_64RegClass);
B.buildCopy(ReturnAddrVReg, LiveInReturn); B.buildCopy(ReturnAddrVReg, LiveInReturn);
} }
▲ Show 20 Lines • Show All 317 Lines • ▼ Show 20 Linesbool AMDGPUCallLowering::lowerFormalArguments(
} }
if (Info->hasImplicitBufferPtr()) { if (Info->hasImplicitBufferPtr()) {
Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI); Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass); MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(ImplicitBufferPtrReg); CCInfo.AllocateReg(ImplicitBufferPtrReg);
} }
SmallVector<ArgInfo, 32> SplitArgs; SmallVector<ArgInfo, 32> SplitArgs;
unsigned Idx = 0; unsigned Idx = 0;
unsigned PSInputNum = 0; unsigned PSInputNum = 0;
// Insert the hidden sret parameter if the return value won't fit in the
// return registers.
if (!FLI.CanLowerReturn)
insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
for (auto &Arg : F.args()) { for (auto &Arg : F.args()) {
if (DL.getTypeStoreSize(Arg.getType()) == 0) if (DL.getTypeStoreSize(Arg.getType()) == 0)
continue; continue;
const bool InReg = Arg.hasAttribute(Attribute::InReg); const bool InReg = Arg.hasAttribute(Attribute::InReg);
// SGPR arguments to functions not implemented. // SGPR arguments to functions not implemented.
if (!IsGraphics && InReg) if (!IsGraphics && InReg)
▲ Show 20 Lines • Show All 433 Lines • ▼ Show 20 Linesbool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// Now we can add the actual call instruction to the correct position. // Now we can add the actual call instruction to the correct position.
MIRBuilder.insertInstr(MIB); MIRBuilder.insertInstr(MIB);
// Insert this now to give us an anchor point for managing the insert point. // Insert this now to give us an anchor point for managing the insert point.
MachineInstrBuilder CallSeqEnd = MachineInstrBuilder CallSeqEnd =
MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN); MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN);
SmallVector<ArgInfo, 8> InArgs; SmallVector<ArgInfo, 8> InArgs;
if (!Info.OrigRet.Ty->isVoidTy()) { if (!Info.CanLowerReturn) {
insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
Info.DemoteRegister, Info.DemoteStackIndex);
} else if (!Info.OrigRet.Ty->isVoidTy()) {
splitToValueTypes( splitToValueTypes(
MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv, false, MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv, false,
[&](ArrayRef<Register> Regs, Register DstReg, [&](ArrayRef<Register> Regs, Register DstReg,
LLT LLTy, LLT PartLLT, int VTSplitIdx) { LLT LLTy, LLT PartLLT, int VTSplitIdx) {
assert(DstReg == Info.OrigRet.Regs[VTSplitIdx]); assert(DstReg == Info.OrigRet.Regs[VTSplitIdx]);
packSplitRegsToOrigType(MIRBuilder, Info.OrigRet.Regs[VTSplitIdx], packSplitRegsToOrigType(MIRBuilder, Info.OrigRet.Regs[VTSplitIdx],
Regs, LLTy, PartLLT); Regs, LLTy, PartLLT);
}); });
} }
// Make sure the raw argument copies are inserted before the marshalling to // Make sure the raw argument copies are inserted before the marshalling to
// the original types. // the original types.
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd);
// Finally we can copy the returned value back into its virtual-register. In // Finally we can copy the returned value back into its virtual-register. In
// symmetry with the arguments, the physical register must be an // symmetry with the arguments, the physical register must be an
// implicit-define of the call instruction. // implicit-define of the call instruction.
if (!Info.OrigRet.Ty->isVoidTy()) { if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv,
Info.IsVarArg); Info.IsVarArg);
CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn); CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
if (!handleAssignments(MIRBuilder, InArgs, Handler)) if (!handleAssignments(MIRBuilder, InArgs, Handler))
return false; return false;
} }
uint64_t CalleePopBytes = NumBytes; uint64_t CalleePopBytes = NumBytes;
CallSeqEnd.addImm(0) CallSeqEnd.addImm(0)
.addImm(CalleePopBytes); .addImm(CalleePopBytes);
// Restore the insert point to after the call sequence. // Restore the insert point to after the call sequence.
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), OrigInsertPt); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), OrigInsertPt);
return true; return true;
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

Show First 20 Lines • Show All 1,166 Lines • ▼ Show 20 Lines
} }
; FIXME: Should be able to fold offsets in all of these pre-gfx9. Call ; FIXME: Should be able to fold offsets in all of these pre-gfx9. Call
; lowering introduces an extra CopyToReg/CopyFromReg obscuring the ; lowering introduces an extra CopyToReg/CopyFromReg obscuring the
; AssertZext inserted. Not using it introduces the spills. ; AssertZext inserted. Not using it introduces the spills.
define <33 x i32> @v33i32_func_void() #0 { define <33 x i32> @v33i32_func_void() #0 {
; CHECK-LABEL: name: v33i32_func_void ; CHECK-LABEL: name: v33i32_func_void
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `<33 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `<33 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[LOAD]](p1) :: (load 132 from %ir.ptr, align 256, addrspace 1) ; CHECK: [[LOAD1:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[LOAD]](p1) :: (load 132 from %ir.ptr, align 256, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<33 x s32>) ; CHECK: G_STORE [[LOAD1]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr = load volatile <33 x i32> addrspace(1)*, <33 x i32> addrspace(1)* addrspace(4)* undef %ptr = load volatile <33 x i32> addrspace(1)*, <33 x i32> addrspace(1)* addrspace(4)* undef
%val = load <33 x i32>, <33 x i32> addrspace(1)* %ptr %val = load <33 x i32>, <33 x i32> addrspace(1)* %ptr
ret <33 x i32> %val ret <33 x i32> %val
} }
define <33 x i32> @v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 {
; CHECK-LABEL: name: v33i32_func_v33i32_i32
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY3]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[MUL]](s64)
; CHECK: [[COPY5:%[0-9]+]]:_(p1) = COPY [[PTR_ADD]](p1)
; CHECK: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[COPY5]](p1) :: (load 132 from %ir.gep, align 256, addrspace 1)
; CHECK: G_STORE [[LOAD]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5)
; CHECK: [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
; CHECK: S_SETPC_B64_return [[COPY6]]
%gep = getelementptr inbounds <33 x i32>, <33 x i32> addrspace(1)* %p, i32 %idx
%val = load <33 x i32>, <33 x i32> addrspace(1)* %gep
ret <33 x i32> %val
}
define { <32 x i32>, i32 } @struct_v32i32_i32_func_void() #0 { define { <32 x i32>, i32 } @struct_v32i32_i32_func_void() #0 {
; CHECK-LABEL: name: struct_v32i32_i32_func_void ; CHECK-LABEL: name: struct_v32i32_i32_func_void
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr, addrspace 1) ; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr + 128, align 128, addrspace 1) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr + 128, align 128, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>) ; CHECK: G_STORE [[LOAD1]](<32 x s32>), [[COPY]](p5) :: (store 128, addrspace 5)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32)
; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD1]](p5) :: (store 4, align 128, addrspace 5)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr = load volatile { <32 x i32>, i32 } addrspace(1)*, { <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef %ptr = load volatile { <32 x i32>, i32 } addrspace(1)*, { <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef
%val = load { <32 x i32>, i32 }, { <32 x i32>, i32 } addrspace(1)* %ptr %val = load { <32 x i32>, i32 }, { <32 x i32>, i32 } addrspace(1)* %ptr
ret { <32 x i32>, i32 }%val ret { <32 x i32>, i32 }%val
} }
define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 { define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 {
; CHECK-LABEL: name: struct_i32_v32i32_func_void ; CHECK-LABEL: name: struct_i32_v32i32_func_void
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ i32, <32 x i32> } addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ i32, <32 x i32> } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p1) :: (load 4 from %ir.ptr, align 128, addrspace 1) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p1) :: (load 4 from %ir.ptr, align 128, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 128 from %ir.ptr + 128, addrspace 1) ; CHECK: [[LOAD2:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 128 from %ir.ptr + 128, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD2]](<32 x s32>) ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p5) :: (store 4, align 128, addrspace 5)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32)
; CHECK: G_STORE [[LOAD2]](<32 x s32>), [[PTR_ADD1]](p5) :: (store 128, addrspace 5)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr = load volatile { i32, <32 x i32> } addrspace(1)*, { i32, <32 x i32> } addrspace(1)* addrspace(4)* undef %ptr = load volatile { i32, <32 x i32> } addrspace(1)*, { i32, <32 x i32> } addrspace(1)* addrspace(4)* undef
%val = load { i32, <32 x i32> }, { i32, <32 x i32> } addrspace(1)* %ptr %val = load { i32, <32 x i32> }, { i32, <32 x i32> } addrspace(1)* %ptr
ret { i32, <32 x i32> }%val ret { i32, <32 x i32> }%val
} }
; Make sure the last struct component is returned in v3, not v4. ; Make sure the last struct component is returned in v3, not v4.
define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 { define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-LABEL: name: v3i32_struct_func_void_wasted_reg ; CHECK-LABEL: name: v3i32_struct_func_void_wasted_reg
▲ Show 20 Lines • Show All 248 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

Show All 40 Lines
declare <2 x i32> @external_v2i32_func_void() #0 declare <2 x i32> @external_v2i32_func_void() #0
declare <3 x i32> @external_v3i32_func_void() #0 declare <3 x i32> @external_v3i32_func_void() #0
declare <4 x i32> @external_v4i32_func_void() #0 declare <4 x i32> @external_v4i32_func_void() #0
declare <5 x i32> @external_v5i32_func_void() #0 declare <5 x i32> @external_v5i32_func_void() #0
declare <8 x i32> @external_v8i32_func_void() #0 declare <8 x i32> @external_v8i32_func_void() #0
declare <16 x i32> @external_v16i32_func_void() #0 declare <16 x i32> @external_v16i32_func_void() #0
declare <32 x i32> @external_v32i32_func_void() #0 declare <32 x i32> @external_v32i32_func_void() #0
declare <33 x i32> @external_v33i32_func_void() #0
declare <33 x i32> @external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)*, i32) #0
declare { <32 x i32>, i32 } @external_v32i32_i32_func_void() #0 declare { <32 x i32>, i32 } @external_v32i32_i32_func_void() #0
declare { i32, <32 x i32> } @external_i32_v32i32_func_void() #0
declare { i32, i64 } @external_i32_i64_func_void() #0 declare { i32, i64 } @external_i32_i64_func_void() #0
declare [2 x i32] @external_a2i32_func_void() #0 declare [2 x i32] @external_a2i32_func_void() #0
declare [5 x i8] @external_a5i8_func_void() #0 declare [5 x i8] @external_a5i8_func_void() #0
; return value and argument ; return value and argument
declare hidden i32 @external_i32_func_i32(i32) #0 declare hidden i32 @external_i32_func_i32(i32) #0
▲ Show 20 Lines • Show All 2,688 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {
store volatile i8 %val.0, i8 addrspace(1)* undef store volatile i8 %val.0, i8 addrspace(1)* undef
store volatile i8 %val.1, i8 addrspace(1)* undef store volatile i8 %val.1, i8 addrspace(1)* undef
store volatile i8 %val.2, i8 addrspace(1)* undef store volatile i8 %val.2, i8 addrspace(1)* undef
store volatile i8 %val.3, i8 addrspace(1)* undef store volatile i8 %val.3, i8 addrspace(1)* undef
store volatile i8 %val.4, i8 addrspace(1)* undef store volatile i8 %val.4, i8 addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v32i32_i32_func_void
; GCN: bb.1 (%ir-block.0):
; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_i32_func_void
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN: $sgpr12 = COPY [[COPY15]](s32)
; GCN: $sgpr13 = COPY [[COPY16]](s32)
; GCN: $sgpr14 = COPY [[COPY17]](s32)
; GCN: $vgpr31 = COPY [[OR1]](s32)
; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 128 from %stack.0, addrspace 5)
; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GCN: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32)
; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load 4 from %stack.0, align 128, addrspace 5)
; GCN: G_STORE [[LOAD]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN: G_STORE [[LOAD1]](s32), [[COPY10]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: S_ENDPGM 0
%val = call { <32 x i32>, i32 } @external_v32i32_i32_func_void()
%val0 = extractvalue { <32 x i32>, i32 } %val, 0
%val1 = extractvalue { <32 x i32>, i32 } %val, 1
store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef, align 8
store volatile i32 %val1, i32 addrspace(1)* undef
ret void
}
define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_i32_v32i32_func_void
; GCN: bb.1 (%ir-block.0):
; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_v32i32_func_void
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN: $sgpr12 = COPY [[COPY15]](s32)
; GCN: $sgpr13 = COPY [[COPY16]](s32)
; GCN: $sgpr14 = COPY [[COPY17]](s32)
; GCN: $vgpr31 = COPY [[OR1]](s32)
; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_v32i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (load 4 from %stack.0, align 128, addrspace 5)
; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GCN: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32)
; GCN: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD1]](p5) :: (load 128 from %stack.0, addrspace 5)
; GCN: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[LOAD1]](<32 x s32>), [[COPY10]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN: S_ENDPGM 0
%val = call { i32, <32 x i32> } @external_i32_v32i32_func_void()
%val0 = extractvalue { i32, <32 x i32> } %val, 0
%val1 = extractvalue { i32, <32 x i32> } %val, 1
store volatile i32 %val0, i32 addrspace(1)* undef
store volatile <32 x i32> %val1, <32 x i32> addrspace(1)* undef, align 8
ret void
}
define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v33i32_func_void
; GCN: bb.1 (%ir-block.0):
; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_void
; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN: $sgpr12 = COPY [[COPY14]](s32)
; GCN: $sgpr13 = COPY [[COPY15]](s32)
; GCN: $sgpr14 = COPY [[COPY16]](s32)
; GCN: $vgpr31 = COPY [[OR1]](s32)
; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 132 from %stack.0, align 256, addrspace 5)
; GCN: G_STORE [[LOAD]](<33 x s32>), [[DEF]](p1) :: (volatile store 132 into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN: S_ENDPGM 0
%val = call <33 x i32> @external_v33i32_func_void()
store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8
ret void
}
define amdgpu_kernel void @test_call_external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 {
; GCN-LABEL: name: test_call_external_v33i32_func_v33i32_i32
; GCN: bb.1 (%ir-block.0):
; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.p.kernarg.offset.cast, align 16, addrspace 4)
; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64)
; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4 from %ir.idx.kernarg.offset.cast, align 8, addrspace 4)
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_v33i32_i32
; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN: $vgpr1 = COPY [[UV]](s32)
; GCN: $vgpr2 = COPY [[UV1]](s32)
; GCN: $vgpr3 = COPY [[LOAD1]](s32)
; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; GCN: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN: $sgpr12 = COPY [[COPY14]](s32)
; GCN: $sgpr13 = COPY [[COPY15]](s32)
; GCN: $sgpr14 = COPY [[COPY16]](s32)
; GCN: $vgpr31 = COPY [[OR1]](s32)
; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_v33i32_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN: [[LOAD2:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 132 from %stack.0, align 256, addrspace 5)
; GCN: G_STORE [[LOAD2]](<33 x s32>), [[DEF]](p1) :: (volatile store 132 into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN: S_ENDPGM 0
%val = call <33 x i32> @external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx)
store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind noinline } attributes #2 = { nounwind noinline }