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Differential D94114

[NFC] Removed unused prefixes in CodeGen/AMDGPU
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Authored by mtrofin on Jan 5 2021, 1:07 PM.

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arsenm
Commits
rGbec987ea6727: [NFC] Removed unused prefixes in CodeGen/AMDGPU
Summary

This is part of the pertinent tests, more to follow in subsequent
patches.

Diff Detail

Event Timeline

mtrofin created this revision.Jan 5 2021, 1:07 PM
Herald added subscribers: kerbowa, t-tye, tpr and 5 others. · View Herald TranscriptJan 5 2021, 1:08 PM
mtrofin requested review of this revision.Jan 5 2021, 1:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 5 2021, 1:08 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
arsenm accepted this revision.Jan 5 2021, 1:16 PM
This revision is now accepted and ready to land.Jan 5 2021, 1:16 PM
Harbormaster completed remote builds in B84105: Diff 314701.Jan 5 2021, 1:46 PM
This revision was landed with ongoing or failed builds.Jan 5 2021, 2:11 PM
Closed by commit rGbec987ea6727: [NFC] Removed unused prefixes in CodeGen/AMDGPU (authored by mtrofin). · Explain Why
This revision was automatically updated to reflect the committed changes.
mtrofin added a commit: rGbec987ea6727: [NFC] Removed unused prefixes in CodeGen/AMDGPU.

Revision Contents

Diff 314719

llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll

; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s ; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s ; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s ; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s ; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s ; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s ; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; Make sure we don't overwrite workitem information with private memory ; Make sure we don't overwrite workitem information with private memory
; GCN-LABEL: {{^}}work_item_info: ; GCN-LABEL: {{^}}work_item_info:
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
; Legacy intrinsics that just read implicit parameters ; Legacy intrinsics that just read implicit parameters
; FUNC-LABEL: {{^}}ngroups_x: ; FUNC-LABEL: {{^}}ngroups_x:
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
; GCN-NOHSA: buffer_store_dword [[VVAL]] ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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llvm/test/CodeGen/AMDGPU/amdpal-cs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; GCN-LABEL: {{^}}cs_amdpal: ; GCN-LABEL: {{^}}cs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .cs: ; GCN-NEXT: .cs:
; GCN-NEXT: .entry_point: cs_amdpal ; GCN-NEXT: .entry_point: cs_amdpal
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llvm/test/CodeGen/AMDGPU/amdpal-es.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}es_amdpal: ; GCN-LABEL: {{^}}es_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .es: ; GCN-NEXT: .es:
; GCN-NEXT: .entry_point: es_amdpal ; GCN-NEXT: .entry_point: es_amdpal
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llvm/test/CodeGen/AMDGPU/amdpal-gs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; GCN-LABEL: {{^}}gs_amdpal: ; GCN-LABEL: {{^}}gs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .gs: ; GCN-NEXT: .gs:
; GCN-NEXT: .entry_point: gs_amdpal ; GCN-NEXT: .entry_point: gs_amdpal
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llvm/test/CodeGen/AMDGPU/amdpal-hs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; GCN-LABEL: {{^}}hs_amdpal: ; GCN-LABEL: {{^}}hs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .hs: ; GCN-NEXT: .hs:
; GCN-NEXT: .entry_point: hs_amdpal ; GCN-NEXT: .entry_point: hs_amdpal
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llvm/test/CodeGen/AMDGPU/amdpal-ls.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}ls_amdpal: ; GCN-LABEL: {{^}}ls_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .ls: ; GCN-NEXT: .ls:
; GCN-NEXT: .entry_point: ls_amdpal ; GCN-NEXT: .entry_point: ls_amdpal
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; GCN-LABEL: {{^}}cs_amdpal: ; GCN-LABEL: {{^}}cs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2e12 (COMPUTE_PGM_RSRC1) ; GCN: 0x2e12 (COMPUTE_PGM_RSRC1)
define amdgpu_cs half @cs_amdpal(half %arg0) { define amdgpu_cs half @cs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}} ; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}}
; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f02c0{{$}} ; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f02c0{{$}}
; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}} ; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}}
define amdgpu_cs half @cs_amdpal(half %arg0) { define amdgpu_cs half @cs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}} ; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}}
; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c02c0{{$}} ; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c02c0{{$}}
; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}} ; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}}
define amdgpu_cs half @cs_amdpal(half %arg0) #0 { define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}} ; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}}
; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf02c0{{$}} ; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf02c0{{$}}
; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}} ; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}}
define amdgpu_cs half @cs_amdpal(half %arg0) #0 { define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
; GCN-LABEL: {{^}}es_amdpal: ; GCN-LABEL: {{^}}es_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2cca (SPI_SHADER_PGM_RSRC1_ES) ; GCN: 0x2cca (SPI_SHADER_PGM_RSRC1_ES)
define amdgpu_es half @es_amdpal(half %arg0) { define amdgpu_es half @es_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
; GCN-LABEL: {{^}}gs_amdpal: ; GCN-LABEL: {{^}}gs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) ; GCN: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS)
define amdgpu_gs half @gs_amdpal(half %arg0) { define amdgpu_gs half @gs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
; GCN-LABEL: {{^}}hs_amdpal: ; GCN-LABEL: {{^}}hs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) ; GCN: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS)
define amdgpu_hs half @hs_amdpal(half %arg0) { define amdgpu_hs half @hs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} ; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}}
; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0{{$}} ; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0{{$}}
; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} ; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}}
define amdgpu_cs half @cs_amdpal(half %arg0) #0 { define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
; GCN-LABEL: {{^}}ls_amdpal: ; GCN-LABEL: {{^}}ls_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) ; GCN: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS)
define amdgpu_ls half @ls_amdpal(half %arg0) { define amdgpu_ls half @ls_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal
; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and ; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and
; it has a value starting 0x42 as it is set to 0x42000000 in the metadata ; it has a value starting 0x42 as it is set to 0x42000000 in the metadata
; below. Also check that .internal_pipeline_hash is propagated. ; below. Also check that .internal_pipeline_hash is propagated.
; GCN-LABEL: {{^}}ps_amdpal: ; GCN-LABEL: {{^}}ps_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: .internal_pipeline_hash: ; GCN: .internal_pipeline_hash:
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; This pixel shader does not use the result of its interpolation, so it would ; This pixel shader does not use the result of its interpolation, so it would
; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests ; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
; the workaround that ensures that an interpolation mode is also set in PSEnable. ; the workaround that ensures that an interpolation mode is also set in PSEnable.
; GCN-LABEL: {{^}}amdpal_psenable: ; GCN-LABEL: {{^}}amdpal_psenable:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2 ; GCN: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2
; GCN: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2 ; GCN: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2
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llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
; GCN-LABEL: {{^}}vs_amdpal: ; GCN-LABEL: {{^}}vs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS) ; GCN: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS)
define amdgpu_vs half @vs_amdpal(half %arg0) { define amdgpu_vs half @vs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
; Force MsgPack format metadata ; Force MsgPack format metadata
!amdgpu.pal.metadata.msgpack = !{!0} !amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!""} !0 = !{!""}

llvm/test/CodeGen/AMDGPU/amdpal-ps.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal
; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and ; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and
; it has a value starting 0x42 as it is set to 0x42000000 in the metadata ; it has a value starting 0x42 as it is set to 0x42000000 in the metadata
; below. Also check that key 0x10000000 value 0x12345678 is propagated. ; below. Also check that key 0x10000000 value 0x12345678 is propagated.
; GCN-LABEL: {{^}}ps_amdpal: ; GCN-LABEL: {{^}}ps_amdpal:
; GCN: .amd_amdgpu_pal_metadata{{.*0x2c0a,[^,]*,0x2c0b,0x42.*,0x10000000,0x12345678}} ; GCN: .amd_amdgpu_pal_metadata{{.*0x2c0a,[^,]*,0x2c0b,0x42.*,0x10000000,0x12345678}}
define amdgpu_ps half @ps_amdpal(half %arg0) { define amdgpu_ps half @ps_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0 %add = fadd half %arg0, 1.0
ret half %add ret half %add
} }
!amdgpu.pal.metadata = !{!0} !amdgpu.pal.metadata = !{!0}
!0 = !{i32 11275, i32 1107296256, i32 268435456, i32 305419896} !0 = !{i32 11275, i32 1107296256, i32 268435456, i32 305419896}

llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; This pixel shader does not use the result of its interpolation, so it would ; This pixel shader does not use the result of its interpolation, so it would
; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests ; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
; the workaround that ensures that an interpolation mode is also set in PSEnable. ; the workaround that ensures that an interpolation mode is also set in PSEnable.
; GCN-LABEL: {{^}}amdpal_psenable: ; GCN-LABEL: {{^}}amdpal_psenable:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
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llvm/test/CodeGen/AMDGPU/amdpal-vs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s
; GCN-LABEL: {{^}}vs_amdpal: ; GCN-LABEL: {{^}}vs_amdpal:
; GCN: .amdgpu_pal_metadata ; GCN: .amdgpu_pal_metadata
; GCN-NEXT: --- ; GCN-NEXT: ---
; GCN-NEXT: amdpal.pipelines: ; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages: ; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .vs: ; GCN-NEXT: .vs:
; GCN-NEXT: .entry_point: vs_amdpal ; GCN-NEXT: .entry_point: vs_amdpal
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llvm/test/CodeGen/AMDGPU/andorn2.ll

; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s ; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s ; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}scalar_andn2_i32_one_use ; GCN-LABEL: {{^}}scalar_andn2_i32_one_use
; GCN: s_andn2_b32 ; GCN: s_andn2_b32
define amdgpu_kernel void @scalar_andn2_i32_one_use( define amdgpu_kernel void @scalar_andn2_i32_one_use(
i32 addrspace(1)* %r0, i32 %a, i32 %b) { i32 addrspace(1)* %r0, i32 %a, i32 %b) {
entry: entry:
%nb = xor i32 %b, -1 %nb = xor i32 %b, -1
%r0.val = and i32 %a, %nb %r0.val = and i32 %a, %nb
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llvm/test/CodeGen/AMDGPU/anyext.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,GFX89 %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX89 %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
; GCN-LABEL: {{^}}anyext_i1_i32: ; GCN-LABEL: {{^}}anyext_i1_i32:
; GCN: v_cndmask_b32_e64 ; GCN: v_cndmask_b32_e64
define amdgpu_kernel void @anyext_i1_i32(i32 addrspace(1)* %out, i32 %cond) #0 { define amdgpu_kernel void @anyext_i1_i32(i32 addrspace(1)* %out, i32 %cond) #0 {
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llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI,SICI,SICIVI,GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI,SICI,SICIVI,GCN %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SICI,CIVI,SICIVI,GCN %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SICI,CIVI,SICIVI,GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,SICIVI,GFX89,GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,SICIVI,GFX89,GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX89,GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX89,GCN %s
; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset: ; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 ; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c ; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=ALL %s
; FIXME: Vectorization can increase required SGPR count beyond limit. ; FIXME: Vectorization can increase required SGPR count beyond limit.
; ALL-LABEL: {{^}}max_10_sgprs: ; ALL-LABEL: {{^}}max_10_sgprs:
; ALL: SGPRBlocks: 1 ; ALL: SGPRBlocks: 1
; ALL: NumSGPRsForWavesPerEU: 10 ; ALL: NumSGPRsForWavesPerEU: 10
define amdgpu_kernel void @max_10_sgprs() #0 { define amdgpu_kernel void @max_10_sgprs() #0 {
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