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[PowerPC] Fix issue where vsrq is given incorrect shift vector
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Authored by stefanp on Jan 5 2021, 12:55 PM.

Details

Summary

The new Power10 instruction vsrq was being given the wrong shift vector.
The original code assumed that the shift would be found in bits 121 to 127.
This is not correct. The shift is found in bits 57 to 63.
This can be fixed by swaping the first and second double words.

Diff Detail

Event Timeline

stefanp created this revision.Jan 5 2021, 12:55 PM
stefanp requested review of this revision.Jan 5 2021, 12:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 5 2021, 12:55 PM
stefanp added a reviewer: Restricted Project.Jan 5 2021, 12:58 PM
stefanp updated this revision to Diff 314697.Jan 5 2021, 1:00 PM

Forgot to delete the old lines in the TD file.

nemanjai accepted this revision.Jan 5 2021, 2:41 PM

LGTM.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td
2561

I know that the issue is not new with P10, but I think it would be good to mention here something like:

// FIXME: The swap is overkill when the shift amount is a constant.
// We should just fix the constant in the DAG.

And then of course, not forget to follow this patch up with one that does that :).

This revision is now accepted and ready to land.Jan 5 2021, 2:41 PM
stefanp updated this revision to Diff 314842.Jan 6 2021, 3:28 AM

Added the todo comment in the TD file.

This revision was landed with ongoing or failed builds.Jan 6 2021, 3:56 AM
This revision was automatically updated to reflect the committed changes.