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Differential D92868

[AArch64][GlobalISel] Fold G_SELECT cc, %t, (G_ADD %x, 1) -> CSINC %t, %x, cc
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Authored by paquette on Dec 8 2020, 10:26 AM.

Details

Reviewers
aemerson
Commits
rG5b5d3fa9d9cf: [AArch64][GlobalISel] Fold G_SELECT cc, %t, (G_ADD %x, 1) -> CSINC %t, %x, cc
Summary

This implements

G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc

Godbolt example: https://godbolt.org/z/eoPqKq

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
15 lines
test/
CodeGen/
AArch64/
GlobalISel/
58 lines

Diff 310288

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 1,060 Lines • ▼ Show 20 Lines auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI](Register &Reg,
if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) { if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) {
Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr; Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
Reg = MatchReg; Reg = MatchReg;
if (Invert) if (Invert)
CC = AArch64CC::getInvertedCondCode(CC); CC = AArch64CC::getInvertedCondCode(CC);
return true; return true;
} }
// Attempt to fold:
//
// %add = G_ADD %x, 1
// %select = G_SELECT cc, %reg, %add
//
// Into:
// %select = CSINC %reg, %x, cc
if (mi_match(Reg, MRI, m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)))) {
Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
Reg = MatchReg;
if (Invert)
CC = AArch64CC::getInvertedCondCode(CC);
return true;
}
return false; return false;
}; };
// Helper lambda which tries to use CSINC/CSINV for the instruction when its // Helper lambda which tries to use CSINC/CSINV for the instruction when its
// true/false values are constants. // true/false values are constants.
// FIXME: All of these patterns already exist in tablegen. We should be // FIXME: All of these patterns already exist in tablegen. We should be
// able to import these. // able to import these.
auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI, auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI,
▲ Show 20 Lines • Show All 4,871 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir

Show First 20 Lines • Show All 586 Lines • ▼ Show 20 Lines bb.0:
%cond:gpr(s1) = G_TRUNC %reg0(s64) %cond:gpr(s1) = G_TRUNC %reg0(s64)
%t:gpr(s64) = COPY $x2 %t:gpr(s64) = COPY $x2
%negative_one:gpr(s32) = G_CONSTANT i32 -1 %negative_one:gpr(s32) = G_CONSTANT i32 -1
%zext:gpr(s64) = G_ZEXT %negative_one(s32) %zext:gpr(s64) = G_ZEXT %negative_one(s32)
%xor:gpr(s64) = G_XOR %reg1(s64), %zext %xor:gpr(s64) = G_XOR %reg1(s64), %zext
%select:gpr(s64) = G_SELECT %cond(s1), %t, %xor %select:gpr(s64) = G_SELECT %cond(s1), %t, %xor
$x0 = COPY %select(s64) $x0 = COPY %select(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
...
---
name: csinc_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
; CHECK-LABEL: name: csinc_s32
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %reg0:gpr32 = COPY $w0
; CHECK: %reg1:gpr32 = COPY $w1
; CHECK: %t:gpr32 = COPY $w2
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
; CHECK: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
; CHECK: $w0 = COPY %select
; CHECK: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%t:gpr(s32) = COPY $w2
%one:gpr(s32) = G_CONSTANT i32 1
%add:gpr(s32) = G_ADD %reg1(s32), %one
%select:gpr(s32) = G_SELECT %cond(s1), %t, %add
$w0 = COPY %select(s32)
RET_ReallyLR implicit $w0
...
---
name: csinc_s32_inverted_cc
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc
; CHECK-LABEL: name: csinc_s32_inverted_cc
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %reg0:gpr32 = COPY $w0
; CHECK: %reg1:gpr32 = COPY $w1
; CHECK: %f:gpr32 = COPY $w2
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
; CHECK: %select:gpr32 = CSINCWr %reg1, %f, 0, implicit $nzcv
; CHECK: $w0 = COPY %select
; CHECK: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%f:gpr(s32) = COPY $w2
%one:gpr(s32) = G_CONSTANT i32 1
%add:gpr(s32) = G_ADD %reg1(s32), %one
%select:gpr(s32) = G_SELECT %cond(s1), %add, %f
$w0 = COPY %select(s32)
RET_ReallyLR implicit $w0