[PowerPC] Set SubRegIndex offset for sub_vsx1/sub_pair1

[jsji]

Summary

We defined SubRegIndex for 256/512 regs, but we did not set the offset for higher part,
so the offset of lower and higher part are the same.
This may cause problem in access ranges of SubReg, it is great that this haven't affected any testcases,
but I think we should fix it to avoid hidden bugs in the future.

You can see the changes in PPCGenRegisterInfo.inc.

@@ -637,25 +637,25 @@
extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {

{ 65535, 65535 },
{ 0, 32 },   // sub_32
{ 0, 64 },   // sub_64
{ 2, 1 },    // sub_eq
{ 1, 1 },    // sub_gt
{ 0, 1 },    // sub_lt
{ 0, 256 },  // sub_pair0

• { 0, 256 }, // sub_pair1

+ { 256, 256 }, // sub_pair1

{ 3, 1 },    // sub_un
{ 0, 128 },  // sub_vsx0

• { 0, 128 }, // sub_vsx1
• { 0, 64 }, // sub_vsx1_then_sub_64
• { 0, 64 }, // sub_pair1_then_sub_64
• { 0, 128 }, // sub_pair1_then_sub_vsx0
• { 0, 128 }, // sub_pair1_then_sub_vsx1
• { 0, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64

+ { 128, 128 }, sub_vsx1
+ { 128, 64 }, sub_vsx1_then_sub_64
+ { 256, 64 }, sub_pair1_then_sub_64
+ { 256, 128 }, sub_pair1_then_sub_vsx0
+ { 384, 128 }, sub_pair1_then_sub_vsx1
+ { 384, 64 }, sub_pair1_then_sub_vsx1_then_sub_64
};

[bsaleil]

Good catch, thanks for fixing that.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 let Namespace = "PPC" in {
 def sub_lt : SubRegIndex<1>;
 def sub_gt : SubRegIndex<1, 1>;
 def sub_eq : SubRegIndex<1, 2>;
 def sub_un : SubRegIndex<1, 3>;
 def sub_32 : SubRegIndex<32>;
 def sub_64 : SubRegIndex<64>;
 def sub_vsx0 : SubRegIndex<128>;
-def sub_vsx1 : SubRegIndex<128>;
+def sub_vsx1 : SubRegIndex<128, 128>;
 def sub_pair0 : SubRegIndex<256>;
-def sub_pair1 : SubRegIndex<256>;
+def sub_pair1 : SubRegIndex<256, 256>;
 }
 
 
 class PPCReg<string n> : Register<n> {
   let Namespace = "PPC";
 }
 
 // We identify all our registers with a 5-bit ID, for consistency's sake.