This is an archive of the discontinued LLVM Phabricator instance.

Differential D92400

[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
ClosedPublic

Authored by foad on Dec 1 2020, 8:57 AM.

Details

Reviewers
arsenm
rampitec
Commits
rGd28624a20948: [AMDGPU] Stop adding an implicit def of vcc_hi for wave32
Summary

This doesn't seem to be needed for anything.

Diff Detail

Event Timeline

foad created this revision.Dec 1 2020, 8:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 1 2020, 8:57 AM
Herald added subscribers: llvm-commits, wenlei, kerbowa and 11 others. · View Herald Transcript
foad requested review of this revision.Dec 1 2020, 8:57 AM
Herald added a subscriber: wdng. · View Herald TranscriptDec 1 2020, 8:57 AM
Harbormaster completed remote builds in B80674: Diff 308677.Dec 1 2020, 9:32 AM
arsenm accepted this revision.Dec 1 2020, 10:04 AM

LGTM, this was really annoying

llvm/lib/Target/AMDGPU/SIISelLowering.cpp
11567

We should really fix the need for this loop too

This revision is now accepted and ready to land.Dec 1 2020, 10:04 AM
foad added inline comments.Dec 1 2020, 11:12 AM
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
11567

How? Would you need separate wave32/wave64 versions of every pseudo that has an implicit VCC operand? There are quite a few of those.

arsenm added inline comments.Dec 1 2020, 11:40 AM
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
11567

Yes, I think having to fixup every instruction is error prone and we have hit bugs from doing this

Closed by commit rGd28624a20948: [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 (authored by foad). · Explain WhyDec 2 2020, 2:12 AM
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGd28624a20948: [AMDGPU] Stop adding an implicit def of vcc_hi for wave32.

Large Diff

This large diff affects 151 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
10 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
6 lines
14 lines
6 lines
12 lines
149 lines
4 lines
6 lines
3 lines
7 lines
9 lines
15 lines
8 lines
4 lines
3 lines
14 lines
14 lines
13 lines
12 lines
29 lines
14 lines
6 lines
6 lines
2 lines
33 lines
8 lines
23 lines
25 lines
18 lines
24 lines
1 line
8 lines
4 lines
3 lines
14 lines
7 lines
4 lines
3 lines
5 lines
10 lines
8 lines
4 lines
3 lines
3 lines
16 lines
15 lines
1 line
1 line
2 lines
2 lines
4 lines
4 lines
2 lines
2 lines
4 lines
14 lines
6 lines
24 lines
24 lines
1 line
9 lines
28 lines
5 lines
1 line
1 line
42 lines
42 lines
14 lines
17 lines
12 lines
9 lines
12 lines
14 lines
15 lines
3 lines
3 lines
3 lines
3 lines
3 lines
19 lines
12 lines
10 lines
8 lines
2 lines
9 lines
25 lines
67 lines
14 lines
5 lines
4 lines
14 lines
5 lines
4 lines
2 lines
12 lines
50 lines
49 lines
49 lines
49 lines
1 line
9 lines
6 lines
10 lines
6 lines
41 lines
2 lines
7 lines
1 line
2 lines
30 lines
94 lines
13 lines
2 lines
3 lines
20 lines
6 lines
12 lines
7 lines
11 lines
7 lines
42 lines
2 lines
6 lines
4 lines
47 lines
47 lines
73 lines
14 lines
47 lines
8 lines
71 lines
19 lines
19 lines
12 lines
12 lines
66 lines
50 lines
50 lines
5 lines
20 lines
2 lines
5 lines
8 lines
32 lines
1 line
1 line
2 lines
1 line
2 lines
8 lines
5 lines

Diff 308918

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 11,555 Lines • ▼ Show 20 Lines if (Info->getScratchRSrcReg() != AMDGPU::PRIVATE_RSRC_REG)
MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg()); MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());
if (Info->getFrameOffsetReg() != AMDGPU::FP_REG) if (Info->getFrameOffsetReg() != AMDGPU::FP_REG)
MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg()); MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());
Info->limitOccupancy(MF); Info->limitOccupancy(MF);
if (ST.isWave32() && !MF.empty()) { if (ST.isWave32() && !MF.empty()) {
// Add VCC_HI def because many instructions marked as imp-use VCC where
// we may only define VCC_LO. If nothing defines VCC_HI we may end up
// having a use of undef.
const SIInstrInfo *TII = ST.getInstrInfo(); const SIInstrInfo *TII = ST.getInstrInfo();
DebugLoc DL;
MachineBasicBlock &MBB = MF.front();
MachineBasicBlock::iterator I = MBB.getFirstNonDebugInstr();
BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), AMDGPU::VCC_HI);
for (auto &MBB : MF) { for (auto &MBB : MF) {
for (auto &MI : MBB) { for (auto &MI : MBB) {
TII->fixImplicitOperands(MI); TII->fixImplicitOperands(MI);
arsenmUnsubmitted
Not Done
ReplyInline Actions

We should really fix the need for this loop too

arsenm: We should really fix the need for this loop too
foadAuthorUnsubmitted
Done
ReplyInline Actions

How? Would you need separate wave32/wave64 versions of every pseudo that has an implicit VCC operand? There are quite a few of those.

foad: How? Would you need separate wave32/wave64 versions of every pseudo that has an implicit VCC…
arsenmUnsubmitted
Not Done
ReplyInline Actions

Yes, I think having to fixup every instruction is error prone and we have hit bugs from doing this

arsenm: Yes, I think having to fixup every instruction is error prone and we have hit bugs from doing…
} }
} }
} }
TargetLoweringBase::finalizeLowering(MF); TargetLoweringBase::finalizeLowering(MF);
// Allocate a VGPR for future SGPR Spill if // Allocate a VGPR for future SGPR Spill if
// "amdgpu-reserve-vgpr-for-sgpr-spill" option is used // "amdgpu-reserve-vgpr-for-sgpr-spill" option is used
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.icmp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir

llvm/test/CodeGen/AMDGPU/add3.ll

llvm/test/CodeGen/AMDGPU/add_shl.ll

llvm/test/CodeGen/AMDGPU/amdpal-elf.ll

llvm/test/CodeGen/AMDGPU/and_or.ll

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll

llvm/test/CodeGen/AMDGPU/cc-update.ll

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll

llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll

llvm/test/CodeGen/AMDGPU/idot2.ll

llvm/test/CodeGen/AMDGPU/idot4s.ll

llvm/test/CodeGen/AMDGPU/idot4u.ll

llvm/test/CodeGen/AMDGPU/idot8s.ll

llvm/test/CodeGen/AMDGPU/idot8u.ll

llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll

llvm/test/CodeGen/AMDGPU/imm16.ll

llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll

llvm/test/CodeGen/AMDGPU/offset-split-flat.ll

llvm/test/CodeGen/AMDGPU/offset-split-global.ll

llvm/test/CodeGen/AMDGPU/or3.ll

llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir

llvm/test/CodeGen/AMDGPU/shl_add.ll

llvm/test/CodeGen/AMDGPU/shl_or.ll

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

llvm/test/CodeGen/AMDGPU/smrd.ll

llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll

llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

llvm/test/CodeGen/AMDGPU/xor3.ll

llvm/test/CodeGen/AMDGPU/xor_add.ll