[RISCV] WIP add DAG combining for rotates and GREVI

[craig.topper]

Summary

This is an initial patch to enable combining (rotate (grev)) and (grev (rotate)). I've added a helper to match rotates that we care about. Not sure if I'm happy with it yet. The match needs more test cases.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
   // We can use any register for comparisons
   setHasMultipleConditionRegisters();
 
   if (Subtarget.hasStdExtZbp()) {
     setTargetDAGCombine(ISD::OR);
+    setTargetDAGCombine(ISD::ROTL);
+    setTargetDAGCombine(ISD::ROTR);
   }
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
   return VT.changeVectorElementTypeToInteger();
if (LHS && RHS && LHS->formsPairWith(*RHS) && LHS->Op == OrOp1) {
       return DAG.getNode(
           RISCVISD::GORCI, DL, VT, LHS->Op,
           DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
     }
   }
   return SDValue();
 }
 
+// Helper to enable rotates by bitwidth/2 to be treated as a GREVI/GREVIW.
+static bool canCombineWithGREVOrGORC(SDNode *N, unsigned &Opcode,
+                                     unsigned &ShAmt, SDValue &Src) {
+  if (N->getOpcode() == ISD::ROTL || N->getOpcode() == ISD::ROTR) {
+    Opcode = RISCVISD::GREVI;
+    ShAmt = N->getValueSizeInBits(0) / 2;
+  } else if (N->getOpcode() == RISCVISD::ROLW ||
+             N->getOpcode() == RISCVISD::RORW) {
+    Opcode = RISCVISD::GREVIW;
+    ShAmt = 16;
+  } else
+    return false;
+
+  // We found a rotate, check that it is a constant that matches the required
+  // value.
+  Src = N->getOperand(0);
+  return isa<ConstantSDNode>(N->getOperand(1)) &&
+         N->getConstantOperandVal(1) == ShAmt;
+}
+
 // Combine (GREVI (GREVI x, C2), C1) -> (GREVI x, C1^C2) when C1^C2 is
 // non-zero, and to x when it is. Any repeated GREVI stage undoes itself.
 // Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2). Repeated stage does
 // not undo itself, but they are redundant.
 static SDValue combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) {
-  unsigned ShAmt1 = N->getConstantOperandVal(1);
   SDValue Src = N->getOperand(0);
 
-  if (Src.getOpcode() != N->getOpcode())
+  unsigned ShAmt2;
+  unsigned Opcode;
+  if (N->getOpcode() == Src.getOpcode()) {
+    ShAmt2 = Src.getConstantOperandVal(1);
+    Src = Src.getOperand(0);
+  } else if (canCombineWithGREVOrGORC(Src.getNode(), Opcode, ShAmt2, Src) &&
+             N->getOpcode() == Opcode) {
+    // Variables assigned by canCombineWithGREVOrGORC.
+  } else
     return SDValue();
 
-  unsigned ShAmt2 = Src.getConstantOperandVal(1);
-  Src = Src.getOperand(0);
+  unsigned ShAmt1 = N->getConstantOperandVal(1);
 
   unsigned CombinedShAmt;
   if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW)
     CombinedShAmt = ShAmt1 | ShAmt2;
   else
     CombinedShAmt = ShAmt1 ^ ShAmt2;
 
   if (CombinedShAmt == 0)
     return Src;
 
   SDLoc DL(N);
   return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src,
                      DAG.getTargetConstant(CombinedShAmt, DL,
                                            N->getOperand(1).getValueType()));
 }
 
+// Combine (rotl/rotr (GREVI X, C1), BitWidth/2) into a single GREVI.
+static SDValue combineRotate(SDNode *N, SelectionDAG &DAG) {
+  assert((N->getOpcode() == ISD::ROTL || N->getOpcode() == ISD::ROTR) &&
+         "Unexpected opcode!");
+
+  SDValue Src = N->getOperand(0);
+
+  // Input must be a GREVI.
+  if (Src.getOpcode() != RISCVISD::GREVI)
+    return SDValue();
+
+  unsigned ShAmt1;
+  unsigned Opcode;
+  SDValue Dummy;
+  if (!canCombineWithGREVOrGORC(N, Opcode, ShAmt1, Dummy) ||
+      Opcode != RISCVISD::GREVI)
+    return SDValue();
+
+  unsigned ShAmt2 = Src.getConstantOperandVal(1);
+
+  unsigned CombinedShAmt = ShAmt1 ^ ShAmt2;
+
+  SDLoc DL(N);
+  return DAG.getNode(RISCVISD::GREVI, DL, N->getValueType(0), Src.getOperand(0),
+                     DAG.getTargetConstant(CombinedShAmt, DL,
+                                           Src.getOperand(1).getValueType()));
+}
+
 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
 
   switch (N->getOpcode()) {
   default:
     break;
   case RISCVISD::SplitF64: {
case RISCVISD::RORW: {
     APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32);
     APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5);
     if (SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI) ||
         SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) {
       if (N->getOpcode() != ISD::DELETED_NODE)
         DCI.AddToWorklist(N);
       return SDValue(N, 0);
     }
+
+    // Combine (ROLW/RORW (GREVIW X, C1), 16) into a single GREVIW.
+    SDValue Src = N->getOperand(0);
+    unsigned ShAmt1;
+    unsigned Opcode;
+    SDValue Dummy;
+    if (Src.getOpcode() == RISCVISD::GREVIW &&
+        canCombineWithGREVOrGORC(N, Opcode, ShAmt1, Dummy) &&
+        Opcode == RISCVISD::GREVIW) {
+      unsigned ShAmt2 = Src.getConstantOperandVal(1);
+      unsigned CombinedShAmt = ShAmt1 ^ ShAmt2;
+      SDLoc DL(N);
+      return DAG.getNode(
+          RISCVISD::GREVIW, DL, N->getValueType(0), Src.getOperand(0),
+          DAG.getTargetConstant(CombinedShAmt, DL,
+                                Src.getOperand(1).getValueType()));
+    }
+
     break;
   }
   case RISCVISD::FSLW:
   case RISCVISD::FSRW: {
     // Only the lower 32 bits of Values and lower 6 bits of shift amount are
     // read.
     SDValue Op0 = N->getOperand(0);
     SDValue Op1 = N->getOperand(1);
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case RISCVISD::GORCI:
     return combineGREVI_GORCI(N, DCI.DAG);
   case ISD::OR:
     if (auto GREV = combineORToGREV(SDValue(N, 0), DCI.DAG, Subtarget))
       return GREV;
     if (auto GORC = combineORToGORC(SDValue(N, 0), DCI.DAG, Subtarget))
       return GORC;
     break;
+  case ISD::ROTL:
+  case ISD::ROTR:
+    return combineRotate(N, DCI.DAG);
   }
 
   return SDValue();
 }
 
 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
   // The following folds are only desirable if `(OP _, c1 << c2)` can be

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def riscv_gorci    : SDNode<"RISCVISD::GORCI", SDT_RISCVGREVGORC, []>;
 def riscv_gorciw   : SDNode<"RISCVISD::GORCIW", SDT_RISCVGREVGORC, []>;
 
 let Predicates = [HasStdExtZbp] in {
 def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;
 def : Pat<(riscv_gorci GPR:$rs1, timm:$shamt), (GORCI GPR:$rs1, timm:$shamt)>;
 } // Predicates = [HasStdExtZbp]
 
-let Predicates = [HasStdExtZbp, IsRV32] in {
-def : Pat<(rotr (riscv_grevi GPR:$rs1, (i32 24)), (i32 16)), (GREVI GPR:$rs1, 8)>;
-def : Pat<(rotl (riscv_grevi GPR:$rs1, (i32 24)), (i32 16)), (GREVI GPR:$rs1, 8)>;
-} // Predicates = [HasStdExtZbp, IsRV32]
-
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
           (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_selectcc GPR:$rs2, (XLenVT 0), (XLenVT 17), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 } // Predicates = [HasStdExtZbt]
 
 // fshl and fshr concatenate their operands in the same order. fsr and fsl

 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(SLOIWPat GPR:$rs1, uimmlog2xlen:$shamt),
           (SLOIW GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : Pat<(SROIWPat GPR:$rs1, uimmlog2xlen:$shamt),
           (SROIW GPR:$rs1, uimmlog2xlen:$shamt)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(riscv_rorw (riscv_greviw GPR:$rs1, 24), (i64 16)), (GREVIW GPR:$rs1, 8)>;
-def : Pat<(riscv_rolw (riscv_greviw GPR:$rs1, 24), (i64 16)), (GREVIW GPR:$rs1, 8)>;
 def : Pat<(riscv_greviw GPR:$rs1, timm:$shamt), (GREVIW GPR:$rs1, timm:$shamt)>;
 def : Pat<(riscv_gorciw GPR:$rs1, timm:$shamt), (GORCIW GPR:$rs1, timm:$shamt)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),