This is an archive of the discontinued LLVM Phabricator instance.

Differential D91671

[DAGCombiner] Precommit Sext Tests
ClosedPublic

Authored by laytonio on Nov 17 2020, 5:43 PM.

Details

Reviewers
RKSimon
Commits
rG7a8b2f692ec4: [DAGCombiner] Precommit Sext Tests for D91589
Summary

Precommit tests for D91589

Diff Detail

Event Timeline

laytonio created this revision.Nov 17 2020, 5:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 17 2020, 5:43 PM
Herald added subscribers: llvm-commits, frasercrmck, luismarques and 21 others. · View Herald Transcript
laytonio requested review of this revision.Nov 17 2020, 5:43 PM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 17 2020, 5:43 PM
laytonio added a comment.Nov 17 2020, 5:45 PM

@RKSimon could you commit these for me? Thanks in advance!

Harbormaster completed remote builds in B79206: Diff 305938.Nov 17 2020, 6:29 PM
RKSimon accepted this revision.Nov 18 2020, 7:44 AM

LGTM - I'll commit it shortly

This revision is now accepted and ready to land.Nov 18 2020, 7:44 AM
This revision was landed with ongoing or failed builds.Nov 18 2020, 7:56 AM
Closed by commit rG7a8b2f692ec4: [DAGCombiner] Precommit Sext Tests for D91589 (authored by RKSimon). · Explain Why
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rG7a8b2f692ec4: [DAGCombiner] Precommit Sext Tests for D91589.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
131 lines
SystemZ/
46 lines

Diff 306109

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: trunc_i64_to_i32: ; RV64I-LABEL: trunc_i64_to_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = trunc i64 %a to i32 %1 = trunc i64 %a to i32
ret i32 %1 ret i32 %1
} }
;; TODO: fold (sext (not x)) -> (add (zext x) -1)
define i32 @sext_of_not_i32(i1 %x) {
; RV32I-LABEL: sext_of_not_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_of_not_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
%xor = xor i1 %x, 1
%sext = sext i1 %xor to i32
ret i32 %sext
}
define i64 @sext_of_not_i64(i1 %x) {
; RV32I-LABEL: sext_of_not_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_of_not_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
%xor = xor i1 %x, 1
%sext = sext i1 %xor to i64
ret i64 %sext
}
;; TODO: fold (sext (not (setcc a, b, cc))) -> (sext (setcc a, b, !cc))
define i32 @sext_of_not_cmp_i32(i32 %x) {
; RV32I-LABEL: sext_of_not_cmp_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, -7
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_of_not_cmp_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
%cmp = icmp eq i32 %x, 7
%xor = xor i1 %cmp, 1
%sext = sext i1 %xor to i32
ret i32 %sext
}
define i64 @sext_of_not_cmp_i64(i64 %x) {
; RV32I-LABEL: sext_of_not_cmp_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_of_not_cmp_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
%cmp = icmp eq i64 %x, 7
%xor = xor i1 %cmp, 1
%sext = sext i1 %xor to i64
ret i64 %sext
}
;; TODO: fold (add (zext (setcc a, b, cc)), -1) -> (sext (setcc a, b, !cc))
define i32 @dec_of_zexted_cmp_i32(i32 %x) {
; RV32I-LABEL: dec_of_zexted_cmp_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, -7
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV64I-LABEL: dec_of_zexted_cmp_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
%cmp = icmp eq i32 %x, 7
%zext = zext i1 %cmp to i32
%dec = sub i32 %zext, 1
ret i32 %dec
}
define i64 @dec_of_zexted_cmp_i64(i64 %x) {
; RV32I-LABEL: dec_of_zexted_cmp_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: seqz a1, a0
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: ret
;
; RV64I-LABEL: dec_of_zexted_cmp_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
%cmp = icmp eq i64 %x, 7
%zext = zext i1 %cmp to i64
%dec = sub i64 %zext, 1
ret i64 %dec
}

llvm/test/CodeGen/SystemZ/sext-zext.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
;; TODO: fold (sext (not x)) -> (add (zext x) -1)
define i32 @sext_of_not(i1 %x) {
; CHECK-LABEL: sext_of_not:
; CHECK: # %bb.0:
; CHECK-NEXT: xilf %r2, 4294967295
; CHECK-NEXT: nilf %r2, 1
; CHECK-NEXT: lcr %r2, %r2
; CHECK-NEXT: br %r14
%xor = xor i1 %x, 1
%sext = sext i1 %xor to i32
ret i32 %sext
}
;; TODO: fold (sext (not (setcc a, b, cc))) -> (sext (setcc a, b, !cc))
define i32 @sext_of_not_cmp(i32 %x) {
; CHECK-LABEL: sext_of_not_cmp:
; CHECK: # %bb.0:
; CHECK-NEXT: chi %r2, 7
; CHECK-NEXT: ipm %r2
; CHECK-NEXT: afi %r2, 1879048192
; CHECK-NEXT: sra %r2, 31
; CHECK-NEXT: br %r14
%cmp = icmp eq i32 %x, 7
%xor = xor i1 %cmp, 1
%sext = sext i1 %xor to i32
ret i32 %sext
}
;; TODO: fold (add (zext (setcc a, b, cc)), -1) -> (sext (setcc a, b, !cc))
define i32 @dec_of_zexted_cmp(i32 %x) {
; CHECK-LABEL: dec_of_zexted_cmp:
; CHECK: # %bb.0:
; CHECK-NEXT: chi %r2, 7
; CHECK-NEXT: ipm %r2
; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31
; CHECK-NEXT: ahi %r2, -1
; CHECK-NEXT: br %r14
%cmp = icmp eq i32 %x, 7
%zext = zext i1 %cmp to i32
%dec = sub i32 %zext, 1
ret i32 %dec
}