[VE] LVLGen sets VL before vector insts

[simoll]

Summary

The VE backend represents vector instructions with an explicit 'i32'
vector length operand. In the VE ISA, the vector length is always read
from the VL hardware register. The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.

[simoll]

• Add a test case for non-changing VL after initial setting.

[kaz7]

LGTM. Please follow clang-tidy naming rule suggestions.

[simoll]

NFC. Formatting.

[craig.topper]

llvm/lib/Target/VE/LVLGen.cpp

92

Does this handle the case of a call in the middle of a group of vector instructions? Such a call might modify VL. But I don't think the call will show VL as a def for findRegisterDefOperandIdx.

[kaz7]

llvm/lib/Target/VE/LVLGen.cpp

92

No, this doesn't handle such case and generates wrong instructions. Thank you for suggestions. I'll prepare updates.

[kaz7]

Add comment about new patch.

llvm/lib/Target/VE/LVLGen.cpp

92

@craig.topper, thank you for your suggestion. I fixed the problem in D92716. Please check it out when you have time. Thanks!

llvm/lib/Target/VE/CMakeLists.txt

 add_llvm_component_group(VE)
 
 set(LLVM_TARGET_DEFINITIONS VE.td)
 
 tablegen(LLVM VEGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM VEGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM VEGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
 add_public_tablegen_target(VECommonTableGen)
 
 add_llvm_target(VECodeGen
+  LVLGen.cpp
   VEAsmPrinter.cpp
   VEFrameLowering.cpp
   VEISelDAGToDAG.cpp
   VEISelLowering.cpp
   VEInstrInfo.cpp
   VEMachineFunctionInfo.cpp
   VEMCInstLower.cpp
   VERegisterInfo.cpp

llvm/lib/Target/VE/LVLGen.cpp

+//===-- LVLGen.cpp - LVL instruction generator ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "VE.h"
+#include "VESubtarget.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "lvl-gen"
+
+namespace {
+struct LVLGen : public MachineFunctionPass {
+  const TargetInstrInfo *TII;
+  const TargetRegisterInfo *TRI;
+
+  static char ID;
+  LVLGen() : MachineFunctionPass(ID) {}
+  bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
+  bool runOnMachineFunction(MachineFunction &F) override;
+
+  unsigned getVL(const MachineInstr &MI);
+  int getVLIndex(unsigned Opcode);
+};
+char LVLGen::ID = 0;
+
+} // end of anonymous namespace
+
+FunctionPass *llvm::createLVLGenPass() { return new LVLGen; }
+
+int LVLGen::getVLIndex(unsigned Opcode) {
+  const MCInstrDesc &MCID = TII->get(Opcode);
+
+  // If an instruction has VLIndex information, return it.
+  if (HAS_VLINDEX(MCID.TSFlags))
+    return GET_VLINDEX(MCID.TSFlags);
+
+  return -1;
+}
+
+// returns a register holding a vector length. NoRegister is returned when
+// this MI does not have a vector length.
+unsigned LVLGen::getVL(const MachineInstr &MI) {
+  int Index = getVLIndex(MI.getOpcode());
+  if (Index >= 0)
+    return MI.getOperand(Index).getReg();
+
+  return VE::NoRegister;
+}
+
+bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
+#define RegName(no)                                                            \
+  (MBB.getParent()->getSubtarget<VESubtarget>().getRegisterInfo()->getName(no))
+
+  bool Changed = false;
+  bool HasRegForVL = false;
+  unsigned RegForVL;
+
+  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) {
+    MachineBasicBlock::iterator MI = I;
+
+    unsigned Reg = getVL(*MI);
+    if (Reg != VE::NoRegister) {
+      LLVM_DEBUG(dbgs() << "Vector instruction found: ");
+      LLVM_DEBUG(MI->dump());
+      LLVM_DEBUG(dbgs() << "Vector length is " << RegName(Reg) << ". ");
+      LLVM_DEBUG(dbgs() << "Current VL is "
+                        << (HasRegForVL ? RegName(RegForVL) : "unknown")
+                        << ". ");
+
+      if (!HasRegForVL || RegForVL != Reg) {
+        LLVM_DEBUG(dbgs() << "Generate a LVL instruction to load "
+                          << RegName(Reg) << ".\n");
+        BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg);
+        HasRegForVL = true;
+        RegForVL = Reg;
+        Changed = true;
+      } else {
+        LLVM_DEBUG(dbgs() << "Reuse current VL.\n");
+      }
+    } else if (HasRegForVL) {
+      // Old VL is overwritten, so disable HasRegForVL.
+      if (MI->findRegisterDefOperandIdx(RegForVL, false, false, TRI) != -1) {
+        LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
+        LLVM_DEBUG(MI->dump());
+        HasRegForVL = false;
+      }
+    }
+    if (HasRegForVL) {
+      // The latest VL is killed, so disable HasRegForVL.
+      if (MI->killsRegister(RegForVL, TRI)) {
+        LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
+        LLVM_DEBUG(MI->dump());
+        HasRegForVL = false;
+      }
+    }
+
+    ++I;
+  }
+  return Changed;
+}
+
+bool LVLGen::runOnMachineFunction(MachineFunction &F) {
+  LLVM_DEBUG(dbgs() << "********** Begin LVLGen **********\n");
+  LLVM_DEBUG(dbgs() << "********** Function: " << F.getName() << '\n');
+  LLVM_DEBUG(F.dump());
+
+  bool Changed = false;
+
+  const VESubtarget &Subtarget = F.getSubtarget<VESubtarget>();
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+
+  for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
+    Changed |= runOnMachineBasicBlock(*FI);
+
+  if (Changed) {
+    LLVM_DEBUG(dbgs() << "\n");
+    LLVM_DEBUG(F.dump());
+  }
+  LLVM_DEBUG(dbgs() << "********** End LVLGen **********\n");
+  return Changed;
+}

llvm/lib/Target/VE/VE.h

 class VETargetMachine;
 class formatted_raw_ostream;
 class AsmPrinter;
 class MCInst;
 class MachineInstr;
 
 FunctionPass *createVEISelDag(VETargetMachine &TM);
 FunctionPass *createVEPromoteToI1Pass();
+FunctionPass *createLVLGenPass();
 
 void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                  AsmPrinter &AP);
 } // namespace llvm
 
 namespace llvm {
 // Enums corresponding to VE condition codes, both icc's and fcc's.  These
 // values must be kept in sync with the ones in the .td file.

llvm/lib/Target/VE/VETargetMachine.cpp

VEPassConfig(VETargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 
   VETargetMachine &getVETargetMachine() const {
     return getTM<VETargetMachine>();
   }
 
   void addIRPasses() override;
   bool addInstSelector() override;
+  void addPreEmitPass() override;
 };
 } // namespace
 
 TargetPassConfig *VETargetMachine::createPassConfig(PassManagerBase &PM) {
   return new VEPassConfig(*this, PM);
 }
 
 void VEPassConfig::addIRPasses() {
   // VE requires atomic expand pass.
   addPass(createAtomicExpandPass());
   TargetPassConfig::addIRPasses();
 }
 
 bool VEPassConfig::addInstSelector() {
   addPass(createVEISelDag(getVETargetMachine()));
   return false;
 }
+
+void VEPassConfig::addPreEmitPass() {
+  // LVLGen should be called after scheduling and register allocation
+  addPass(createLVLGenPass());
+}

llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll

+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+; Test for correct placement of 'lvl' instructions
+
+; Function Attrs: nounwind readonly
+declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
+declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
+
+; Check that the backend can handle constant VL as well as parametric VL
+; sources.
+
+; Function Attrs: nounwind
+define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
+; CHECK-LABEL: switching_vl:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, 256
+; CHECK-NEXT:    lvl %s4
+; CHECK-NEXT:    vld %v0, 8, %s2
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vst %v0, 16, %s3
+; CHECK-NEXT:    lea %s4, 128
+; CHECK-NEXT:    lvl %s4
+; CHECK-NEXT:    vld %v0, 16, %s2
+; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    vst %v0, 16, %s3
+; CHECK-NEXT:    lvl %s4
+; CHECK-NEXT:    vld %v0, 8, %s2
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vst %v0, 16, %s3
+; CHECK-NEXT:    or %s11, 0, %s9
+  %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 256)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
+  %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 128)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl2)
+  %l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 128)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl)
+  ret void
+}
+
+; Check that no redundant 'lvl' is inserted when vector length does not change
+; in a basic block.
+
+
+; Function Attrs: nounwind
+define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
+; CHECK-LABEL: stable_vl:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vld %v0, 8, %s1
+; CHECK-NEXT:    vst %v0, 16, %s2
+; CHECK-NEXT:    vld %v0, 16, %s1
+; CHECK-NEXT:    vst %v0, 16, %s2
+; CHECK-NEXT:    vld %v0, 8, %s1
+; CHECK-NEXT:    vst %v0, 16, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
+  %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 %evl)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl)
+  %l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl)
+  tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl)
+  ret void
+}

llvm/test/CodeGen/VE/VELIntrinsics/vld.ll

 ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
 
 ;;; Test vector load intrinsic instructions
 ;;;
 ;;; Note:
 ;;;   We test VLD*rrl, VLD*irl, VLD*rrl_v, VLD*irl_v
 
 ; Function Attrs: nounwind
 define void @vld_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vld_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vld_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vld_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vld %v0, %s1, %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vld_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vld_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vld_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vld_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, 8, %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vld.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vld.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld.nc %v0, 8, %s1
 ; CHECK-NEXT:    vld.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldu_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldu_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldu %v0, %s1, %s2
 ; CHECK-NEXT:    vldu %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldu_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldu_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldu %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldu_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu %v0, 8, %s1
 ; CHECK-NEXT:    vldu %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldunc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldunc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldunc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldu.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldu.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldunc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldunc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldu.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldunc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldunc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldu.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlsx_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldlsx_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.sx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldlsx_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl.sx %v0, %s1, %s2
 ; CHECK-NEXT:    vldl.sx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldlsx_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldlsx_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl.sx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlsx_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldlsx_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.sx %v0, 8, %s1
 ; CHECK-NEXT:    vldl.sx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlsxnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldlsxnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.sx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldlsxnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl.sx.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldl.sx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldlsxnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldlsxnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl.sx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldlsxnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.sx.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldl.sx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlzx_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldlzx_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.zx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldlzx_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl.zx %v0, %s1, %s2
 ; CHECK-NEXT:    vldl.zx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldlzx_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldlzx_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl.zx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlzx_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldlzx_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.zx %v0, 8, %s1
 ; CHECK-NEXT:    vldl.zx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlzxnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldlzxnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.zx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldlzxnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl.zx.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldl.zx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldlzxnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldlzxnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl.zx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldlzxnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl.zx.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldl.zx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vld2d_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vld2d_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld2d %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vld2d_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vld2d %v0, %s1, %s2
 ; CHECK-NEXT:    vld2d %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vld2d_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vld2d_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld2d %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vld2d_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vld2d_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld2d %v0, 8, %s1
 ; CHECK-NEXT:    vld2d %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vld2dnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vld2dnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vld2dnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vld2d.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vld2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vld2dnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vld2dnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vld2dnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld2d.nc %v0, 8, %s1
 ; CHECK-NEXT:    vld2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu2d_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldu2d_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu2d %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldu2d_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldu2d %v0, %s1, %s2
 ; CHECK-NEXT:    vldu2d %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldu2d_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldu2d_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldu2d %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu2d_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldu2d_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu2d %v0, 8, %s1
 ; CHECK-NEXT:    vldu2d %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu2dnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldu2dnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldu2dnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldu2d.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldu2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldu2dnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldu2dnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldu2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldu2dnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldu2d.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldu2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dsx_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldl2dsx_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.sx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldl2dsx_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl2d.sx %v0, %s1, %s2
 ; CHECK-NEXT:    vldl2d.sx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dsx_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldl2dsx_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl2d.sx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldl2dsx_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.sx %v0, 8, %s1
 ; CHECK-NEXT:    vldl2d.sx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dsxnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldl2dsxnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldl2dsxnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dsxnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldl2dsxnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldl2dsxnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldl2d.sx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dzx_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldl2dzx_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.zx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldl2dzx_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl2d.zx %v0, %s1, %s2
 ; CHECK-NEXT:    vldl2d.zx %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dzx_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldl2dzx_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl2d.zx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldl2dzx_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.zx %v0, 8, %s1
 ; CHECK-NEXT:    vldl2d.zx %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dzxnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vldl2dzxnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
 ; CHECK-LABEL: vldl2dzxnc_vssvl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s3, 256
+; CHECK-NEXT:    lvl %s3
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, %s1, %s2
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, %s1, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256)
   %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
   tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, i8*, <256 x double>, i32)
 
 ; Function Attrs: nounwind
 define void @vldl2dzxnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vldl2dzxnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) {
 ; CHECK-LABEL: vldl2dzxnc_vssvl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, 8, %s1
 ; CHECK-NEXT:    vldl2d.zx.nc %v0, 8, %s0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256)
   %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
   tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
   ret void
 }

llvm/test/CodeGen/VE/VELIntrinsics/vst.ll

 ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
 
 ;;; Test vector store intrinsic instructions
 ;;;
 ;;; Note:
 ;;;   We test VST*rrvl, VST*rrvml, VST*irvl, and VST*irvml instructions.
 
 ; Function Attrs: nounwind
 define void @vst_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vst_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vst_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vst_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vst_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstnc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstnc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstnc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstnc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstnc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstu_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstu_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstu_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstu_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstunc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstunc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstunc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstunc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstunc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstunc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstunc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstunc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstunc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstunc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstuot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstuot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstuot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstuot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstuot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstuot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstuot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstuot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstuot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstuot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstuncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstuncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstuncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstuncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstuncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstuncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstuncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstuncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstuncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstuncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstl_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstl_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstl_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstl_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlnc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstlnc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlnc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstlnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstlnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlnc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstlnc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstlot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstlot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstlot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstlot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstlncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstlncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstlncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstlncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstlncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstlncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstlncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2d_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2d_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2d.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vst2d_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2d_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vst2d_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vst2d_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2d_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vst2d_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dnc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dnc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dnc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vst2dnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dnc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vst2dnc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vst2dot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vst2dot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vst2dncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vst2d.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vst2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vst2dncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vst2dncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vst2dncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vst2dncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vst2d.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2d_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2d_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2d.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2d_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2d_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2d_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstu2d_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2d_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstu2d_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dnc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dnc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dnc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dnc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dnc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstu2dncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstu2d.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstu2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstu2dncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstu2dncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstu2dncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstu2d.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2d_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2d_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2d.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2d_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2d_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2d_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstl2d_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2d_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstl2d_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dnc_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dnc_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.nc %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dnc.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dnc_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dnc_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.nc %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dnc_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dnc_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.nc %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dnc_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dnc_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.nc %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dncot_vssl(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dncot_vssl:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.nc.ot %v0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dncot.vssl(<256 x double>, i64, i8*, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dncot_vssml(i8* %0, i64 %1) {
 ; CHECK-LABEL: vstl2dncot_vssml:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
 ; CHECK-NEXT:    vld %v0, %s1, %s0
 ; CHECK-NEXT:    vstl2d.nc.ot %v0, %s1, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind writeonly
 declare void @llvm.ve.vl.vstl2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
 
 ; Function Attrs: nounwind
 define void @vstl2dncot_vssl_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dncot_vssl_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.nc.ot %v0, 8, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @vstl2dncot_vssml_imm(i8* %0) {
 ; CHECK-LABEL: vstl2dncot_vssml_imm:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
 ; CHECK-NEXT:    vld %v0, 8, %s0
 ; CHECK-NEXT:    vstl2d.nc.ot %v0, 8, %s0, %vm0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
   tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
   ret void
 }