AMDGPU: Factor out large flat offset splitting

[foad]

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

1713

Not really related to your change, but it has always seemed crazy to me to have IsSigned as a template argument instead of a normal argument.

[rampitec]

LGTM

[arsenm]

Move to TII

[foad]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

6988

Don't need this cast.

6990

Or this one.

[arsenm]

e722943e05a16901eb336fc4a3e954b541211383

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

static MemSDNode* findMemSDNode(SDNode *N) {
   assert(isa<BuildVectorSDNode>(N));
   for (SDValue V : N->op_values())
     if (MemSDNode *MN =
           dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
       return MN;
   llvm_unreachable("cannot find MemSDNode in the pattern!");
 }
 
 template <bool IsSigned>
 bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N,
                                           SDValue Addr,
                                           SDValue &VAddr,
                                           SDValue &Offset) const {
   int64_t OffsetVal = 0;
 
   unsigned AS = findMemSDNode(N)->getAddressSpace();
 
if (isBaseWithConstantOffset64(Addr, N0, N1)) {
         // For a FLAT instruction the hardware decides whether to access
         // global/scratch/shared memory based on the high bits of vaddr,
         // ignoring the offset field, so we have to ensure that when we add
         // remainder to vaddr it still points into the same underlying object.
         // The easiest way to do that is to make sure that we split the offset
         // into two pieces that are both >= 0 or both <= 0.
 
         SDLoc DL(N);
-        uint64_t RemainderOffset = COffsetVal;
-        uint64_t ImmField = 0;
-        const unsigned NumBits = TII->getNumFlatOffsetBits(IsSigned);
-        if (IsSigned) {
-          // Use signed division by a power of two to truncate towards 0.
-          int64_t D = 1LL << (NumBits - 1);
-          RemainderOffset = (static_cast<int64_t>(COffsetVal) / D) * D;
-          ImmField = COffsetVal - RemainderOffset;
-        } else if (static_cast<int64_t>(COffsetVal) >= 0) {
-          ImmField = COffsetVal & maskTrailingOnes<uint64_t>(NumBits);
-          RemainderOffset = COffsetVal - ImmField;
-        }
-        assert(TII->isLegalFLATOffset(ImmField, AS, IsSigned));
-        assert(RemainderOffset + ImmField == COffsetVal);
+        uint64_t RemainderOffset;
 
-        OffsetVal = ImmField;
+        std::tie(OffsetVal, RemainderOffset)
+          = TII->splitFlatOffset(COffsetVal, AS, IsSigned);
 
         SDValue AddOffsetLo =
             getMaterializedScalarImm32(Lo_32(RemainderOffset), DL);
         SDValue Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
 
         if (Addr.getValueType().getSizeInBits() == 32) {
           SmallVector<SDValue, 3> Opnds;
           Opnds.push_back(N0);

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   unsigned getNumFlatOffsetBits(bool Signed) const;
 
   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
   /// encoded instruction. If \p Signed, this is for an instruction that
   /// interprets the offset as signed.
   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
                          bool Signed) const;
 
+  /// Split \p COffsetVal into {immediate offset field, remainder offset}
+  /// values.
+  std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
+                                              unsigned AddrSpace,
+                                              bool IsSigned) const;
+
   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
   /// Return -1 if the target-specific opcode for the pseudo instruction does
   /// not exist. If Opcode is not a pseudo instruction, this is identity.
   int pseudoToMCOpcode(int Opcode) const;
 
   /// \brief Check if this instruction should only be used by assembler.
   /// Return true if this opcode should not be used by codegen.
   bool isAsmOnlyOpcode(int MCOp) const;

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (ST.hasFlatSegmentOffsetBug() && AddrSpace == AMDGPUAS::FLAT_ADDRESS)
     return false;
 
   if (ST.getGeneration() >= AMDGPUSubtarget::GFX10)
     return Signed ? isInt<12>(Offset) : isUInt<11>(Offset);
 
   return Signed ? isInt<13>(Offset) :isUInt<12>(Offset);
 }
 
+std::pair<int64_t, int64_t> SIInstrInfo::splitFlatOffset(int64_t COffsetVal,
+                                                         unsigned AddrSpace,
+                                                         bool IsSigned) const {
+  int64_t RemainderOffset = COffsetVal;
+  int64_t ImmField = 0;
+  const unsigned NumBits = getNumFlatOffsetBits(IsSigned);
+  if (IsSigned) {
+    // Use signed division by a power of two to truncate towards 0.
+    int64_t D = 1LL << (NumBits - 1);
+    RemainderOffset = (static_cast<int64_t>(COffsetVal) / D) * D;
+    ImmField = COffsetVal - RemainderOffset;
+  } else if (static_cast<int64_t>(COffsetVal) >= 0) {
+    ImmField = COffsetVal & maskTrailingOnes<uint64_t>(NumBits);
+    RemainderOffset = COffsetVal - ImmField;
+  }
+
+  assert(isLegalFLATOffset(ImmField, AddrSpace, IsSigned));
+  assert(RemainderOffset + ImmField == COffsetVal);
+  return {ImmField, RemainderOffset};
+}
 
 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
 enum SIEncodingFamily {
   SI = 0,
   VI = 1,
   SDWA = 2,
   SDWA9 = 3,
   GFX80 = 4,