[PowerPC] Do not fold `cmp(d|w)` and `subf` instruction to `subf.` if `nsw` is not present

[lkail]

Summary

In PPCInstrInfo::optimizeCompareInstr we seek opportunities to fold cmp(d|w) and subf as an subf.. However, if subf. gets overflow, cr0 can't reflect the correct order, violating the semantics of cmp(d|w).

Fixed https://bugs.llvm.org/show_bug.cgi?id=47830.

[lkail]

Rebased.

[nemanjai]

LGTM with a minor nit.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2144

Please add a note why this is OK when equalityOnly is set.

[lkail]

Update comment and I've pre-commit a mir test https://github.com/llvm/llvm-project/commit/e3e25cfb44bc2a35e3b53d62d37c27b7d13157b6 to demonstrate the situation when equalityOnly is true. The codegen of the test case doesn't change with this patch.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   // forms are fast, and we should use only the fast ones.
 
   // The defining instruction has a record form (or is already a record
   // form). It is possible, however, that we'll need to reverse the condition
   // code of the users.
   if (NewOpC == -1)
     return false;
 
+  // This transformation should not be performed if `nsw` is missing and is not
+  // `equalityOnly` comparison. Since if there is overflow, sub_lt, sub_gt in
+  // CRReg do not reflect correct order. If `equalityOnly` is true, sub_eq in
+  // CRReg can reflect if compared values are equal, this optz is still valid.
+  if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
+      Sub && !Sub->getFlag(MachineInstr::NoSWrap))
+    return false;
+
   // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
   // needs to be updated to be based on SUB.  Push the condition code
   // operands to OperandsToUpdate.  If it is safe to remove CmpInstr, the
   // condition code of these operands will be modified.
   // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
   // comparison against 0, which may modify predicate.
   bool ShouldSwap = false;
   if (Sub && Value == 0) {

llvm/test/CodeGen/PowerPC/pr47830.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
 ; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
 
 define i64 @f(i64 %a, i64 %b) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sub. r3, r3, r4
-; CHECK-NEXT:    isellt r3, 0, r3
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    isellt r3, 0, r5
 ; CHECK-NEXT:    blr
   %c = icmp slt i64 %a, %b
   %d = sub i64 %a, %b
   %e = select i1 %c, i64 0, i64 %d
   ret i64 %e
 }
 
 define i64 @g(i64 %a, i64 %b) {