[ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate

[andreadb]

The new predicate looks good. I only have a couple of nits (see below).

llvm/lib/Target/ARM/ARMScheduleA57.td

45–59

I wonder if this could be formatted in a more readable way.
Maybe the CheckNot could go to a new line.
The last line might be split into multiple lines maybe. The >]>]>> sequence is not very nice.

53–55

What about the original isLdstScaledRegNotPlusLsl2 ?
Is it still used by something else other than the scheduling model?
If not, then it should be removed.

[evgeny777]

Addressed

[andreadb]

Much better. Thanks a lot :)

Assuming that the new numbers are correct, then the patch looks good to me.

[dmgreen]

LGTM. Thanks

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
                          bool SkipDead) const override;
 
   bool isPredicable(const MachineInstr &MI) const override;
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
 
-  // Load, scaled register offset, not plus LSL2
-  bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
-
   /// GetInstSize - Returns the size of the specified MachineInstr.
   ///
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 
 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
   for (const auto &MO : MI.operands())
     if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
       return true;
   return false;
 }
 
-// Load, scaled register offset, not plus LSL2
-bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
-                                                  unsigned Op) const {
-  const MachineOperand &Opc = MI.getOperand(Op + 2);
-  unsigned OffImm = Opc.getImm();
-
-  bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
-  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
-  ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm);
-  if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
-  bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2);
-  return !SimpleScaled;
-}
-
 static bool isEligibleForITBlock(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default: return true;
   case ARM::tADC:   // ADC (register) T1
   case ARM::tADDi3: // ADD (immediate) T1
   case ARM::tADDi8: // ADD (immediate) T2
   case ARM::tADDrr: // ADD (register) T1
   case ARM::tAND:   // AND (register) T1

llvm/lib/Target/ARM/ARMSchedule.td

def IsCPSRDefined : CheckFunctionPredicateWithTII<
   "ARM_MC::isCPSRDefined",
   "ARMBaseInstrInfo::isCPSRDefined"
 >;
 
 def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
 
 let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
   class CheckAM2NoShift<int n> : CheckImmOperand_s<n, "ARM_AM::no_shift">;
+  class CheckAM2ShiftLSL<int n> : CheckImmOperand_s<n, "ARM_AM::lsl">;
 }
 
 let FunctionMapper = "ARM_AM::getAM2Op" in {
+  class CheckAM2OpAdd<int n> : CheckImmOperand_s<n, "ARM_AM::add"> {}
   class CheckAM2OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
 }
 
+let FunctionMapper = "ARM_AM::getAM2Offset" in {
+  class CheckAM2Offset<int n, int of> : CheckImmOperand<n, of> {}
+}
+
 def IsLDMBaseRegInList : CheckFunctionPredicate<
   "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
 >;
 
 let FunctionMapper = "ARM_AM::getAM3Op" in {
   class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
 }
 //===----------------------------------------------------------------------===//

llvm/lib/Target/ARM/ARMScheduleA57.td

class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[
                                       CheckValidRegOperand<n>,
                                       CheckAM3OpSub<!add(n, 1)>]>>;
 
 def IsLdrAm3NegRegOffPred : Am3NegativeRegOffset<2>;
 def IsLdrAm3NegRegOffPredX2 : Am3NegativeRegOffset<3>;
 def IsLdrAm3NegRegOffPredX3 : Am3NegativeRegOffset<4>;
 
 // Load, scaled register offset, not plus LSL2
-def IsLdstsoScaledNotOptimalPredX0 :
-  SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>;
-def IsLdstsoScaledNotOptimalPred :
-  SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>;
-def IsLdstsoScaledNotOptimalPredX2 :
-  SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
+class ScaledRegNotPlusLsl2<int n> : CheckNot<
+                                      CheckAny<[
+                                        CheckAM2NoShift<n>,
+                                        CheckAll<[
+                                          CheckAM2OpAdd<n>,
+                                          CheckAM2ShiftLSL<n>,
+                                          CheckAM2Offset<n, 2>
+                                        ]>
+                                      ]>
+                                    >;
+
+def IsLdstsoScaledNotOptimalPredX0 : MCSchedPredicate<ScaledRegNotPlusLsl2<2>>;
+def IsLdstsoScaledNotOptimalPred : MCSchedPredicate<ScaledRegNotPlusLsl2<3>>;
+def IsLdstsoScaledNotOptimalPredX2 : MCSchedPredicate<ScaledRegNotPlusLsl2<4>>;
 
 def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckAM2NoShift<4>>>;
 
 def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
 def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
 def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
 
 // LDM, base reg in list
 def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
 
   .text
   pld [pc, #8]
   pldw [pc, #-128]
   pldw [pc, r0, lsl #2]
+  pldw [pc, r0, lsl #4]
   pldw [pc, -r0]
   ldr r5, [r7]
   ldr r6, [r3, #63]
   ldr r2, [r4, #4095]!
   ldr r1, [r2], #30
   ldr r3, [r1], #-30
   ldr r3, [r8, r1]
   ldr  r3, [r8, r1, lsl #2]

 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      4     1.00    *      *            pld [pc, #8]
 # CHECK-NEXT:  1      4     1.00    *      *            pldw  [pc, #-128]
 # CHECK-NEXT:  1      4     1.00    *      *            pldw  [pc, r0, lsl #2]
+# CHECK-NEXT:  2      5     1.00    *      *            pldw  [pc, r0, lsl #4]
 # CHECK-NEXT:  2      5     1.00    *      *            pldw  [pc, -r0]
 # CHECK-NEXT:  1      4     1.00    *                   ldr r5, [r7]
 # CHECK-NEXT:  1      4     1.00    *                   ldr r6, [r3, #63]
 # CHECK-NEXT:  2      4     1.00    *                   ldr r2, [r4, #4095]!
 # CHECK-NEXT:  2      4     1.00    *                   ldr r1, [r2], #30
 # CHECK-NEXT:  2      4     1.00    *                   ldr r3, [r1], #-30
 # CHECK-NEXT:  1      4     1.00    *                   ldr r3, [r8, r1]
 # CHECK-NEXT:  1      4     1.00    *                   ldr r3, [r8, r1, lsl #2]
-# CHECK-NEXT:  1      4     1.00    *                   ldr r3, [r8, r1, asr #2]
+# CHECK-NEXT:  2      5     1.00    *                   ldr r3, [r8, r1, asr #2]
 # CHECK-NEXT:  2      5     1.00    *                   ldr r2, [r5, -r3]
 # CHECK-NEXT:  2      4     1.00    *                   ldr r1, [r5, r9]!
 # CHECK-NEXT:  2      4     1.00    *                   ldr r6, [r7, -r8]!
-# CHECK-NEXT:  2      4     1.00    *                   ldr r1, [r0, r2, lsr #3]!
+# CHECK-NEXT:  2      5     1.00    *                   ldr r1, [r0, r2, lsr #3]!
 # CHECK-NEXT:  2      4     1.00    *                   ldr r5, [r9], r2
 # CHECK-NEXT:  2      4     1.00    *                   ldr r4, [r3], -r6
 # CHECK-NEXT:  2      5     1.00    *                   ldr r3, [r8, -r2, lsl #15]
 # CHECK-NEXT:  2      4     1.00    *                   ldr r1, [r5], r3, asr #15
 # CHECK-NEXT:  1      4     1.00    *                   ldrb  r3, [r8]
 # CHECK-NEXT:  1      4     1.00    *                   ldrb  r1, [sp, #63]
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r9, [r3, #4095]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r8, [r1], #22
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r2, [r7], #-19
 # CHECK-NEXT:  1      4     1.00    *                   ldrb  r9, [r8, r5]
 # CHECK-NEXT:  2      5     1.00    *                   ldrb  r1, [r5, -r1]
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r3, [r5, r2]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r3, [r5, r2, lsl #2]!
-# CHECK-NEXT:  2      4     1.00    *                   ldrb  r3, [r5, r2, asr #2]!
+# CHECK-NEXT:  2      5     1.00    *                   ldrb  r3, [r5, r2, asr #2]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r6, [r9, -r3]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r2, [r1], r4
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r8, [r4], -r5
 # CHECK-NEXT:  2      5     1.00    *                   ldrb  r7, [r12, -r1, lsl #15]
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r5, [r2], r9, asr #15
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r3, [r1], #4
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r2, [r8], #-8
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r8, [r7], r6

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     70.50  70.50  173.00 10.00  57.00   -      -
+# CHECK-NEXT:  -     71.50  71.50  174.00 10.00  57.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pld [pc, #8]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pldw  [pc, #-128]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pldw  [pc, r0, lsl #2]
+# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     pldw  [pc, r0, lsl #4]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     pldw  [pc, -r0]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r5, [r7]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r6, [r3, #63]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r4, #4095]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r2], #30
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r3, [r1], #-30
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r3, [r8, r1]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r3, [r8, r1, lsl #2]
-# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r3, [r8, r1, asr #2]
+# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r3, [r8, r1, asr #2]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r5, -r3]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r5, r9]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r6, [r7, -r8]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r0, r2, lsr #3]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r5, [r9], r2
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r4, [r3], -r6
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r3, [r8, -r2, lsl #15]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r5], r3, asr #15