[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

[evgeny777]

Rebased and added context

[andreadb]

llvm/lib/Target/ARM/ARMScheduleA57.td

43

You also need to check that the operand is not the invalid register.
So, something like: CheckNot<CheckInvalidRegOperand<2>>.

As a side note: it might be worthy to add a helper MCSchedPredicate named CheckIsValidRegOperand which is basically a shorthand for
CheckNot<CheckInvalidRegOperand<n>>.

46

Same.

48–50

Same.

By the way: the CheckAll <CheckIsRegOperand, CheckAM3OpSub> sequence is a repeated three times (one per each definition).
You could add a template class which expands to that predicate sequence? Just an idea.

[evgeny777]

@andreadb Looks like I updated wrong diff last time, sorry. Addressed comments

[andreadb]

Nice!
The predicates look good to me.

As always, please wait for the final LGTM from @dmgreen (or other people tthat know how to validate the lat/throughput/resource numbers).

[dmgreen]

Thanks folks. LGTM

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
   // Minus reg for ldstso addr mode
   bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
-  // Scaled register offset in address mode 2
-  bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
 
   /// GetInstSize - Returns the size of the specified MachineInstr.
   ///
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 
 // Minus reg for ldstso addr mode
 bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
                                         unsigned Op) const {
   unsigned OffImm = MI.getOperand(Op + 2).getImm();
   return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
 }
 
-// Load, scaled register offset
-bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
-                                      unsigned Op) const {
-  unsigned OffImm = MI.getOperand(Op + 2).getImm();
-  return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
 static bool isEligibleForITBlock(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default: return true;
   case ARM::tADC:   // ADC (register) T1
   case ARM::tADDi3: // ADD (immediate) T1
   case ARM::tADDi8: // ADD (immediate) T2
   case ARM::tADDrr: // ADD (register) T1
   case ARM::tAND:   // AND (register) T1

llvm/lib/Target/ARM/ARMScheduleA57.td

 // If Addrmode3 contains "minus register"
 def IsLdrAm3NegRegOffPred :
   SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;
 // The same predicate with operand offset 2 and 3:
 def IsLdrAm3NegRegOffPredX2 :
   SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 2)}]>;
 def IsLdrAm3NegRegOffPredX3 :
   SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 3)}]>;
 
 // Load, scaled register offset, not plus LSL2
 def IsLdstsoScaledNotOptimalPredX0 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>;
 def IsLdstsoScaledNotOptimalPred :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>;
 def IsLdstsoScaledNotOptimalPredX2 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
 
 def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
 
 def IsLdstsoMinusRegPredX0 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>;
 def IsLdstsoMinusRegPred :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 1)}]>;
 def IsLdstsoMinusRegPredX2 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
 
-// Load, scaled register offset
-def IsLdrAm2ScaledPred :
-  SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
-
 // LDM, base reg in list
 def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
 
 class A57WriteLMOpsListType<list<SchedWriteRes> writes> {
   list <SchedWriteRes> Writes = writes;
   SchedMachineModel SchedModel = ?;
 }
 
def : InstRW<[A57Write_4cyc_1L_1I, A57WriteLdrAm3PostWrBack],
   (instregex "LDR(H|SH|SB)_POST")>;
 def : InstRW<[A57Write_4cyc_1L, A57WrBackOne],
   (instregex "t2LDR(H|SH|SB)?_POST")>;
 
 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR_POST_REG",
   "LDRB_POST_REG", "LDR(B?)T_POST$")>;
 
 def A57WriteLdrTRegPost : SchedWriteVariant<[
-  SchedVar<IsLdrAm2ScaledPred, [A57Write_4cyc_1I_1L_1M]>,
+  SchedVar<IsLdstsoScaledPredX2, [A57Write_4cyc_1I_1L_1M]>,
   SchedVar<NoSchedPred,        [A57Write_4cyc_1L_1I]>
 ]>;
 def A57WriteLdrTRegPostWrBack : SchedWriteVariant<[
-  SchedVar<IsLdrAm2ScaledPred, [A57WrBackThree]>,
+  SchedVar<IsLdstsoScaledPredX2, [A57WrBackThree]>,
   SchedVar<NoSchedPred,        [A57WrBackTwo]>
 ]>;
 // 4(3) "I0/I1,L,M" for scaled register, otherwise 4(2) "I0/I1,L"
 def : InstRW<[A57WriteLdrTRegPost, A57WriteLdrTRegPostWrBack],
   (instregex "LDRT_POST_REG", "LDRBT_POST_REG")>;
 
 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;
 

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r6, [r9, -r3]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r2, [r1], r4
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r8, [r4], -r5
 # CHECK-NEXT:  1      4     1.00    *                   ldrb  r7, [r12, -r1, lsl #15]
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r5, [r2], r9, asr #15
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r3, [r1], #4
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r2, [r8], #-8
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r8, [r7], r6
-# CHECK-NEXT:  2      4     1.00    *                   ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT:  3      4     1.00    *                   ldrbt r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5, r2]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5, -r2]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r8, r9, [r2, #15]
 # CHECK-NEXT:  4      5     2.00    *                   ldrd  r2, r3, [r9, #32]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r6, r7, [r1], #8
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r2, r3, [r8], #0

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     63.00  63.00  167.00 9.00   57.00   -      -
+# CHECK-NEXT:  -     63.00  63.00  167.00 10.00  57.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pld [pc, #8]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pldw  [pc, #-128]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r5, [r7]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r6, [r3, #63]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r4, #4095]!

 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrb  r6, [r9, -r3]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrb  r2, [r1], r4
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrb  r8, [r4], -r5
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrb  r7, [r12, -r1, lsl #15]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrb  r5, [r2], r9, asr #15
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r3, [r1], #4
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r2, [r8], #-8
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r8, [r7], r6
-# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT:  -     0.50   0.50   1.00   1.00    -      -      -     ldrbt r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5, r2]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5, -r2]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r8, r9, [r2, #15]
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r9, #32]!
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r6, r7, [r1], #8
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r8], #0