[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

[evgeny777]

Rebased and added context

[andreadb]

llvm/lib/Target/ARM/ARMScheduleA57.td

37

You also need to check that the operand is not the invalid register.
So, something like: CheckNot<CheckInvalidRegOperand<2>>.

As a side note: it might be worthy to add a helper MCSchedPredicate named CheckIsValidRegOperand which is basically a shorthand for
CheckNot<CheckInvalidRegOperand<n>>.

40

Same.

42–44

Same.

By the way: the CheckAll <CheckIsRegOperand, CheckAM3OpSub> sequence is a repeated three times (one per each definition).
You could add a template class which expands to that predicate sequence? Just an idea.

[evgeny777]

@andreadb Looks like I updated wrong diff last time, sorry. Addressed comments

[andreadb]

Nice!
The predicates look good to me.

As always, please wait for the final LGTM from @dmgreen (or other people tthat know how to validate the lat/throughput/resource numbers).

[dmgreen]

Thanks folks. LGTM

llvm/include/llvm/Target/TargetInstrPredicate.td

 // operand at position `Index` is a register operand.
 class CheckRegOperand<int Index, Register R> : CheckOperandBase<Index> {
   Register Reg = R;
 }
 
 // Check if register operand at index `Index` is the invalid register.
 class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>;
 
+// Return true if machine operand at position `Index` is a valid
+// register operand.
+class CheckValidRegOperand<int Index> :
+  CheckNot<CheckInvalidRegOperand<Index>>;
+
 // Check that the operand at position `Index` is immediate `Imm`.
 // If field `FunctionMapper` is a non-empty string, then function
 // `FunctionMapper` is applied to the operand value, and the return value is then
 // compared against `Imm`.
 class CheckImmOperand<int Index, int Imm> : CheckOperandBase<Index> {
   int ImmVal = Imm;
 }
 

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
 
   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
                          bool SkipDead) const override;
 
   bool isPredicable(const MachineInstr &MI) const override;
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
-  bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
   // Minus reg for ldstso addr mode
   bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
   // Scaled register offset in address mode 2
   bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
 

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 
 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
   for (const auto &MO : MI.operands())
     if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
       return true;
   return false;
 }
 
-// Load with negative register offset requires additional 1cyc and +I unit
-// for Cortex A57
-bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
-                                             unsigned Op) const {
-  const MachineOperand &Offset = MI.getOperand(Op + 1);
-  const MachineOperand &Opc = MI.getOperand(Op + 2);
-  assert(Opc.isImm());
-  assert(Offset.isReg());
-  int64_t OpcImm = Opc.getImm();
-
-  bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
-  return (isSub && Offset.getReg() != 0);
-}
-
 // Load, scaled register offset, not plus LSL2
 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
                                                   unsigned Op) const {
   const MachineOperand &Opc = MI.getOperand(Op + 2);
   unsigned OffImm = Opc.getImm();
 
   bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
   unsigned Amt = ARM_AM::getAM2Offset(OffImm);

llvm/lib/Target/ARM/ARMSchedule.td

 
 let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
   def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
 }
 
 def IsLDMBaseRegInList : CheckFunctionPredicate<
   "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
 >;
+
+let FunctionMapper = "ARM_AM::getAM3Op" in {
+  class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
+}
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;
 def IIC_iALUsir    : InstrItinClass;

llvm/lib/Target/ARM/ARMScheduleA57.td

 // Cortex A57 rev. r1p0 or later (false = r0px)
 def IsR1P0AndLaterPred : MCSchedPredicate<FalsePred>;
 
 def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
 def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
 def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;
 
 // If Addrmode3 contains "minus register"
-def IsLdrAm3NegRegOffPred :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;
-// The same predicate with operand offset 2 and 3:
-def IsLdrAm3NegRegOffPredX2 :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 2)}]>;
-def IsLdrAm3NegRegOffPredX3 :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 3)}]>;
+class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[
+                                      CheckValidRegOperand<n>,
+                                      CheckAM3OpSub<!add(n, 1)>]>>;
+
+def IsLdrAm3NegRegOffPred : Am3NegativeRegOffset<2>;
+def IsLdrAm3NegRegOffPredX2 : Am3NegativeRegOffset<3>;
+def IsLdrAm3NegRegOffPredX3 : Am3NegativeRegOffset<4>;
 
 // Load, scaled register offset, not plus LSL2
 def IsLdstsoScaledNotOptimalPredX0 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>;
 def IsLdstsoScaledNotOptimalPred :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>;
 def IsLdstsoScaledNotOptimalPredX2 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
 
 def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

 # CHECK-NEXT:  1      4     1.00    *                   ldrb  r7, [r12, -r1, lsl #15]
 # CHECK-NEXT:  2      4     1.00    *                   ldrb  r5, [r2], r9, asr #15
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r3, [r1], #4
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r2, [r8], #-8
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r8, [r7], r6
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5, r2]
-# CHECK-NEXT:  2      4     2.00    *                   ldrd  r0, r1, [r5, -r2]
+# CHECK-NEXT:  4      5     2.00    *                   ldrd  r0, r1, [r5, -r2]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r8, r9, [r2, #15]
 # CHECK-NEXT:  4      5     2.00    *                   ldrd  r2, r3, [r9, #32]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r6, r7, [r1], #8
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r2, r3, [r8], #-0
 # CHECK-NEXT:  2      4     2.00    *                   ldrd  r4, r5, [r1, r3]
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r4, r5, [r7, r2]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r0, r1, [r8], r12
 # CHECK-NEXT:  4      4     2.00    *                   ldrd  r0, r1, [r8], -r12
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r3, [r4]
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r2, [r7, #4]
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r1, [r8, #64]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrh  r12, [sp], #4
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r6, [r5, r4]
-# CHECK-NEXT:  1      4     1.00    *                   ldrh  r6, [r5, -r4]
+# CHECK-NEXT:  2      5     1.00    *                   ldrh  r6, [r5, -r4]
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r3, [r8, r11]!
 # CHECK-NEXT:  1      4     1.00    *                   ldrh  r1, [r2, -r1]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrh  r9, [r7], r2
 # CHECK-NEXT:  2      4     1.00    *                   ldrh  r4, [r3], -r2
 # CHECK-NEXT:  2      4     1.00    *                   ldrht r9, [r7], #128
 # CHECK-NEXT:  2      4     1.00    *                   ldrht r4, [r3], #-75
 # CHECK-NEXT:  2      4     1.00    *                   ldrht r9, [r7], r2
 # CHECK-NEXT:  2      4     1.00    *                   ldrht r4, [r3], -r2

 # CHECK-NEXT:  2      2     1.00           *            strb  sp, [r7], r2, asr #12
 # CHECK-NEXT:  2      1     1.00                  U     strbt r6, [r2], #12
 # CHECK-NEXT:  2      1     1.00                  U     strbt r5, [r6], #-13
 # CHECK-NEXT:  2      2     1.00                  U     strbt r4, [r9], r5
 # CHECK-NEXT:  2      2     1.00                  U     strbt r3, [r8], -r2, lsl #3
 # CHECK-NEXT:  1      1     1.00           *            strd  r0, r1, [r4]
 # CHECK-NEXT:  1      1     1.00           *            strd  r2, r3, [r6, #1]
 # CHECK-NEXT:  1      1     1.00           *            strd  r2, r3, [r6, r2]
-# CHECK-NEXT:  1      1     1.00           *            strd  r2, r3, [r6, -r2]
+# CHECK-NEXT:  2      3     1.00           *            strd  r2, r3, [r6, -r2]
 # CHECK-NEXT:  2      1     1.00           *            strd  r2, r3, [r7, #22]!
 # CHECK-NEXT:  2      1     1.00           *            strd  r4, r5, [r8], #7
 # CHECK-NEXT:  2      1     1.00           *            strd  r4, r5, [sp], #0
 # CHECK-NEXT:  2      1     1.00           *            strd  r6, r7, [lr], #0
 # CHECK-NEXT:  2      1     1.00           *            strd  r6, r7, [r9], #-0
 # CHECK-NEXT:  1      1     1.00           *            strd  r8, r9, [r4, r1]
 # CHECK-NEXT:  2      1     1.00           *            strd  r6, r7, [r3, r9]!
 # CHECK-NEXT:  2      1     1.00           *            strd  r6, r7, [r5], r8

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     63.00  63.00  167.00 9.00   57.00   -      -
+# CHECK-NEXT:  -     65.00  65.00  167.00 9.00   57.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pld [pc, #8]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     pldw  [pc, #-128]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r5, [r7]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r6, [r3, #63]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r4, #4095]!

 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrb  r7, [r12, -r1, lsl #15]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrb  r5, [r2], r9, asr #15
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r3, [r1], #4
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r2, [r8], #-8
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r8, [r7], r6
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5, r2]
-# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r0, r1, [r5, -r2]
+# CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r0, r1, [r5, -r2]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r8, r9, [r2, #15]
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r9, #32]!
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r6, r7, [r1], #8
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r8], #0
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r2, r3, [r8], #-0
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd  r4, r5, [r1, r3]
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r4, r5, [r7, r2]!
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r0, r1, [r8], r12
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd  r0, r1, [r8], -r12
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r3, [r4]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r2, [r7, #4]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r1, [r8, #64]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh  r12, [sp], #4
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r6, [r5, r4]
-# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r6, [r5, -r4]
+# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh  r6, [r5, -r4]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r3, [r8, r11]!
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh  r1, [r2, -r1]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh  r9, [r7], r2
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh  r4, [r3], -r2
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrht r9, [r7], #128
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrht r4, [r3], #-75
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrht r9, [r7], r2
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrht r4, [r3], -r2

 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     strb  sp, [r7], r2, asr #12
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strbt r6, [r2], #12
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strbt r5, [r6], #-13
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     strbt r4, [r9], r5
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     strbt r3, [r8], -r2, lsl #3
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd  r0, r1, [r4]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd  r2, r3, [r6, #1]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd  r2, r3, [r6, r2]
-# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd  r2, r3, [r6, -r2]
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r2, r3, [r6, -r2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r2, r3, [r7, #22]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r4, r5, [r8], #7
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r4, r5, [sp], #0
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r6, r7, [lr], #0
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r6, r7, [r9], #-0
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd  r8, r9, [r4, r1]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r6, r7, [r3, r9]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd  r6, r7, [r5], r8