Page MenuHomePhabricator

[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate
ClosedPublic

Authored by evgeny777 on Oct 23 2020, 7:09 AM.

Diff Detail

Event Timeline

evgeny777 created this revision.Oct 23 2020, 7:09 AM
evgeny777 requested review of this revision.Oct 23 2020, 7:09 AM
evgeny777 updated this revision to Diff 300286.Oct 23 2020, 7:23 AM

Rebased and added context

andreadb added inline comments.Oct 23 2020, 7:32 AM
llvm/lib/Target/ARM/ARMScheduleA57.td
37

You also need to check that the operand is not the invalid register.
So, something like: CheckNot<CheckInvalidRegOperand<2>>.

As a side note: it might be worthy to add a helper MCSchedPredicate named CheckIsValidRegOperand which is basically a shorthand for
CheckNot<CheckInvalidRegOperand<n>>.

40

Same.

42–44

Same.

By the way: the CheckAll <CheckIsRegOperand, CheckAM3OpSub> sequence is a repeated three times (one per each definition).
You could add a template class which expands to that predicate sequence? Just an idea.

evgeny777 updated this revision to Diff 300298.Oct 23 2020, 8:06 AM

@andreadb Looks like I updated wrong diff last time, sorry. Addressed comments

Nice!
The predicates look good to me.

As always, please wait for the final LGTM from @dmgreen (or other people tthat know how to validate the lat/throughput/resource numbers).

dmgreen accepted this revision.Oct 23 2020, 8:50 AM

Thanks folks. LGTM

This revision is now accepted and ready to land.Oct 23 2020, 8:50 AM