This is an archive of the discontinued LLVM Phabricator instance.

Differential D90029

[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate
ClosedPublic

Authored by evgeny777 on Oct 23 2020, 4:59 AM.

Details

Reviewers
andreadb
dmgreen
Commits
rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Diff Detail

Event Timeline

evgeny777 created this revision.Oct 23 2020, 4:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 23 2020, 4:59 AM
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
evgeny777 requested review of this revision.Oct 23 2020, 4:59 AM
evgeny777 added inline comments.
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
166

This should 5 cyc when IsLdstsoScaledNotOptimalPred is converted to MC pred

evgeny777 updated this revision to Diff 300267.Oct 23 2020, 6:32 AM

Simplified

andreadb added a comment.Oct 23 2020, 7:22 AM

The new predicate looks good to me.

dmgreen accepted this revision.Oct 23 2020, 8:51 AM

LGTM

This revision is now accepted and ready to land.Oct 23 2020, 8:51 AM
Closed by commit rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (authored by evgeny777). · Explain WhyOct 26 2020, 1:54 AM
This revision was automatically updated to reflect the committed changes.
evgeny777 added a commit: rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
7 lines
6 lines
9 lines
test/
tools/
llvm-mca/
ARM/
44 lines

Diff 300236

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Context not available.
// Load, scaled register offset, not plus LSL2 // Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const; bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Minus reg for ldstso addr mode
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
// Scaled register offset in address mode 2 // Scaled register offset in address mode 2
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const; bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
Context not available.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Context not available.
return !SimpleScaled; return !SimpleScaled;
} }
// Minus reg for ldstso addr mode
bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
unsigned Op) const {
unsigned OffImm = MI.getOperand(Op + 2).getImm();
return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
}
// Load, scaled register offset // Load, scaled register offset
bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI, bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
unsigned Op) const { unsigned Op) const {
Context not available.

llvm/lib/Target/ARM/ARMSchedule.td

Context not available.
def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">; def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
} }
let FunctionMapper = "ARM_AM::getAM2Op" in {
def CheckAM2OpSub2 : CheckImmOperand_s<2, "ARM_AM::sub">;
def CheckAM2OpSub3 : CheckImmOperand_s<3, "ARM_AM::sub">;
def CheckAM2OpSub4 : CheckImmOperand_s<4, "ARM_AM::sub">;
}
def IsLDMBaseRegInList : CheckFunctionPredicate< def IsLDMBaseRegInList : CheckFunctionPredicate<
"ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList" "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
>; >;
Context not available.

llvm/lib/Target/ARM/ARMScheduleA57.td

Context not available.
def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>; def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
def IsLdstsoMinusRegPredX0 : def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub2>;
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>; def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub3>;
def IsLdstsoMinusRegPred : def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub4>;
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 1)}]>;
def IsLdstsoMinusRegPredX2 :
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
// Load, scaled register offset // Load, scaled register offset
def IsLdrAm2ScaledPred : def IsLdrAm2ScaledPred :
Context not available.

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

Context not available.
# RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s # RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
.text .text
pld [pc, #8]
pldw [pc, #-128]
ldr r5, [r7] ldr r5, [r7]
ldr r6, [r3, #63] ldr r6, [r3, #63]
ldr r2, [r4, #4095]! ldr r2, [r4, #4095]!
Context not available.
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 1.00 * * pld [pc, #8]
# CHECK-NEXT: 1 4 1.00 * * pldw [pc, #-128]
evgeny777AuthorUnsubmitted
Done
ReplyInline Actions

This should 5 cyc when IsLdstsoScaledNotOptimalPred is converted to MC pred

evgeny777: This should 5 cyc when `IsLdstsoScaledNotOptimalPred` is converted to MC pred
# CHECK-NEXT: 1 4 1.00 * ldr r5, [r7] # CHECK-NEXT: 1 4 1.00 * ldr r5, [r7]
# CHECK-NEXT: 1 4 1.00 * ldr r6, [r3, #63] # CHECK-NEXT: 1 4 1.00 * ldr r6, [r3, #63]
# CHECK-NEXT: 2 4 1.00 * ldr r2, [r4, #4095]! # CHECK-NEXT: 2 4 1.00 * ldr r2, [r4, #4095]!
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r2], #30 # CHECK-NEXT: 2 4 1.00 * ldr r1, [r2], #30
# CHECK-NEXT: 2 4 1.00 * ldr r3, [r1], #-30 # CHECK-NEXT: 2 4 1.00 * ldr r3, [r1], #-30
# CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, r1] # CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, r1]
# CHECK-NEXT: 1 4 1.00 * ldr r2, [r5, -r3] # CHECK-NEXT: 2 5 1.00 * ldr r2, [r5, -r3]
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r5, r9]! # CHECK-NEXT: 2 4 1.00 * ldr r1, [r5, r9]!
# CHECK-NEXT: 2 4 1.00 * ldr r6, [r7, -r8]! # CHECK-NEXT: 2 4 1.00 * ldr r6, [r7, -r8]!
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r0, r2, lsr #3]! # CHECK-NEXT: 2 4 1.00 * ldr r1, [r0, r2, lsr #3]!
# CHECK-NEXT: 2 4 1.00 * ldr r5, [r9], r2 # CHECK-NEXT: 2 4 1.00 * ldr r5, [r9], r2
# CHECK-NEXT: 2 4 1.00 * ldr r4, [r3], -r6 # CHECK-NEXT: 2 4 1.00 * ldr r4, [r3], -r6
# CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, -r2, lsl #15] # CHECK-NEXT: 2 5 1.00 * ldr r3, [r8, -r2, lsl #15]
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r5], r3, asr #15 # CHECK-NEXT: 2 4 1.00 * ldr r1, [r5], r3, asr #15
# CHECK-NEXT: 1 4 1.00 * ldrb r3, [r8] # CHECK-NEXT: 1 4 1.00 * ldrb r3, [r8]
# CHECK-NEXT: 1 4 1.00 * ldrb r1, [sp, #63] # CHECK-NEXT: 1 4 1.00 * ldrb r1, [sp, #63]
Context not available.
# CHECK-NEXT: 2 4 1.00 * ldrb r8, [r1], #22 # CHECK-NEXT: 2 4 1.00 * ldrb r8, [r1], #22
# CHECK-NEXT: 2 4 1.00 * ldrb r2, [r7], #-19 # CHECK-NEXT: 2 4 1.00 * ldrb r2, [r7], #-19
# CHECK-NEXT: 1 4 1.00 * ldrb r9, [r8, r5] # CHECK-NEXT: 1 4 1.00 * ldrb r9, [r8, r5]
# CHECK-NEXT: 1 4 1.00 * ldrb r1, [r5, -r1] # CHECK-NEXT: 2 5 1.00 * ldrb r1, [r5, -r1]
# CHECK-NEXT: 2 4 1.00 * ldrb r3, [r5, r2]! # CHECK-NEXT: 2 4 1.00 * ldrb r3, [r5, r2]!
# CHECK-NEXT: 2 4 1.00 * ldrb r6, [r9, -r3]! # CHECK-NEXT: 2 4 1.00 * ldrb r6, [r9, -r3]!
# CHECK-NEXT: 2 4 1.00 * ldrb r2, [r1], r4 # CHECK-NEXT: 2 4 1.00 * ldrb r2, [r1], r4
# CHECK-NEXT: 2 4 1.00 * ldrb r8, [r4], -r5 # CHECK-NEXT: 2 4 1.00 * ldrb r8, [r4], -r5
# CHECK-NEXT: 1 4 1.00 * ldrb r7, [r12, -r1, lsl #15] # CHECK-NEXT: 2 5 1.00 * ldrb r7, [r12, -r1, lsl #15]
# CHECK-NEXT: 2 4 1.00 * ldrb r5, [r2], r9, asr #15 # CHECK-NEXT: 2 4 1.00 * ldrb r5, [r2], r9, asr #15
# CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4 # CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4
# CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8 # CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8
Context not available.
# CHECK-NEXT: 2 1 1.00 * str r9, [sp], #4095 # CHECK-NEXT: 2 1 1.00 * str r9, [sp], #4095
# CHECK-NEXT: 2 1 1.00 * str r1, [r7], #-128 # CHECK-NEXT: 2 1 1.00 * str r1, [r7], #-128
# CHECK-NEXT: 1 1 1.00 * str r9, [r6, r3] # CHECK-NEXT: 1 1 1.00 * str r9, [r6, r3]
# CHECK-NEXT: 1 1 1.00 * str r8, [r0, -r2] # CHECK-NEXT: 2 3 1.00 * str r8, [r0, -r2]
# CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6]! # CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6]!
# CHECK-NEXT: 2 2 1.00 * str r7, [r1, r6, lsl #2]! # CHECK-NEXT: 2 2 1.00 * str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: 2 1 1.00 * str r6, [sp, -r1]! # CHECK-NEXT: 2 3 1.00 * str r6, [sp, -r1]!
# CHECK-NEXT: 2 2 1.00 * str r5, [r3], r9 # CHECK-NEXT: 2 2 1.00 * str r5, [r3], r9
# CHECK-NEXT: 2 2 1.00 * str r4, [r2], -r5 # CHECK-NEXT: 2 2 1.00 * str r4, [r2], -r5
# CHECK-NEXT: 1 1 1.00 * str r3, [r4, -r2, lsl #2] # CHECK-NEXT: 2 3 1.00 * str r3, [r4, -r2, lsl #2]
# CHECK-NEXT: 2 2 1.00 * str r2, [r7], r3, asr #24 # CHECK-NEXT: 2 2 1.00 * str r2, [r7], r3, asr #24
# CHECK-NEXT: 1 1 1.00 * strb r9, [r2] # CHECK-NEXT: 1 1 1.00 * strb r9, [r2]
# CHECK-NEXT: 1 1 1.00 * strb r7, [r1, #3] # CHECK-NEXT: 1 1 1.00 * strb r7, [r1, #3]
Context not available.
# CHECK-NEXT: 2 1 1.00 * strb r5, [r7], #72 # CHECK-NEXT: 2 1 1.00 * strb r5, [r7], #72
# CHECK-NEXT: 2 1 1.00 * strb r1, [sp], #-1 # CHECK-NEXT: 2 1 1.00 * strb r1, [sp], #-1
# CHECK-NEXT: 1 1 1.00 * strb r1, [r2, r9] # CHECK-NEXT: 1 1 1.00 * strb r1, [r2, r9]
# CHECK-NEXT: 1 1 1.00 * strb r2, [r3, -r8] # CHECK-NEXT: 2 3 1.00 * strb r2, [r3, -r8]
# CHECK-NEXT: 2 1 1.00 * strb r3, [r4, r7]! # CHECK-NEXT: 2 1 1.00 * strb r3, [r4, r7]!
# CHECK-NEXT: 2 1 1.00 * strb r4, [r5, -r6]! # CHECK-NEXT: 2 3 1.00 * strb r4, [r5, -r6]!
# CHECK-NEXT: 2 2 1.00 * strb r5, [r6], r5 # CHECK-NEXT: 2 2 1.00 * strb r5, [r6], r5
# CHECK-NEXT: 2 2 1.00 * strb r6, [r2], -r4 # CHECK-NEXT: 2 2 1.00 * strb r6, [r2], -r4
# CHECK-NEXT: 1 1 1.00 * strb r7, [r12, -r3, lsl #5] # CHECK-NEXT: 2 3 1.00 * strb r7, [r12, -r3, lsl #5]
# CHECK-NEXT: 2 2 1.00 * strb sp, [r7], r2, asr #12 # CHECK-NEXT: 2 2 1.00 * strb sp, [r7], r2, asr #12
# CHECK-NEXT: 2 1 1.00 U strbt r6, [r2], #12 # CHECK-NEXT: 2 1 1.00 U strbt r6, [r2], #12
# CHECK-NEXT: 2 1 1.00 U strbt r5, [r6], #-13 # CHECK-NEXT: 2 1 1.00 U strbt r5, [r6], #-13
Context not available.
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
# CHECK-NEXT: - 63.00 63.00 160.00 9.00 55.00 - - # CHECK-NEXT: - 67.00 67.00 162.00 9.00 55.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - pld [pc, #8]
# CHECK-NEXT: - - - 1.00 - - - - pldw [pc, #-128]
# CHECK-NEXT: - - - 1.00 - - - - ldr r5, [r7] # CHECK-NEXT: - - - 1.00 - - - - ldr r5, [r7]
# CHECK-NEXT: - - - 1.00 - - - - ldr r6, [r3, #63] # CHECK-NEXT: - - - 1.00 - - - - ldr r6, [r3, #63]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r4, #4095]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r4, #4095]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r2], #30 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r2], #30
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r1], #-30 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r1], #-30
# CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, r1] # CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, r1]
# CHECK-NEXT: - - - 1.00 - - - - ldr r2, [r5, -r3] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r5, -r3]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5, r9]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5, r9]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r6, [r7, -r8]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r6, [r7, -r8]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r0, r2, lsr #3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r0, r2, lsr #3]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r5, [r9], r2 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r5, [r9], r2
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r4, [r3], -r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r4, [r3], -r6
# CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, -r2, lsl #15] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r8, -r2, lsl #15]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5], r3, asr #15 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5], r3, asr #15
# CHECK-NEXT: - - - 1.00 - - - - ldrb r3, [r8] # CHECK-NEXT: - - - 1.00 - - - - ldrb r3, [r8]
# CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [sp, #63] # CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [sp, #63]
Context not available.
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r1], #22 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r1], #22
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r7], #-19 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r7], #-19
# CHECK-NEXT: - - - 1.00 - - - - ldrb r9, [r8, r5] # CHECK-NEXT: - - - 1.00 - - - - ldrb r9, [r8, r5]
# CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [r5, -r1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r1, [r5, -r1]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r3, [r5, r2]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r3, [r5, r2]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r6, [r9, -r3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r6, [r9, -r3]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r1], r4 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r1], r4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r4], -r5 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r4], -r5
# CHECK-NEXT: - - - 1.00 - - - - ldrb r7, [r12, -r1, lsl #15] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r7, [r12, -r1, lsl #15]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r5, [r2], r9, asr #15 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r5, [r2], r9, asr #15
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8
Context not available.
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r9, [sp], #4095 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r9, [sp], #4095
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r1, [r7], #-128 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r1, [r7], #-128
# CHECK-NEXT: - - - - - 1.00 - - str r9, [r6, r3] # CHECK-NEXT: - - - - - 1.00 - - str r9, [r6, r3]
# CHECK-NEXT: - - - - - 1.00 - - str r8, [r0, -r2] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r8, [r0, -r2]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6]!
# CHECK-NEXT: - - - - 1.00 1.00 - - str r7, [r1, r6, lsl #2]! # CHECK-NEXT: - - - - 1.00 1.00 - - str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r6, [sp, -r1]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r6, [sp, -r1]!
# CHECK-NEXT: - - - - 1.00 1.00 - - str r5, [r3], r9 # CHECK-NEXT: - - - - 1.00 1.00 - - str r5, [r3], r9
# CHECK-NEXT: - - - - 1.00 1.00 - - str r4, [r2], -r5 # CHECK-NEXT: - - - - 1.00 1.00 - - str r4, [r2], -r5
# CHECK-NEXT: - - - - - 1.00 - - str r3, [r4, -r2, lsl #2] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r3, [r4, -r2, lsl #2]
# CHECK-NEXT: - - - - 1.00 1.00 - - str r2, [r7], r3, asr #24 # CHECK-NEXT: - - - - 1.00 1.00 - - str r2, [r7], r3, asr #24
# CHECK-NEXT: - - - - - 1.00 - - strb r9, [r2] # CHECK-NEXT: - - - - - 1.00 - - strb r9, [r2]
# CHECK-NEXT: - - - - - 1.00 - - strb r7, [r1, #3] # CHECK-NEXT: - - - - - 1.00 - - strb r7, [r1, #3]
Context not available.
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r5, [r7], #72 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r5, [r7], #72
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r1, [sp], #-1 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r1, [sp], #-1
# CHECK-NEXT: - - - - - 1.00 - - strb r1, [r2, r9] # CHECK-NEXT: - - - - - 1.00 - - strb r1, [r2, r9]
# CHECK-NEXT: - - - - - 1.00 - - strb r2, [r3, -r8] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r2, [r3, -r8]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r3, [r4, r7]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r3, [r4, r7]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r4, [r5, -r6]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r4, [r5, -r6]!
# CHECK-NEXT: - - - - 1.00 1.00 - - strb r5, [r6], r5 # CHECK-NEXT: - - - - 1.00 1.00 - - strb r5, [r6], r5
# CHECK-NEXT: - - - - 1.00 1.00 - - strb r6, [r2], -r4 # CHECK-NEXT: - - - - 1.00 1.00 - - strb r6, [r2], -r4
# CHECK-NEXT: - - - - - 1.00 - - strb r7, [r12, -r3, lsl #5] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r7, [r12, -r3, lsl #5]
# CHECK-NEXT: - - - - 1.00 1.00 - - strb sp, [r7], r2, asr #12 # CHECK-NEXT: - - - - 1.00 1.00 - - strb sp, [r7], r2, asr #12
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r6, [r2], #12 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r6, [r2], #12
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r5, [r6], #-13 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r5, [r6], #-13
Context not available.