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[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate
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Authored by evgeny777 on Oct 23 2020, 4:59 AM.

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evgeny777 created this revision.Oct 23 2020, 4:59 AM
evgeny777 requested review of this revision.Oct 23 2020, 4:59 AM
evgeny777 added inline comments.
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
166

This should 5 cyc when IsLdstsoScaledNotOptimalPred is converted to MC pred

evgeny777 updated this revision to Diff 300267.Oct 23 2020, 6:32 AM

Simplified

The new predicate looks good to me.

dmgreen accepted this revision.Oct 23 2020, 8:51 AM

LGTM

This revision is now accepted and ready to land.Oct 23 2020, 8:51 AM