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Differential D90029

[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate
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Authored by evgeny777 on Oct 23 2020, 4:59 AM.

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andreadb
dmgreen
Commits
rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

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Event Timeline

evgeny777 created this revision.Oct 23 2020, 4:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 23 2020, 4:59 AM
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
evgeny777 requested review of this revision.Oct 23 2020, 4:59 AM
evgeny777 added inline comments.
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
166

This should 5 cyc when IsLdstsoScaledNotOptimalPred is converted to MC pred

evgeny777 updated this revision to Diff 300267.Oct 23 2020, 6:32 AM

Simplified

andreadb added a comment.Oct 23 2020, 7:22 AM

The new predicate looks good to me.

dmgreen accepted this revision.Oct 23 2020, 8:51 AM

LGTM

This revision is now accepted and ready to land.Oct 23 2020, 8:51 AM
Closed by commit rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (authored by evgeny777). · Explain WhyOct 26 2020, 1:54 AM
This revision was automatically updated to reflect the committed changes.
evgeny777 added a commit: rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.

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llvm/
lib/
Target/
ARM/
2 lines
7 lines
4 lines
9 lines
test/
tools/
llvm-mca/
ARM/
38 lines

Diff 300597

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Linespublic:
bool isPredicable(const MachineInstr &MI) const override; bool isPredicable(const MachineInstr &MI) const override;
// CPSR defined in instruction // CPSR defined in instruction
static bool isCPSRDefined(const MachineInstr &MI); static bool isCPSRDefined(const MachineInstr &MI);
// Load, scaled register offset, not plus LSL2 // Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const; bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Minus reg for ldstso addr mode
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
// Scaled register offset in address mode 2 // Scaled register offset in address mode 2
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const; bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
/// GetInstSize - Returns the size of the specified MachineInstr. /// GetInstSize - Returns the size of the specified MachineInstr.
/// ///
unsigned getInstSizeInBytes(const MachineInstr &MI) const override; unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
unsigned isLoadFromStackSlot(const MachineInstr &MI, unsigned isLoadFromStackSlot(const MachineInstr &MI,
▲ Show 20 Lines • Show All 692 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 628 Lines • ▼ Show 20 Linesbool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
unsigned Amt = ARM_AM::getAM2Offset(OffImm); unsigned Amt = ARM_AM::getAM2Offset(OffImm);
ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm); ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm);
if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2);
return !SimpleScaled; return !SimpleScaled;
} }
// Minus reg for ldstso addr mode
bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
unsigned Op) const {
unsigned OffImm = MI.getOperand(Op + 2).getImm();
return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
}
// Load, scaled register offset // Load, scaled register offset
bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI, bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
unsigned Op) const { unsigned Op) const {
unsigned OffImm = MI.getOperand(Op + 2).getImm(); unsigned OffImm = MI.getOperand(Op + 2).getImm();
return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift; return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
} }
static bool isEligibleForITBlock(const MachineInstr *MI) { static bool isEligibleForITBlock(const MachineInstr *MI) {
▲ Show 20 Lines • Show All 5,563 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMSchedule.td

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
>; >;
def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>; def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in { let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">; def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
} }
let FunctionMapper = "ARM_AM::getAM2Op" in {
class CheckAM2OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
}
def IsLDMBaseRegInList : CheckFunctionPredicate< def IsLDMBaseRegInList : CheckFunctionPredicate<
"ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList" "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
>; >;
let FunctionMapper = "ARM_AM::getAM3Op" in { let FunctionMapper = "ARM_AM::getAM3Op" in {
class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {} class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 260 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMScheduleA57.td

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linesdef IsLdstsoScaledNotOptimalPredX0 :
SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>; SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>;
def IsLdstsoScaledNotOptimalPred : def IsLdstsoScaledNotOptimalPred :
SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>; SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>;
def IsLdstsoScaledNotOptimalPredX2 : def IsLdstsoScaledNotOptimalPredX2 :
SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>; SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>; def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
def IsLdstsoMinusRegPredX0 : def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>; def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
def IsLdstsoMinusRegPred : def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 1)}]>;
def IsLdstsoMinusRegPredX2 :
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
// Load, scaled register offset // Load, scaled register offset
def IsLdrAm2ScaledPred : def IsLdrAm2ScaledPred :
SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>; SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
// LDM, base reg in list // LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>; def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
▲ Show 20 Lines • Show All 1,432 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines# RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
strht r5, [r3], r4 strht r5, [r3], r4
strht r6, [r8], -r0 strht r6, [r8], -r0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
evgeny777AuthorUnsubmitted
Done
ReplyInline Actions

This should 5 cyc when IsLdstsoScaledNotOptimalPred is converted to MC pred

evgeny777: This should 5 cyc when `IsLdstsoScaledNotOptimalPred` is converted to MC pred
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 1.00 * * pld [pc, #8] # CHECK-NEXT: 1 4 1.00 * * pld [pc, #8]
# CHECK-NEXT: 1 4 1.00 * * pldw [pc, #-128] # CHECK-NEXT: 1 4 1.00 * * pldw [pc, #-128]
# CHECK-NEXT: 1 4 1.00 * ldr r5, [r7] # CHECK-NEXT: 1 4 1.00 * ldr r5, [r7]
# CHECK-NEXT: 1 4 1.00 * ldr r6, [r3, #63] # CHECK-NEXT: 1 4 1.00 * ldr r6, [r3, #63]
# CHECK-NEXT: 2 4 1.00 * ldr r2, [r4, #4095]! # CHECK-NEXT: 2 4 1.00 * ldr r2, [r4, #4095]!
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r2], #30 # CHECK-NEXT: 2 4 1.00 * ldr r1, [r2], #30
# CHECK-NEXT: 2 4 1.00 * ldr r3, [r1], #-30 # CHECK-NEXT: 2 4 1.00 * ldr r3, [r1], #-30
# CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, r1] # CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, r1]
# CHECK-NEXT: 1 4 1.00 * ldr r2, [r5, -r3] # CHECK-NEXT: 2 5 1.00 * ldr r2, [r5, -r3]
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r5, r9]! # CHECK-NEXT: 2 4 1.00 * ldr r1, [r5, r9]!
# CHECK-NEXT: 2 4 1.00 * ldr r6, [r7, -r8]! # CHECK-NEXT: 2 4 1.00 * ldr r6, [r7, -r8]!
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r0, r2, lsr #3]! # CHECK-NEXT: 2 4 1.00 * ldr r1, [r0, r2, lsr #3]!
# CHECK-NEXT: 2 4 1.00 * ldr r5, [r9], r2 # CHECK-NEXT: 2 4 1.00 * ldr r5, [r9], r2
# CHECK-NEXT: 2 4 1.00 * ldr r4, [r3], -r6 # CHECK-NEXT: 2 4 1.00 * ldr r4, [r3], -r6
# CHECK-NEXT: 1 4 1.00 * ldr r3, [r8, -r2, lsl #15] # CHECK-NEXT: 2 5 1.00 * ldr r3, [r8, -r2, lsl #15]
# CHECK-NEXT: 2 4 1.00 * ldr r1, [r5], r3, asr #15 # CHECK-NEXT: 2 4 1.00 * ldr r1, [r5], r3, asr #15
# CHECK-NEXT: 1 4 1.00 * ldrb r3, [r8] # CHECK-NEXT: 1 4 1.00 * ldrb r3, [r8]
# CHECK-NEXT: 1 4 1.00 * ldrb r1, [sp, #63] # CHECK-NEXT: 1 4 1.00 * ldrb r1, [sp, #63]
# CHECK-NEXT: 2 4 1.00 * ldrb r9, [r3, #4095]! # CHECK-NEXT: 2 4 1.00 * ldrb r9, [r3, #4095]!
# CHECK-NEXT: 2 4 1.00 * ldrb r8, [r1], #22 # CHECK-NEXT: 2 4 1.00 * ldrb r8, [r1], #22
# CHECK-NEXT: 2 4 1.00 * ldrb r2, [r7], #-19 # CHECK-NEXT: 2 4 1.00 * ldrb r2, [r7], #-19
# CHECK-NEXT: 1 4 1.00 * ldrb r9, [r8, r5] # CHECK-NEXT: 1 4 1.00 * ldrb r9, [r8, r5]
# CHECK-NEXT: 1 4 1.00 * ldrb r1, [r5, -r1] # CHECK-NEXT: 2 5 1.00 * ldrb r1, [r5, -r1]
# CHECK-NEXT: 2 4 1.00 * ldrb r3, [r5, r2]! # CHECK-NEXT: 2 4 1.00 * ldrb r3, [r5, r2]!
# CHECK-NEXT: 2 4 1.00 * ldrb r6, [r9, -r3]! # CHECK-NEXT: 2 4 1.00 * ldrb r6, [r9, -r3]!
# CHECK-NEXT: 2 4 1.00 * ldrb r2, [r1], r4 # CHECK-NEXT: 2 4 1.00 * ldrb r2, [r1], r4
# CHECK-NEXT: 2 4 1.00 * ldrb r8, [r4], -r5 # CHECK-NEXT: 2 4 1.00 * ldrb r8, [r4], -r5
# CHECK-NEXT: 1 4 1.00 * ldrb r7, [r12, -r1, lsl #15] # CHECK-NEXT: 2 5 1.00 * ldrb r7, [r12, -r1, lsl #15]
# CHECK-NEXT: 2 4 1.00 * ldrb r5, [r2], r9, asr #15 # CHECK-NEXT: 2 4 1.00 * ldrb r5, [r2], r9, asr #15
# CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4 # CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4
# CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8 # CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8
# CHECK-NEXT: 2 4 1.00 * ldrbt r8, [r7], r6 # CHECK-NEXT: 2 4 1.00 * ldrbt r8, [r7], r6
# CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12 # CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5] # CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5]
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5, r2] # CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5, r2]
# CHECK-NEXT: 4 5 2.00 * ldrd r0, r1, [r5, -r2] # CHECK-NEXT: 4 5 2.00 * ldrd r0, r1, [r5, -r2]
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 16 10 16.00 * ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc} # CHECK-NEXT: 16 10 16.00 * ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
# CHECK-NEXT: 32 11 16.00 * ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc} # CHECK-NEXT: 32 11 16.00 * ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
# CHECK-NEXT: 1 1 1.00 * str r8, [r12] # CHECK-NEXT: 1 1 1.00 * str r8, [r12]
# CHECK-NEXT: 1 1 1.00 * str r7, [r1, #12] # CHECK-NEXT: 1 1 1.00 * str r7, [r1, #12]
# CHECK-NEXT: 2 1 1.00 * str r3, [r5, #40]! # CHECK-NEXT: 2 1 1.00 * str r3, [r5, #40]!
# CHECK-NEXT: 2 1 1.00 * str r9, [sp], #4095 # CHECK-NEXT: 2 1 1.00 * str r9, [sp], #4095
# CHECK-NEXT: 2 1 1.00 * str r1, [r7], #-128 # CHECK-NEXT: 2 1 1.00 * str r1, [r7], #-128
# CHECK-NEXT: 1 1 1.00 * str r9, [r6, r3] # CHECK-NEXT: 1 1 1.00 * str r9, [r6, r3]
# CHECK-NEXT: 1 1 1.00 * str r8, [r0, -r2] # CHECK-NEXT: 2 3 1.00 * str r8, [r0, -r2]
# CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6]! # CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6]!
# CHECK-NEXT: 2 2 1.00 * str r7, [r1, r6, lsl #2]! # CHECK-NEXT: 2 2 1.00 * str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: 2 1 1.00 * str r6, [sp, -r1]! # CHECK-NEXT: 2 3 1.00 * str r6, [sp, -r1]!
# CHECK-NEXT: 2 2 1.00 * str r5, [r3], r9 # CHECK-NEXT: 2 2 1.00 * str r5, [r3], r9
# CHECK-NEXT: 2 2 1.00 * str r4, [r2], -r5 # CHECK-NEXT: 2 2 1.00 * str r4, [r2], -r5
# CHECK-NEXT: 1 1 1.00 * str r3, [r4, -r2, lsl #2] # CHECK-NEXT: 2 3 1.00 * str r3, [r4, -r2, lsl #2]
# CHECK-NEXT: 2 2 1.00 * str r2, [r7], r3, asr #24 # CHECK-NEXT: 2 2 1.00 * str r2, [r7], r3, asr #24
# CHECK-NEXT: 1 1 1.00 * strb r9, [r2] # CHECK-NEXT: 1 1 1.00 * strb r9, [r2]
# CHECK-NEXT: 1 1 1.00 * strb r7, [r1, #3] # CHECK-NEXT: 1 1 1.00 * strb r7, [r1, #3]
# CHECK-NEXT: 2 1 1.00 * strb r6, [r4, #405]! # CHECK-NEXT: 2 1 1.00 * strb r6, [r4, #405]!
# CHECK-NEXT: 2 1 1.00 * strb r5, [r7], #72 # CHECK-NEXT: 2 1 1.00 * strb r5, [r7], #72
# CHECK-NEXT: 2 1 1.00 * strb r1, [sp], #-1 # CHECK-NEXT: 2 1 1.00 * strb r1, [sp], #-1
# CHECK-NEXT: 1 1 1.00 * strb r1, [r2, r9] # CHECK-NEXT: 1 1 1.00 * strb r1, [r2, r9]
# CHECK-NEXT: 1 1 1.00 * strb r2, [r3, -r8] # CHECK-NEXT: 2 3 1.00 * strb r2, [r3, -r8]
# CHECK-NEXT: 2 1 1.00 * strb r3, [r4, r7]! # CHECK-NEXT: 2 1 1.00 * strb r3, [r4, r7]!
# CHECK-NEXT: 2 1 1.00 * strb r4, [r5, -r6]! # CHECK-NEXT: 2 3 1.00 * strb r4, [r5, -r6]!
# CHECK-NEXT: 2 2 1.00 * strb r5, [r6], r5 # CHECK-NEXT: 2 2 1.00 * strb r5, [r6], r5
# CHECK-NEXT: 2 2 1.00 * strb r6, [r2], -r4 # CHECK-NEXT: 2 2 1.00 * strb r6, [r2], -r4
# CHECK-NEXT: 1 1 1.00 * strb r7, [r12, -r3, lsl #5] # CHECK-NEXT: 2 3 1.00 * strb r7, [r12, -r3, lsl #5]
# CHECK-NEXT: 2 2 1.00 * strb sp, [r7], r2, asr #12 # CHECK-NEXT: 2 2 1.00 * strb sp, [r7], r2, asr #12
# CHECK-NEXT: 2 1 1.00 U strbt r6, [r2], #12 # CHECK-NEXT: 2 1 1.00 U strbt r6, [r2], #12
# CHECK-NEXT: 2 1 1.00 U strbt r5, [r6], #-13 # CHECK-NEXT: 2 1 1.00 U strbt r5, [r6], #-13
# CHECK-NEXT: 2 2 1.00 U strbt r4, [r9], r5 # CHECK-NEXT: 2 2 1.00 U strbt r4, [r9], r5
# CHECK-NEXT: 2 2 1.00 U strbt r3, [r8], -r2, lsl #3 # CHECK-NEXT: 2 2 1.00 U strbt r3, [r8], -r2, lsl #3
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r4] # CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r4]
# CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, #1] # CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, #1]
# CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, r2] # CHECK-NEXT: 1 1 1.00 * strd r2, r3, [r6, r2]
Show All 28 Lines
# CHECK-NEXT: [2] - A57UnitL # CHECK-NEXT: [2] - A57UnitL
# CHECK-NEXT: [3] - A57UnitM # CHECK-NEXT: [3] - A57UnitM
# CHECK-NEXT: [4] - A57UnitS # CHECK-NEXT: [4] - A57UnitS
# CHECK-NEXT: [5] - A57UnitW # CHECK-NEXT: [5] - A57UnitW
# CHECK-NEXT: [6] - A57UnitX # CHECK-NEXT: [6] - A57UnitX
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
# CHECK-NEXT: - 65.00 65.00 167.00 9.00 57.00 - - # CHECK-NEXT: - 69.00 69.00 167.00 9.00 57.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - pld [pc, #8] # CHECK-NEXT: - - - 1.00 - - - - pld [pc, #8]
# CHECK-NEXT: - - - 1.00 - - - - pldw [pc, #-128] # CHECK-NEXT: - - - 1.00 - - - - pldw [pc, #-128]
# CHECK-NEXT: - - - 1.00 - - - - ldr r5, [r7] # CHECK-NEXT: - - - 1.00 - - - - ldr r5, [r7]
# CHECK-NEXT: - - - 1.00 - - - - ldr r6, [r3, #63] # CHECK-NEXT: - - - 1.00 - - - - ldr r6, [r3, #63]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r4, #4095]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r4, #4095]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r2], #30 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r2], #30
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r1], #-30 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r1], #-30
# CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, r1] # CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, r1]
# CHECK-NEXT: - - - 1.00 - - - - ldr r2, [r5, -r3] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r2, [r5, -r3]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5, r9]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5, r9]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r6, [r7, -r8]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r6, [r7, -r8]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r0, r2, lsr #3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r0, r2, lsr #3]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r5, [r9], r2 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r5, [r9], r2
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r4, [r3], -r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r4, [r3], -r6
# CHECK-NEXT: - - - 1.00 - - - - ldr r3, [r8, -r2, lsl #15] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r3, [r8, -r2, lsl #15]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5], r3, asr #15 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldr r1, [r5], r3, asr #15
# CHECK-NEXT: - - - 1.00 - - - - ldrb r3, [r8] # CHECK-NEXT: - - - 1.00 - - - - ldrb r3, [r8]
# CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [sp, #63] # CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [sp, #63]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r9, [r3, #4095]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r9, [r3, #4095]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r1], #22 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r1], #22
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r7], #-19 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r7], #-19
# CHECK-NEXT: - - - 1.00 - - - - ldrb r9, [r8, r5] # CHECK-NEXT: - - - 1.00 - - - - ldrb r9, [r8, r5]
# CHECK-NEXT: - - - 1.00 - - - - ldrb r1, [r5, -r1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r1, [r5, -r1]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r3, [r5, r2]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r3, [r5, r2]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r6, [r9, -r3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r6, [r9, -r3]!
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r1], r4 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r2, [r1], r4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r4], -r5 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r8, [r4], -r5
# CHECK-NEXT: - - - 1.00 - - - - ldrb r7, [r12, -r1, lsl #15] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r7, [r12, -r1, lsl #15]
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r5, [r2], r9, asr #15 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrb r5, [r2], r9, asr #15
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r8, [r7], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r8, [r7], r6
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r1, [r2], -r6, lsl #12 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5] # CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5]
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5, r2] # CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5, r2]
# CHECK-NEXT: - 1.00 1.00 2.00 - - - - ldrd r0, r1, [r5, -r2] # CHECK-NEXT: - 1.00 1.00 2.00 - - - - ldrd r0, r1, [r5, -r2]
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
# CHECK-NEXT: - - - 16.00 - - - - ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc} # CHECK-NEXT: - - - 16.00 - - - - ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
# CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc} # CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
# CHECK-NEXT: - - - - - 1.00 - - str r8, [r12] # CHECK-NEXT: - - - - - 1.00 - - str r8, [r12]
# CHECK-NEXT: - - - - - 1.00 - - str r7, [r1, #12] # CHECK-NEXT: - - - - - 1.00 - - str r7, [r1, #12]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r3, [r5, #40]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r3, [r5, #40]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r9, [sp], #4095 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r9, [sp], #4095
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r1, [r7], #-128 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r1, [r7], #-128
# CHECK-NEXT: - - - - - 1.00 - - str r9, [r6, r3] # CHECK-NEXT: - - - - - 1.00 - - str r9, [r6, r3]
# CHECK-NEXT: - - - - - 1.00 - - str r8, [r0, -r2] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r8, [r0, -r2]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6]!
# CHECK-NEXT: - - - - 1.00 1.00 - - str r7, [r1, r6, lsl #2]! # CHECK-NEXT: - - - - 1.00 1.00 - - str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r6, [sp, -r1]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r6, [sp, -r1]!
# CHECK-NEXT: - - - - 1.00 1.00 - - str r5, [r3], r9 # CHECK-NEXT: - - - - 1.00 1.00 - - str r5, [r3], r9
# CHECK-NEXT: - - - - 1.00 1.00 - - str r4, [r2], -r5 # CHECK-NEXT: - - - - 1.00 1.00 - - str r4, [r2], -r5
# CHECK-NEXT: - - - - - 1.00 - - str r3, [r4, -r2, lsl #2] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r3, [r4, -r2, lsl #2]
# CHECK-NEXT: - - - - 1.00 1.00 - - str r2, [r7], r3, asr #24 # CHECK-NEXT: - - - - 1.00 1.00 - - str r2, [r7], r3, asr #24
# CHECK-NEXT: - - - - - 1.00 - - strb r9, [r2] # CHECK-NEXT: - - - - - 1.00 - - strb r9, [r2]
# CHECK-NEXT: - - - - - 1.00 - - strb r7, [r1, #3] # CHECK-NEXT: - - - - - 1.00 - - strb r7, [r1, #3]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r6, [r4, #405]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r6, [r4, #405]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r5, [r7], #72 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r5, [r7], #72
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r1, [sp], #-1 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r1, [sp], #-1
# CHECK-NEXT: - - - - - 1.00 - - strb r1, [r2, r9] # CHECK-NEXT: - - - - - 1.00 - - strb r1, [r2, r9]
# CHECK-NEXT: - - - - - 1.00 - - strb r2, [r3, -r8] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r2, [r3, -r8]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r3, [r4, r7]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r3, [r4, r7]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r4, [r5, -r6]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r4, [r5, -r6]!
# CHECK-NEXT: - - - - 1.00 1.00 - - strb r5, [r6], r5 # CHECK-NEXT: - - - - 1.00 1.00 - - strb r5, [r6], r5
# CHECK-NEXT: - - - - 1.00 1.00 - - strb r6, [r2], -r4 # CHECK-NEXT: - - - - 1.00 1.00 - - strb r6, [r2], -r4
# CHECK-NEXT: - - - - - 1.00 - - strb r7, [r12, -r3, lsl #5] # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strb r7, [r12, -r3, lsl #5]
# CHECK-NEXT: - - - - 1.00 1.00 - - strb sp, [r7], r2, asr #12 # CHECK-NEXT: - - - - 1.00 1.00 - - strb sp, [r7], r2, asr #12
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r6, [r2], #12 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r6, [r2], #12
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r5, [r6], #-13 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - strbt r5, [r6], #-13
# CHECK-NEXT: - - - - 1.00 1.00 - - strbt r4, [r9], r5 # CHECK-NEXT: - - - - 1.00 1.00 - - strbt r4, [r9], r5
# CHECK-NEXT: - - - - 1.00 1.00 - - strbt r3, [r8], -r2, lsl #3 # CHECK-NEXT: - - - - 1.00 1.00 - - strbt r3, [r8], -r2, lsl #3
# CHECK-NEXT: - - - - - 1.00 - - strd r0, r1, [r4] # CHECK-NEXT: - - - - - 1.00 - - strd r0, r1, [r4]
# CHECK-NEXT: - - - - - 1.00 - - strd r2, r3, [r6, #1] # CHECK-NEXT: - - - - - 1.00 - - strd r2, r3, [r6, #1]
# CHECK-NEXT: - - - - - 1.00 - - strd r2, r3, [r6, r2] # CHECK-NEXT: - - - - - 1.00 - - strd r2, r3, [r6, r2]
Show All 23 Lines