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[ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC
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Authored by evgeny777 on Oct 23 2020, 2:52 AM.

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dmgreen
andreadb

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evgeny777 requested review of this revision.Oct 23 2020, 2:52 AM

LGTM.

This revision is now accepted and ready to land.Oct 23 2020, 3:07 AM

This revision was automatically updated to reflect the committed changes.

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	// Therefore, IssueWidth is set to the narrower of the two at three, while still			// Therefore, IssueWidth is set to the narrower of the two at three, while still
	// modeling the machine as out-of-order.			// modeling the machine as out-of-order.

	def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;			def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;
	def IsCPSRDefinedAndPredicatedPred :			def IsCPSRDefinedAndPredicatedPred :
	MCSchedPredicate<IsCPSRDefinedAndPredicated>;			MCSchedPredicate<IsCPSRDefinedAndPredicated>;

	// Cortex A57 rev. r1p0 or later (false = r0px)			// Cortex A57 rev. r1p0 or later (false = r0px)
	def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;			def IsR1P0AndLaterPred : MCSchedPredicate<FalsePred>;

	def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;			def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
	def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;			def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
	def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;			def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;

	// If Addrmode3 contains "minus register"			// If Addrmode3 contains "minus register"
	def IsLdrAm3NegRegOffPred :			def IsLdrAm3NegRegOffPred :
	SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;			SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;
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