[ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC

[andreadb]

LGTM.

llvm/lib/Target/ARM/ARMScheduleA57.td

 // Therefore, IssueWidth is set to the narrower of the two at three, while still
 // modeling the machine as out-of-order.
 
 def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;
 def IsCPSRDefinedAndPredicatedPred :
     MCSchedPredicate<IsCPSRDefinedAndPredicated>;
 
 // Cortex A57 rev. r1p0 or later (false = r0px)
-def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
+def IsR1P0AndLaterPred : MCSchedPredicate<FalsePred>;
 
 def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
 def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
 def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;
 
 // If Addrmode3 contains "minus register"
 def IsLdrAm3NegRegOffPred :
   SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;