[ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate

[evgeny777]

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

255

Cortex-A57 ldm* scheduling seems to be broken in terms of number of uops for instructions having base reg in register list. Patch doesn't address this.

[dmgreen]

llvm/lib/Target/ARM/ARMScheduleA57.td

515

Can you explain the operands this uses? Two from the predicate, And then N*2 for the variable number of regs split into groups of 2?

I think the _UPD forms will have an extra operand, and LDMIA looks like it has 3 + 2*N.

t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3

vs

$sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

52

I think it's common to use I and E for the variables.

[evgeny777]

llvm/lib/Target/ARM/ARMScheduleA57.td

515

Can you explain the operands this uses? Two from the predicate, And then N*2 for the variable number of regs split into groups of 2?

Normal (no update) forms of LDM have N + 3 operands, where N is number of memory accesses. Cortex-a57 model defines same write lists for N and N+1 memory accesses, where N is odd. So A57LMAddrPred1 will trigger for N = 1 and N = 2 (with total number of operands being 4 and 5 respectively), A57LMAddrPred2 for N = 3 and N = 4 and so on

I think the _UPD forms will have an extra operand, and LDMIA looks like it has 3 + 2*N

Right, that's a bug. I'll update the diff.

[evgeny777]

Fixed issue with update forms of ldm* instructions

[evgeny777]

Fixed variable names

[dmgreen]

OK thanks. Looks like a good improvement to me.

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
   // Load, scaled register offset
   bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
   // Minus reg for ldstso addr mode
   bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
   // Scaled register offset in address mode 2
   bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
-  // Load multiple, base reg in list
-  bool isLDMBaseRegInList(const MachineInstr &MI) const;
-  // get LDM variable defs size
-  unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
 
   /// GetInstSize - Returns the size of the specified MachineInstr.
   ///
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
   } else {
     // Assume the worst.
     DefCycle = RegNo + 2;
   }
 
   return DefCycle;
 }
 
-bool ARMBaseInstrInfo::isLDMBaseRegInList(const MachineInstr &MI) const {
-  Register BaseReg = MI.getOperand(0).getReg();
-  for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
-    const auto &Op = MI.getOperand(i);
-    if (Op.isReg() && Op.getReg() == BaseReg)
-      return true;
-  }
-  return false;
-}
-unsigned
-ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {
-  // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops
-  // (outs GPR:$wb), (ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops)
-  return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
-}
-
 int
 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
                                  const MCInstrDesc &DefMCID,
                                  unsigned DefClass,
                                  unsigned DefIdx, unsigned DefAlign) const {
   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
   if (RegNo <= 0)
     // Def is the address writeback.

llvm/lib/Target/ARM/ARMSchedule.td

 
 def IsCPSRDefined : CheckFunctionPredicateWithTII<
   "ARM_MC::isCPSRDefined",
   "ARMBaseInstrInfo::isCPSRDefined"
 >;
 
 def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
 
+def IsLDMBaseRegInList : CheckFunctionPredicate<
+  "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
+>;
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;
 def IIC_iALUsir    : InstrItinClass;

llvm/lib/Target/ARM/ARMScheduleA57.td

 def IsLdstsoMinusRegPredX2 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
 
 // Load, scaled register offset
 def IsLdrAm2ScaledPred :
   SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
 
 // LDM, base reg in list
-def IsLdmBaseRegInList :
-  SchedPredicate<[{TII->isLDMBaseRegInList(*MI)}]>;
+def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
 
 class A57WriteLMOpsListType<list<SchedWriteRes> writes> {
   list <SchedWriteRes> Writes = writes;
   SchedMachineModel SchedModel = ?;
 }
 
 // *** Common description and scheduling model parameters taken from AArch64 ***
 // (AArch64SchedA57.td)
def A57WritePLD : SchedWriteVariant<[
   SchedVar<IsLdstsoScaledNotOptimalPredX0, [A57Write_5cyc_1I_1L]>,
   SchedVar<IsLdstsoMinusRegPredX0,         [A57Write_5cyc_1I_1L]>,
   SchedVar<NoSchedPred,                    [A57Write_4cyc_1L]>
 ]>;
 def : InstRW<[A57WritePLD], (instregex "PLDrs", "PLDWrs")>;
 
 // --- Load multiple instructions ---
 foreach NumAddr = 1-8 in {
-  def A57LMAddrPred#NumAddr :
-    SchedPredicate<"(TII->getLDMVariableDefsSize(*MI)+1)/2 == "#NumAddr>;
+  def A57LMAddrPred#NumAddr : MCSchedPredicate<CheckAny<[
+                                CheckNumOperands<!add(!shl(NumAddr, 1), 2)>,
+                                CheckNumOperands<!add(!shl(NumAddr, 1), 3)>]>>;
 }
 
 def A57LDMOpsListNoregin : A57WriteLMOpsListType<
                 [A57Write_3cyc_1L, A57Write_3cyc_1L,
                  A57Write_4cyc_1L, A57Write_4cyc_1L,
                  A57Write_5cyc_1L, A57Write_5cyc_1L,
                  A57Write_6cyc_1L, A57Write_6cyc_1L,
                  A57Write_7cyc_1L, A57Write_7cyc_1L,
def A57WriteLDM_Upd : SchedWriteVariant<[
   SchedVar<A57LMAddrPred5,     A57LDMOpsList_Upd.Writes[0-10]>,
   SchedVar<A57LMAddrPred6,     A57LDMOpsList_Upd.Writes[0-12]>,
   SchedVar<A57LMAddrPred7,     A57LDMOpsList_Upd.Writes[0-14]>,
   SchedVar<A57LMAddrPred8,     A57LDMOpsList_Upd.Writes[0-16]>,
   SchedVar<NoSchedPred,        A57LDMOpsList_Upd.Writes[0-16]>
 ]> { let Variadic=1; }
 
 def A57WriteLDM : SchedWriteVariant<[
-  SchedVar<IsLdmBaseRegInList, [A57WriteLDMreginlist]>,
-  SchedVar<NoSchedPred,        [A57WriteLDMnoreginlist]>
+  SchedVar<IsLDMBaseRegInListPred, [A57WriteLDMreginlist]>,
+  SchedVar<NoSchedPred,            [A57WriteLDMnoreginlist]>
 ]> { let Variadic=1; }
 
 def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>;
 
 // TODO: no writeback latency defined in documentation (implemented as 1 cyc)
 def : InstRW<[A57WriteLDM_Upd],
   (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>;
 

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
 
 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
 
+template<class Inst>
+bool isLDMBaseRegInList(const Inst &MI) {
+  auto BaseReg = MI.getOperand(0).getReg();
+  for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
+    const auto &Op = MI.getOperand(i);
+    if (Op.isReg() && Op.getReg() == BaseReg)
+      return true;
+  }
+  return false;
+}
+
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,

llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

 # CHECK-NEXT:  1      2     1.00                        eor r4, r4, r5, ror #5
 # CHECK-NEXT:  1      2     1.00                        eor r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        eor r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        eor r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        eor r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        eor r4, r4, r5, rrx
 # CHECK-NEXT:  0      0     0.00    *      *      U     isb sy
 # CHECK-NEXT:  0      0     0.00    *      *      U     isb #0xa
-# CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  16     10    16.00   *                   ldmib r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  16     10    16.00   *                   ldmda r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  16     10    16.00   *                   ldmdb r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  32     10    16.00   *                   ldm r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  32     10    16.00   *                   ldmib r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  32     10    16.00   *                   ldmda r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  32     10    16.00   *                   ldmdb r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  6      5     6.00    *                   ldm r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  6      5     6.00    *                   ldmib r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  6      5     6.00    *                   ldmda r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  6      5     6.00    *                   ldmdb r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     6     8.00    *                   ldm r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     6     8.00    *                   ldmib r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     6     8.00    *                   ldmda r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     6     8.00    *                   ldmdb r2!, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  0      0     0.00    *      *      U     ldrexb  r3, [r4]
 # CHECK-NEXT:  0      0     0.00    *      *      U     ldrexh  r2, [r5]
 # CHECK-NEXT:  0      0     0.00    *      *      U     ldrex r1, [r7]
 # CHECK-NEXT:  0      0     0.00    *             U     ldrexd  r6, r7, [r8]
 # CHECK-NEXT:  1      3     1.00                        mla r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        mlas  r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        mlane r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        mlasne  r1, r2, r3, r4

 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #15
 # CHECK-NEXT:  2      4     1.00    *                   pop {r7}
-# CHECK-NEXT:  32     10    16.00   *                   pop {r7, r8, r9, r10}
+# CHECK-NEXT:  12     5     6.00    *                   pop {r7, r8, r9, r10}
 # CHECK-NEXT:  2      1     1.00           *            push  {r7}
-# CHECK-NEXT:  2      2     1.00           *            push  {r7, r8, r9, r10}
+# CHECK-NEXT:  2      3     1.00           *            push  {r7, r8, r9, r10}
 # CHECK-NEXT:  1      2     1.00                  U     qadd  r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                  U     qaddne  r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                  U     qadd16  r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                  U     qadd16gt  r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                  U     qadd8 r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                  U     qadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00                  U     qdadd r6, r7, r8
 # CHECK-NEXT:  2      3     1.00                  U     qdaddhi r6, r7, r8

 # CHECK-NEXT:  1      2     1.00                        ssat16  r2, #1, r7
 # CHECK-NEXT:  1      2     1.00                        ssat16  r3, #16, r5
 # CHECK-NEXT:  2      3     1.00    *      *      U     ssax  r2, r3, r4
 # CHECK-NEXT:  2      5     1.00    *      *      U     ssaxlt  r2, r3, r4
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub16  r1, r0, r6
 # CHECK-NEXT:  2      4     1.00    *      *      U     ssub16ne  r5, r3, r2
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub8 r9, r2, r4
 # CHECK-NEXT:  2      4     1.00    *      *      U     ssub8eq r5, r1, r2
-# CHECK-NEXT:  1      2     1.00           *            stm r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  1      2     1.00           *            stm r3, {r1, r3, r4, r5, r6, lr}
-# CHECK-NEXT:  1      2     1.00           *            stmib r4, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  1      2     1.00           *            stmda r5, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  1      2     1.00           *            stmdb r6, {r1, r3, r4, r5, r6, r8}
-# CHECK-NEXT:  1      2     1.00           *            stmdb sp, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  2      2     1.00           *            stm r8!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  2      2     1.00           *            stmib r9!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  2      2     1.00           *            stmda sp!, {r1, r3, r4, r5, r6}
-# CHECK-NEXT:  2      2     1.00           *            stmdb r0!, {r1, r5, r7, sp}
+# CHECK-NEXT:  1      3     1.00           *            stm r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      3     1.00           *            stm r3, {r1, r3, r4, r5, r6, lr}
+# CHECK-NEXT:  1      3     1.00           *            stmib r4, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      3     1.00           *            stmda r5, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      3     1.00           *            stmdb r6, {r1, r3, r4, r5, r6, r8}
+# CHECK-NEXT:  1      3     1.00           *            stmdb sp, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      4     1.00           *            stm r8!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      4     1.00           *            stmib r9!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      3     1.00           *            stmda sp!, {r1, r3, r4, r5, r6}
+# CHECK-NEXT:  2      3     1.00           *            stmdb r0!, {r1, r5, r7, sp}
 # CHECK-NEXT:  0      0     0.00    *      *      U     strexb  r1, r3, [r4]
 # CHECK-NEXT:  0      0     0.00    *      *      U     strexh  r4, r2, [r5]
 # CHECK-NEXT:  0      0     0.00    *      *      U     strex r2, r1, [r7]
 # CHECK-NEXT:  0      0     0.00           *      U     strexd  r6, r2, r3, [r8]
 # CHECK-NEXT:  0      0     0.00           *      U     strexd  sp, r0, r1, [r0]
 # CHECK-NEXT:  1      1     0.50                        sub r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        sub r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        sub r7, r8, #40, #2

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT: 8.00   159.00 159.00 171.00 496.00 12.00   -      -
+# CHECK-NEXT: 8.00   138.00 138.00 89.00  496.00 12.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #983040

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r4, r5, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r4, r5, rrx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     isb sy
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     isb #0xa
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmda r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmdb r2, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldm r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmib r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmda r2!, {r1, r3, r4, r5, r6, sp}
-# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmdb r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     6.00    -      -      -      -     ldm r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     6.00    -      -      -      -     ldmib r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     6.00    -      -      -      -     ldmda r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     6.00    -      -      -      -     ldmdb r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     4.00   4.00   8.00    -      -      -      -     ldm r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     4.00   4.00   8.00    -      -      -      -     ldmib r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     4.00   4.00   8.00    -      -      -      -     ldmda r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     4.00   4.00   8.00    -      -      -      -     ldmdb r2!, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexb  r3, [r4]
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexh  r2, [r5]
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrex r1, [r7]
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexd  r6, r7, [r8]
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mla r1, r2, r3, r4
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlas  r1, r2, r3, r4
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlane r1, r2, r3, r4
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlasne  r1, r2, r3, r4

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #15
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     pop {r7}
-# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     pop {r7, r8, r9, r10}
+# CHECK-NEXT:  -     3.00   3.00   6.00    -      -      -      -     pop {r7, r8, r9, r10}
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     push  {r7}
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     push  {r7, r8, r9, r10}
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd  r1, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qaddne  r1, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd16  r1, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd16gt  r1, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd8 r1, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd8le r1, r2, r3

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

 # CHECK-NEXT:  1      4     1.00    *                   ldrsh r4, [r6, r1]!
 # CHECK-NEXT:  1      4     1.00    *                   ldrsh r5, [r3, -r6]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrsh r6, [r9], r8
 # CHECK-NEXT:  2      4     1.00    *                   ldrsh r7, [r8], -r3
 # CHECK-NEXT:  2      4     1.00    *                   ldrsht  r5, [r6], #1
 # CHECK-NEXT:  2      4     1.00    *                   ldrsht  r3, [r8], #-12
 # CHECK-NEXT:  2      4     1.00    *                   ldrsht  r8, [r9], r5
 # CHECK-NEXT:  2      4     1.00    *                   ldrsht  r2, [r1], -r4
-# CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r1, r2, r4, r5, r6}
-# CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r1, r2, r4, r5, r6}
-# CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r1, r3, r4, r5, r6}
-# CHECK-NEXT:  16     10    16.00   *                   ldmib r2, {r1, r2}
-# CHECK-NEXT:  16     10    16.00   *                   ldmdb r2, {r1, r2}
-# CHECK-NEXT:  16     10    16.00   *                   ldmib r2, {r1, r3}
-# CHECK-NEXT:  16     10    16.00   *                   ldmib r2, {r1, r3, r5}
-# CHECK-NEXT:  16     10    16.00   *                   ldmib r2, {r1, r2, r5}
-# CHECK-NEXT:  16     10    16.00   *                   ldmdbeq r2, {r1, r2}
-# CHECK-NEXT:  16     10    16.00   *                   ldmibeq r2, {r1, r3}
+# CHECK-NEXT:  12     6     6.00    *                   ldm r2, {r1, r2, r4, r5, r6}
+# CHECK-NEXT:  12     6     6.00    *                   ldm r2, {r1, r2, r4, r5, r6}
+# CHECK-NEXT:  6      5     6.00    *                   ldm r2, {r1, r3, r4, r5, r6}
+# CHECK-NEXT:  4      4     2.00    *                   ldmib r2, {r1, r2}
+# CHECK-NEXT:  4      4     2.00    *                   ldmdb r2, {r1, r2}
+# CHECK-NEXT:  2      3     2.00    *                   ldmib r2, {r1, r3}
+# CHECK-NEXT:  4      4     4.00    *                   ldmib r2, {r1, r3, r5}
+# CHECK-NEXT:  8      5     4.00    *                   ldmib r2, {r1, r2, r5}
+# CHECK-NEXT:  4      4     2.00    *                   ldmdbeq r2, {r1, r2}
+# CHECK-NEXT:  2      3     2.00    *                   ldmibeq r2, {r1, r3}
 # CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
-# CHECK-NEXT:  16     10    16.00   *                   ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
+# CHECK-NEXT:  32     11    16.00   *                   ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
 # CHECK-NEXT:  1      1     1.00           *            str r8, [r12]
 # CHECK-NEXT:  1      1     1.00           *            str r7, [r1, #12]
 # CHECK-NEXT:  2      1     1.00           *            str r3, [r5, #40]!
 # CHECK-NEXT:  2      1     1.00           *            str r9, [sp], #4095
 # CHECK-NEXT:  2      1     1.00           *            str r1, [r7], #-128
 # CHECK-NEXT:  1      1     1.00           *            str r9, [r6, r3]
 # CHECK-NEXT:  1      1     1.00           *            str r8, [r0, -r2]
 # CHECK-NEXT:  2      1     1.00           *            str r7, [r1, r6]!

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     44.50  44.50  284.00 8.00   55.00   -      -
+# CHECK-NEXT:  -     63.50  63.50  160.00 8.00   55.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r5, [r7]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r6, [r3, #63]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r4, #4095]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r2], #30
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r3, [r1], #-30

 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrsh r4, [r6, r1]!
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrsh r5, [r3, -r6]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsh r6, [r9], r8
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsh r7, [r8], -r3
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsht  r5, [r6], #1
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsht  r3, [r8], #-12
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsht  r8, [r9], r5
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrsht  r2, [r1], -r4
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r1, r2, r4, r5, r6}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r1, r2, r4, r5, r6}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r1, r3, r4, r5, r6}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib r2, {r1, r2}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmdb r2, {r1, r2}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib r2, {r1, r3}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib r2, {r1, r3, r5}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib r2, {r1, r2, r5}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmdbeq r2, {r1, r2}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmibeq r2, {r1, r3}
+# CHECK-NEXT:  -     3.00   3.00   6.00    -      -      -      -     ldm r2, {r1, r2, r4, r5, r6}
+# CHECK-NEXT:  -     3.00   3.00   6.00    -      -      -      -     ldm r2, {r1, r2, r4, r5, r6}
+# CHECK-NEXT:  -      -      -     6.00    -      -      -      -     ldm r2, {r1, r3, r4, r5, r6}
+# CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldmib r2, {r1, r2}
+# CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldmdb r2, {r1, r2}
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldmib r2, {r1, r3}
+# CHECK-NEXT:  -      -      -     4.00    -      -      -      -     ldmib r2, {r1, r3, r5}
+# CHECK-NEXT:  -     2.00   2.00   4.00    -      -      -      -     ldmib r2, {r1, r2, r5}
+# CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldmdbeq r2, {r1, r2}
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldmibeq r2, {r1, r3}
 # CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
-# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldm r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r8, [r12]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r7, [r1, #12]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r3, [r5, #40]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r9, [sp], #4095
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r1, [r7], #-128
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r9, [r6, r3]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r8, [r0, -r2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r7, [r1, r6]!