This is a 1:1 port from the SelectionDAG code, modulo the recent optimizations for known non-zero shift amounts.
Additionally, no conversion between G_FSHL <-> G_FSHR are done yet.
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llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | ||
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6246–6247 | Doesn't this lowering work for vectors? | |
6252 | Is DstTy guaranteed to be the same type as the shift amount operand? | |
6254–6255 | Can't you just use auto ShAmt = MIRBuilder.buildWhatever(...) to avoid explicitly calling createGenericVirtualRegister here and below? | |
6255–6256 | Do we have something that will combine this UREM into an AND if BW is a power of two? |
I somehow forgot about this open review. I'll abandon this then.
Is there anything we can help with to get D76500 integrated? Since a recent upstream change we are seeing G_FSHL's being generated, which our GISel-only backend cannot handle.
The main thing holding that up is I haven't had time to address the problem of avoiding expanding the division in the divide-by-constant case
Doesn't this lowering work for vectors?