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Differential D89308

[ARM.td] Make instruction definitions visible to sched models
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Authored by evgeny777 on Oct 13 2020, 4:14 AM.

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Reviewers
SjoerdMeijer
dmgreen
javed.absar
atrick
Commits
rG2ad82b0ed1b4: [ARM.td] Make instruction definitions visible to sched models

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evgeny777 created this revision.Oct 13 2020, 4:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 13 2020, 4:14 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
evgeny777 requested review of this revision.Oct 13 2020, 4:14 AM
dmgreen accepted this revision.Oct 13 2020, 8:59 AM

Yeah sure, sounds useful. LGTM.

llvm/lib/Target/ARM/ARM.td
909

Can you add a "ARM Schedules" section, and move "ARM processors" below them.

This revision is now accepted and ready to land.Oct 13 2020, 8:59 AM
Closed by commit rG2ad82b0ed1b4: [ARM.td] Make instruction definitions visible to sched models (authored by evgeny777). · Explain WhyOct 13 2020, 11:59 PM
This revision was automatically updated to reflect the committed changes.
evgeny777 added a commit: rG2ad82b0ed1b4: [ARM.td] Make instruction definitions visible to sched models.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
37 lines
11 lines
4 lines

Diff 297817

llvm/lib/Target/ARM/ARM.td

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ARM schedules. // ARM schedules.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
include "ARMPredicates.td" include "ARMPredicates.td"
include "ARMSchedule.td" include "ARMSchedule.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "ARMRegisterInfo.td"
include "ARMRegisterBanks.td"
include "ARMCallingConv.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "ARMInstrInfo.td"
def ARMInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// ARM processors // ARM processors
dmgreenUnsubmitted
Not Done
ReplyInline Actions

Can you add a "ARM Schedules" section, and move "ARM processors" below them.

dmgreen: Can you add a "ARM Schedules" section, and move "ARM processors" below them.
// //
include "ARMScheduleV6.td"
include "ARMScheduleA8.td"
include "ARMScheduleA9.td"
include "ARMScheduleSwift.td"
include "ARMScheduleR52.td"
include "ARMScheduleA57.td"
include "ARMScheduleM4.td"
// Dummy CPU, used to target architectures // Dummy CPU, used to target architectures
def : ProcessorModel<"generic", CortexA8Model, []>; def : ProcessorModel<"generic", CortexA8Model, []>;
// FIXME: Several processors below are not using their own scheduler // FIXME: Several processors below are not using their own scheduler
// model, but one of similar/previous processor. These should be fixed. // model, but one of similar/previous processor. These should be fixed.
def : ProcNoItin<"arm8", [ARMv4]>; def : ProcNoItin<"arm8", [ARMv4]>;
▲ Show 20 Lines • Show All 387 Lines • ▼ Show 20 Linesdef : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
FeatureUseMISched, FeatureUseMISched,
FeatureFPAO]>; FeatureFPAO]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "ARMRegisterInfo.td"
include "ARMRegisterBanks.td"
include "ARMCallingConv.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "ARMInstrInfo.td"
def ARMInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing // Declare the target which we are implementing
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ARMAsmWriter : AsmWriter { def ARMAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter"; string AsmWriterClassName = "InstPrinter";
int PassSubtarget = 1; int PassSubtarget = 1;
int Variant = 0; int Variant = 0;
bit isMCAsmWriter = 1; bit isMCAsmWriter = 1;
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llvm/lib/Target/ARM/ARMSchedule.td

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def IIC_VTB2 : InstrItinClass; def IIC_VTB2 : InstrItinClass;
def IIC_VTB3 : InstrItinClass; def IIC_VTB3 : InstrItinClass;
def IIC_VTB4 : InstrItinClass; def IIC_VTB4 : InstrItinClass;
def IIC_VTBX1 : InstrItinClass; def IIC_VTBX1 : InstrItinClass;
def IIC_VTBX2 : InstrItinClass; def IIC_VTBX2 : InstrItinClass;
def IIC_VTBX3 : InstrItinClass; def IIC_VTBX3 : InstrItinClass;
def IIC_VTBX4 : InstrItinClass; def IIC_VTBX4 : InstrItinClass;
def IIC_VDOTPROD : InstrItinClass; def IIC_VDOTPROD : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
include "ARMScheduleV6.td"
include "ARMScheduleA8.td"
include "ARMScheduleA9.td"
include "ARMScheduleSwift.td"
include "ARMScheduleR52.td"
include "ARMScheduleA57.td"
include "ARMScheduleM4.td"

llvm/lib/Target/ARM/ARMScheduleA9.td

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def : ReadAdvance<ReadFPMAC, 0>; def : ReadAdvance<ReadFPMAC, 0>;
// ===---------------------------------------------------------------------===// // ===---------------------------------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types. // Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types.
// //
def : InstRW< [WriteALU], def : InstRW< [WriteALU],
(instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr", (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr",
"BICrr")>; "BICrr")>;
def : InstRW< [WriteALUsi], (instregex "ANDrsi", "ORRrsi", "EORrsi", "BICrsi")>; def : InstRW< [WriteALUsi], (instrs ANDrsi, ORRrsi, EORrsi, BICrsi)>;
def : InstRW< [WriteALUsr], (instregex "ANDrsr", "ORRrsr", "EORrsr", "BICrsr")>; def : InstRW< [WriteALUsr], (instrs ANDrsr, ORRrsr, EORrsr, BICrsr)>;
def : SchedAlias<WriteCMP, A9WriteALU>; def : SchedAlias<WriteCMP, A9WriteALU>;
def : SchedAlias<WriteCMPsi, A9WriteALU>; def : SchedAlias<WriteCMPsi, A9WriteALU>;
def : SchedAlias<WriteCMPsr, A9WriteALU>; def : SchedAlias<WriteCMPsr, A9WriteALU>;
def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi", def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi",
"MOVCCsr")>; "MOVCCsr")>;
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