[GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.

[aemerson]

Summary

It's probably better to split these into separate G_FADD/G_FMUL + G_VECREDUCE operations in the translator rather than carrying the scalar around. The majority of the time it'll get simplified away as the scalars are probably identity values.

[aemerson]

Only do this for the relaxed ordering ones. If we were to split the op for the sequential variants, the commutative G_FADD would lose the associativity of the intrinsic.

[aemerson]

ping

[paquette]

LGTM

llvm/include/llvm/Target/GenericOpcodes.td

def G_SHUFFLE_VECTOR: GenericInstruction {
   let InOperandList = (ins type1:$v1, type1:$v2, unknown:$mask);
   let hasSideEffects = 0;
 }
 
 //------------------------------------------------------------------------------
 // Vector reductions
 //------------------------------------------------------------------------------
 
-def G_VECREDUCE_SEQ_FADD : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
-def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
+class VectorReduction : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
+  let InOperandList = (ins type1:$v);
   let hasSideEffects = 0;
 }
 
-def G_VECREDUCE_FADD : GenericInstruction {
+def G_VECREDUCE_SEQ_FADD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$acc, type2:$v);
   let hasSideEffects = 0;
 }
 
-def G_VECREDUCE_FMUL : GenericInstruction {
+def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$acc, type2:$v);
   let hasSideEffects = 0;
 }
 
-class VectorReduction : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$v);
-  let hasSideEffects = 0;
-}
+def G_VECREDUCE_FADD : VectorReduction;
+def G_VECREDUCE_FMUL : VectorReduction;
 
 def G_VECREDUCE_FMAX : VectorReduction;
 def G_VECREDUCE_FMIN : VectorReduction;
 
 def G_VECREDUCE_ADD : VectorReduction;
 def G_VECREDUCE_MUL : VectorReduction;
 def G_VECREDUCE_AND : VectorReduction;
 def G_VECREDUCE_OR : VectorReduction;

llvm/lib/CodeGen/MachineVerifier.cpp

case TargetOpcode::G_MEMSET: {
     }
 
     if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
       report("inconsistent memset address space", MI);
 
     break;
   }
   case TargetOpcode::G_VECREDUCE_SEQ_FADD:
-  case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
-  case TargetOpcode::G_VECREDUCE_FADD:
-  case TargetOpcode::G_VECREDUCE_FMUL: {
+  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
     LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
     if (!DstTy.isScalar())
       report("Vector reduction requires a scalar destination type", MI);
     if (!Src1Ty.isScalar())
-      report("FADD/FMUL vector reduction requires a scalar 1st operand", MI);
+      report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
     if (!Src2Ty.isVector())
-      report("FADD/FMUL vector reduction must have a vector 2nd operand", MI);
+      report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
     break;
   }
+  case TargetOpcode::G_VECREDUCE_FADD:
+  case TargetOpcode::G_VECREDUCE_FMUL:
   case TargetOpcode::G_VECREDUCE_FMAX:
   case TargetOpcode::G_VECREDUCE_FMIN:
   case TargetOpcode::G_VECREDUCE_ADD:
   case TargetOpcode::G_VECREDUCE_MUL:
   case TargetOpcode::G_VECREDUCE_AND:
   case TargetOpcode::G_VECREDUCE_OR:
   case TargetOpcode::G_VECREDUCE_XOR:
   case TargetOpcode::G_VECREDUCE_SMAX:

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_VECREDUCE_SEQ_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECREDUCE_SEQ_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECREDUCE_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECREDUCE_FMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined

llvm/test/MachineVerifier/test_vector_reductions.mir

bb.0:
 
     %vec_v2s64:_(<2 x s64>) = IMPLICIT_DEF
     %scalar_s64:_(s64) = IMPLICIT_DEF
 
     %seq_fadd:_(<2 x s64>) = G_VECREDUCE_SEQ_FADD %scalar_s64, %vec_v2s64
     ; CHECK: Bad machine code: Vector reduction requires a scalar destination type
 
     %dst:_(s64) = G_VECREDUCE_SEQ_FADD %vec_v2s64, %vec_v2s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction requires a scalar 1st operand
+    ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction requires a scalar 1st operand
 
     %dst:_(s64) = G_VECREDUCE_SEQ_FADD %scalar_s64, %scalar_s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction must have a vector 2nd operand
+    ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
 
     %dst2:_(s64) = G_VECREDUCE_MUL %scalar_s64
     ; CHECK: Bad machine code: Vector reduction requires vector source
 ...