[SystemZ] Use LA instead of AGR in eliminateFrameIndex().

[jonpa]

Summary

Since AGR clobbers CC it should not be used here.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47736.

[uweigand]

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

325

I think it may be better from a micro-architecture perspective to use %r15 as the base pointer in the instruction here, i.e. swap the two source registers. So we should get something like

la %r1, 0(%r1, %r15)

[cuviper]

I applied this all the way back to my original issue and confirmed that the coreos-installer test now passes -- thanks!
(I'll wait for the final version of this patch before I actually submit this to LLVM builds for Rust/Fedora/etc.)

[jonpa]

Updated per review.

[uweigand]

LGTM, thanks!

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

if (MI->getDesc().TSFlags & SystemZII::HasIndex
       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
       if (LAOpcode)
         BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
           .addReg(BasePtr).addImm(HighOffset).addReg(0);
       else {
         // Load the high offset into the scratch register and use it as
         // an index.
         TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
-        BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
-          .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
+        BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
+          .addReg(ScratchReg, RegState::Kill).addImm(0).addReg(BasePtr);
       }
 
       // Use the scratch register as the base.  It then dies here.
       MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
                                                     false, false, true);
     }
   }
   MI->setDesc(TII->get(OpcodeForOffset));

llvm/test/CodeGen/SystemZ/frame-14.ll

 }
 
 ; Test the first out-of-range offset.  We can't use an index register here,
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4() {
 ; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: mvi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: mvi 0(%r1), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
   %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
   %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
 }
 
 ; Add 4095 to the previous offset, to test the other end of the MVI range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5() {
 ; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: mvi 4095(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: mvi 4095(%r1), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
   %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103
   %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
 }
 
 ; Test the next offset after that, which uses MVIY instead of MVI.
 define void @f6() {
 ; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: mviy 4096(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: mviy 4096(%r1), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
   %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104
   %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
 }
 
 ; Now try an offset of 524287 from the start of the object, with the
 ; object being at offset 1048576 (1 << 20).  The backend prefers to create
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using MVI in more cases than 0x40000 anchors would.
 define void @f7() {
 ; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: mviy 65535(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: mviy 65535(%r1), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [1048400 x i8], align 8
   %region2 = alloca [1048400 x i8], align 8
   %ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287
   %ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
 }
 
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
 ; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: mvi 7(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: mvi 7(%r1), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [1048408 x i8], align 8
   %region2 = alloca [1048408 x i8], align 8
   %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287
   %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2

 
 ; Repeat f4 in a case that needs the emergency spill slots (because all
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
 ; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
-; CHECK-NOFP: agr [[REGISTER]], %r15
+; CHECK-NOFP: la [[REGISTER]], 0(%r15,[[REGISTER]])
 ; CHECK-NOFP: mvi 0([[REGISTER]]), 42
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
-; CHECK-FP: agr [[REGISTER]], %r11
+; CHECK-FP: la [[REGISTER]], 0(%r11,[[REGISTER]])
 ; CHECK-FP: mvi 0([[REGISTER]]), 42
 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
   %i0 = load volatile i32, i32 *%vptr
   %i1 = load volatile i32, i32 *%vptr
   %i3 = load volatile i32, i32 *%vptr
   %i4 = load volatile i32, i32 *%vptr
   %i5 = load volatile i32, i32 *%vptr

 ; NOFP case needs are the emergency ones, so the offsets are the same as for f4.
 ; The FP case needs to spill an extra register and is too dependent on
 ; register allocation heuristics for a stable test.
 define void @f11(i32 *%vptr) {
 ; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
-; CHECK-NOFP: agr [[REGISTER]], %r15
+; CHECK-NOFP: la [[REGISTER]], 0(%r15,[[REGISTER]])
 ; CHECK-NOFP: mvi 0([[REGISTER]]), 42
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
   %i0 = load volatile i32, i32 *%vptr
   %i1 = load volatile i32, i32 *%vptr
   %i3 = load volatile i32, i32 *%vptr
   %i4 = load volatile i32, i32 *%vptr

llvm/test/CodeGen/SystemZ/frame-16.ll

; CHECK-FP: br %r14
   store volatile i32 %i14, i32 *%vptr
   ret void
 }
 
 ; Repeat f4 in a case where the index register is already occupied.
 define void @f12(i8 %byte, i64 %index) {
 ; CHECK-NOFP-LABEL: f12:
 ; CHECK-NOFP: llilh %r1, 8
-; CHECK-NOFP: agr %r1, %r15
+; CHECK-NOFP: la %r1, 0(%r15,%r1)
 ; CHECK-NOFP: stc %r2, 0(%r3,%r1)
 ; CHECK-NOFP: br %r14
 ;
 ; CHECK-FP-LABEL: f12:
 ; CHECK-FP: llilh %r1, 8
-; CHECK-FP: agr %r1, %r11
+; CHECK-FP: la %r1, 0(%r11,%r1)
 ; CHECK-FP: stc %r2, 0(%r3,%r1)
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
   %index1 = add i64 %index, 8
   %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 %index1
   %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 %index1
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
 }