[NFC][MC] Type uses of MCRegUnitIterator as MCRegister

[mtrofin]

Summary

This is one of many subsequent similar changes. Note that we're ok with
the parameter being typed as MCPhysReg, as MCPhysReg -> MCRegister is a
correct conversion; Register -> MCRegister assumes the former is indeed
physical, so we stop relying on the implicit conversion and use the
explicit, value-asserting asMCReg().

llvm/include/llvm/CodeGen/LiveIntervals.h

void removeRegUnit(unsigned Unit) {
       delete RegUnitRanges[Unit];
       RegUnitRanges[Unit] = nullptr;
     }
 
     /// Remove associated live ranges for the register units associated with \p
     /// Reg. Subsequent uses should rely on on-demand recomputation.  \note This
     /// method can result in inconsistent liveness tracking if multiple phyical
     /// registers share a regunit, and should be used cautiously.
-    void removeAllRegUnitsForPhysReg(unsigned Reg) {
+    void removeAllRegUnitsForPhysReg(MCRegister Reg) {
       for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
         removeRegUnit(*Units);
     }
 
     /// Remove value numbers and related live segments starting at position
     /// \p Pos that are part of any liverange of physical register \p Reg or one
     /// of its subregisters.
     void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

public:
   /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
   /// SubB.
   LaneBitmask getCoveringLanes() const { return CoveringLanes; }
 
   /// Returns true if the two registers are equal or alias each other.
   /// The registers may be virtual registers.
   bool regsOverlap(Register regA, Register regB) const {
     if (regA == regB) return true;
-    if (regA.isVirtual() || regB.isVirtual())
+    if (!regA.isPhysical() || !regB.isPhysical())
       return false;
 
     // Regunits are numerically ordered. Find a common unit.
-    MCRegUnitIterator RUA(regA, this);
-    MCRegUnitIterator RUB(regB, this);
+    MCRegUnitIterator RUA(regA.asMCReg(), this);
+    MCRegUnitIterator RUB(regB.asMCReg(), this);
     do {
       if (*RUA == *RUB) return true;
       if (*RUA < *RUB) ++RUA;
       else             ++RUB;
     } while (RUA.isValid() && RUB.isValid());
     return false;
   }
 

llvm/lib/CodeGen/BreakFalseDeps.cpp

bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
 
   MachineOperand &MO = MI->getOperand(OpIdx);
   assert(MO.isUndef() && "Expected undef machine operand");
 
   // We can't change registers that aren't renamable.
   if (!MO.isRenamable())
     return false;
 
-  Register OriginalReg = MO.getReg();
+  MCRegister OriginalReg = MO.getReg().asMCReg();
 
   // Update only undef operands that have reg units that are mapped to one root.
   for (MCRegUnitIterator Unit(OriginalReg, TRI); Unit.isValid(); ++Unit) {
     unsigned NumRoots = 0;
     for (MCRegUnitRootIterator Root(*Unit, TRI); Root.isValid(); ++Root) {
       NumRoots++;
       if (NumRoots > 1)
         return false;

llvm/lib/CodeGen/EarlyIfConversion.cpp

if (MO.isRegMask()) {
       return false;
     }
     if (!MO.isReg())
       continue;
     Register Reg = MO.getReg();
 
     // Remember clobbered regunits.
     if (MO.isDef() && Register::isPhysicalRegister(Reg))
-      for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
+      for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
+           ++Units)
         ClobberedRegUnits.set(*Units);
 
     if (!MO.readsReg() || !Register::isVirtualRegister(Reg))
       continue;
     MachineInstr *DefMI = MRI->getVRegDef(Reg);
     if (!DefMI || DefMI->getParent() != Head)
       continue;
     if (InsertAfter.insert(DefMI).second)

 ///
 /// This function sets InsertionPoint and returns true when successful, it
 /// returns false if no valid insertion point could be found.
 ///
 bool SSAIfConv::findInsertionPoint() {
   // Keep track of live regunits before the current position.
   // Only track RegUnits that are also in ClobberedRegUnits.
   LiveRegUnits.clear();
-  SmallVector<unsigned, 8> Reads;
+  SmallVector<MCRegister, 8> Reads;
   MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
   MachineBasicBlock::iterator I = Head->end();
   MachineBasicBlock::iterator B = Head->begin();
   while (I != B) {
     --I;
     // Some of the conditional code depends in I.
     if (InsertAfter.count(&*I)) {
       LLVM_DEBUG(dbgs() << "Can't insert code after " << *I);
       return false;
     }
 
     // Update live regunits.
     for (const MachineOperand &MO : I->operands()) {
       // We're ignoring regmask operands. That is conservatively correct.
       if (!MO.isReg())
         continue;
       Register Reg = MO.getReg();
       if (!Register::isPhysicalRegister(Reg))
         continue;
       // I clobbers Reg, so it isn't live before I.
       if (MO.isDef())
-        for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
+        for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
+             ++Units)
           LiveRegUnits.erase(*Units);
       // Unless I reads Reg.
       if (MO.readsReg())
-        Reads.push_back(Reg);
+        Reads.push_back(Reg.asMCReg());
     }
     // Anything read by I is live before I.
     while (!Reads.empty())
       for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
            ++Units)
         if (ClobberedRegUnits.test(*Units))
           LiveRegUnits.insert(*Units);